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ea1cca0268
Add clock definitions for the main clock and reset controllers of MT6735 (apmixedsys, topckgen, infracfg and pericfg). Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20241017071708.38663-2-y.oudjana@protonmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
28 lines
917 B
C
28 lines
917 B
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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#ifndef _DT_BINDINGS_RESET_MT6735_INFRACFG_H
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#define _DT_BINDINGS_RESET_MT6735_INFRACFG_H
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#define MT6735_INFRA_RST0_EMI_REG 0
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#define MT6735_INFRA_RST0_DRAMC0_AO 1
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#define MT6735_INFRA_RST0_AP_CIRQ_EINT 2
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#define MT6735_INFRA_RST0_APXGPT 3
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#define MT6735_INFRA_RST0_SCPSYS 4
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#define MT6735_INFRA_RST0_KP 5
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#define MT6735_INFRA_RST0_PMIC_WRAP 6
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#define MT6735_INFRA_RST0_CLDMA_AO_TOP 7
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#define MT6735_INFRA_RST0_USBSIF_TOP 8
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#define MT6735_INFRA_RST0_EMI 9
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#define MT6735_INFRA_RST0_CCIF 10
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#define MT6735_INFRA_RST0_DRAMC0 11
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#define MT6735_INFRA_RST0_EMI_AO_REG 12
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#define MT6735_INFRA_RST0_CCIF_AO 13
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#define MT6735_INFRA_RST0_TRNG 14
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#define MT6735_INFRA_RST0_SYS_CIRQ 15
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#define MT6735_INFRA_RST0_GCE 16
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#define MT6735_INFRA_RST0_M4U 17
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#define MT6735_INFRA_RST0_CCIF1 18
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#define MT6735_INFRA_RST0_CLDMA_TOP_PD 19
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#endif
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