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ea1cca0268
Add clock definitions for the main clock and reset controllers of MT6735 (apmixedsys, topckgen, infracfg and pericfg). Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20241017071708.38663-2-y.oudjana@protonmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
32 lines
973 B
C
32 lines
973 B
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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#ifndef _DT_BINDINGS_RESET_MT6735_PERICFG_H
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#define _DT_BINDINGS_RESET_MT6735_PERICFG_H
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#define MT6735_PERI_RST0_UART0 0
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#define MT6735_PERI_RST0_UART1 1
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#define MT6735_PERI_RST0_UART2 2
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#define MT6735_PERI_RST0_UART3 3
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#define MT6735_PERI_RST0_UART4 4
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#define MT6735_PERI_RST0_BTIF 5
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#define MT6735_PERI_RST0_DISP_PWM_PERI 6
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#define MT6735_PERI_RST0_PWM 7
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#define MT6735_PERI_RST0_AUXADC 8
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#define MT6735_PERI_RST0_DMA 9
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#define MT6735_PERI_RST0_IRDA 10
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#define MT6735_PERI_RST0_IRTX 11
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#define MT6735_PERI_RST0_THERM 12
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#define MT6735_PERI_RST0_MSDC2 13
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#define MT6735_PERI_RST0_MSDC3 14
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#define MT6735_PERI_RST0_MSDC0 15
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#define MT6735_PERI_RST0_MSDC1 16
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#define MT6735_PERI_RST0_I2C0 17
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#define MT6735_PERI_RST0_I2C1 18
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#define MT6735_PERI_RST0_I2C2 19
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#define MT6735_PERI_RST0_I2C3 20
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#define MT6735_PERI_RST0_USB 21
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#define MT6735_PERI_RST1_SPI0 22
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#endif
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