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a0bbe77faf
Add support for the time slot assigner (TSA) available in some PowerQUICC SoC that uses a QUICC Engine (QE) block such as MPC8321. This QE TSA is similar to the CPM TSA except that it uses UCCs (Unified Communication Controllers) instead of SCCs (Serial Communication Controllers). Also, compared against the CPM TSA, this QE TSA can handle up to 4 TDMs instead of 2 and allows to configure the logic level of sync signals. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/20240808071132.149251-8-herve.codina@bootlin.com Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
14 lines
308 B
C
14 lines
308 B
C
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
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#ifndef __DT_BINDINGS_SOC_FSL_QE_TSA_H
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#define __DT_BINDINGS_SOC_FSL_QE_TSA_H
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#define FSL_QE_TSA_NU 0
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#define FSL_QE_TSA_UCC1 1
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#define FSL_QE_TSA_UCC2 2
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#define FSL_QE_TSA_UCC3 3
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#define FSL_QE_TSA_UCC4 4
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#define FSL_QE_TSA_UCC5 5
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#endif
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