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00eb2b8a07
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Update the comment to include 'may'. Fixes: fea251b6a5db ("iio: addac: add AD74413R driver") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Cc: Cosmin Tanislav <cosmin.tanislav@analog.com> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-41-jic23@kernel.org