Dan Williams 2aec048cdc ioat3: hardware version 3.2 register / descriptor definitions ...

ioat3.2 adds raid5 and raid6 offload capabilities.

Signed-off-by: Tom Picard <tom.s.picard@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>

2009-09-08 17:42:54 -07:00

..

ioat

ioat3: hardware version 3.2 register / descriptor definitions

2009-09-08 17:42:54 -07:00

ipu

dma: fix ipu_idmac.c to not discard the last queued buffer

2009-05-12 14:41:48 -07:00

dmaengine.c

dmaengine, async_tx: add a "no channel switch" allocator

2009-09-08 17:42:51 -07:00

dmatest.c

dmaengine, async_tx: support alignment checks

2009-09-08 17:42:53 -07:00

dw_dmac_regs.h

dw_dmac: add cyclic API to DW DMA driver

2009-04-01 15:42:34 -07:00

dw_dmac.c

Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx

2009-04-03 12:13:45 -07:00

fsldma.c

fsldma: Fix compile warnings

2009-05-27 13:40:00 -07:00

fsldma.h

fsldma: allow Freescale Elo DMA driver to be compiled as a module

2008-09-26 17:00:11 -07:00

iop-adma.c

dmaengine: cleanup unused transaction types

2009-09-08 17:42:52 -07:00

iovlock.c

net_dma: poll for a descriptor after allocation failure

2009-09-08 17:38:54 -07:00

Kconfig

dmaengine, async_tx: add a "no channel switch" allocator

2009-09-08 17:42:51 -07:00

Makefile

ioat: move to drivers/dma/ioat/

2009-07-28 14:32:12 -07:00

mv_xor.c

dmaengine: initialize tx_list in dma_async_tx_descriptor_init

2009-03-25 09:13:24 -07:00

mv_xor.h

dmaengine: DMA engine driver for Marvell XOR engine

2008-07-08 11:58:36 -07:00