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546b366600
Those are the registers directly accessible through the MMIO range. FW registers are exposed in panthor_fw.h. v6: - Add Maxime's and Heiko's acks v4: - Add the CORE_FEATURES register (needed for GPU variants) - Add Steve's R-b v3: - Add macros to extract GPU ID info - Formatting changes - Remove AS_TRANSCFG_ADRMODE_LEGACY - it doesn't exist post-CSF - Remove CSF_GPU_LATEST_FLUSH_ID_DEFAULT - Add GPU_L2_FEATURES_LINE_SIZE for extracting the GPU cache line size Co-developed-by: Steven Price <steven.price@arm.com> Signed-off-by: Steven Price <steven.price@arm.com> Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Acked-by: Steven Price <steven.price@arm.com> # MIT+GPL2 relicensing,Arm Acked-by: Grant Likely <grant.likely@linaro.org> # MIT+GPL2 relicensing,Linaro Acked-by: Boris Brezillon <boris.brezillon@collabora.com> # MIT+GPL2 relicensing,Collabora Reviewed-by: Steven Price <steven.price@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/20240229162230.2634044-3-boris.brezillon@collabora.com
240 lines
8.1 KiB
C
240 lines
8.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 or MIT */
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/* Copyright 2018 Marty E. Plummer <hanetzer@startmail.com> */
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/* Copyright 2019 Linaro, Ltd, Rob Herring <robh@kernel.org> */
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/* Copyright 2023 Collabora ltd. */
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/*
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* Register definitions based on mali_kbase_gpu_regmap.h and
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* mali_kbase_gpu_regmap_csf.h
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* (C) COPYRIGHT 2010-2022 ARM Limited. All rights reserved.
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*/
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#ifndef __PANTHOR_REGS_H__
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#define __PANTHOR_REGS_H__
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#define GPU_ID 0x0
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#define GPU_ARCH_MAJOR(x) ((x) >> 28)
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#define GPU_ARCH_MINOR(x) (((x) & GENMASK(27, 24)) >> 24)
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#define GPU_ARCH_REV(x) (((x) & GENMASK(23, 20)) >> 20)
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#define GPU_PROD_MAJOR(x) (((x) & GENMASK(19, 16)) >> 16)
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#define GPU_VER_MAJOR(x) (((x) & GENMASK(15, 12)) >> 12)
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#define GPU_VER_MINOR(x) (((x) & GENMASK(11, 4)) >> 4)
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#define GPU_VER_STATUS(x) ((x) & GENMASK(3, 0))
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#define GPU_L2_FEATURES 0x4
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#define GPU_L2_FEATURES_LINE_SIZE(x) (1 << ((x) & GENMASK(7, 0)))
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#define GPU_CORE_FEATURES 0x8
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#define GPU_TILER_FEATURES 0xC
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#define GPU_MEM_FEATURES 0x10
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#define GROUPS_L2_COHERENT BIT(0)
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#define GPU_MMU_FEATURES 0x14
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#define GPU_MMU_FEATURES_VA_BITS(x) ((x) & GENMASK(7, 0))
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#define GPU_MMU_FEATURES_PA_BITS(x) (((x) >> 8) & GENMASK(7, 0))
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#define GPU_AS_PRESENT 0x18
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#define GPU_CSF_ID 0x1C
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#define GPU_INT_RAWSTAT 0x20
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#define GPU_INT_CLEAR 0x24
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#define GPU_INT_MASK 0x28
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#define GPU_INT_STAT 0x2c
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#define GPU_IRQ_FAULT BIT(0)
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#define GPU_IRQ_PROTM_FAULT BIT(1)
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#define GPU_IRQ_RESET_COMPLETED BIT(8)
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#define GPU_IRQ_POWER_CHANGED BIT(9)
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#define GPU_IRQ_POWER_CHANGED_ALL BIT(10)
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#define GPU_IRQ_CLEAN_CACHES_COMPLETED BIT(17)
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#define GPU_IRQ_DOORBELL_MIRROR BIT(18)
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#define GPU_IRQ_MCU_STATUS_CHANGED BIT(19)
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#define GPU_CMD 0x30
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#define GPU_CMD_DEF(type, payload) ((type) | ((payload) << 8))
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#define GPU_SOFT_RESET GPU_CMD_DEF(1, 1)
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#define GPU_HARD_RESET GPU_CMD_DEF(1, 2)
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#define CACHE_CLEAN BIT(0)
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#define CACHE_INV BIT(1)
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#define GPU_FLUSH_CACHES(l2, lsc, oth) \
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GPU_CMD_DEF(4, ((l2) << 0) | ((lsc) << 4) | ((oth) << 8))
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#define GPU_STATUS 0x34
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#define GPU_STATUS_ACTIVE BIT(0)
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#define GPU_STATUS_PWR_ACTIVE BIT(1)
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#define GPU_STATUS_PAGE_FAULT BIT(4)
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#define GPU_STATUS_PROTM_ACTIVE BIT(7)
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#define GPU_STATUS_DBG_ENABLED BIT(8)
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#define GPU_FAULT_STATUS 0x3C
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#define GPU_FAULT_ADDR_LO 0x40
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#define GPU_FAULT_ADDR_HI 0x44
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#define GPU_PWR_KEY 0x50
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#define GPU_PWR_KEY_UNLOCK 0x2968A819
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#define GPU_PWR_OVERRIDE0 0x54
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#define GPU_PWR_OVERRIDE1 0x58
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#define GPU_TIMESTAMP_OFFSET_LO 0x88
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#define GPU_TIMESTAMP_OFFSET_HI 0x8C
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#define GPU_CYCLE_COUNT_LO 0x90
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#define GPU_CYCLE_COUNT_HI 0x94
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#define GPU_TIMESTAMP_LO 0x98
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#define GPU_TIMESTAMP_HI 0x9C
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#define GPU_THREAD_MAX_THREADS 0xA0
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#define GPU_THREAD_MAX_WORKGROUP_SIZE 0xA4
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#define GPU_THREAD_MAX_BARRIER_SIZE 0xA8
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#define GPU_THREAD_FEATURES 0xAC
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#define GPU_TEXTURE_FEATURES(n) (0xB0 + ((n) * 4))
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#define GPU_SHADER_PRESENT_LO 0x100
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#define GPU_SHADER_PRESENT_HI 0x104
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#define GPU_TILER_PRESENT_LO 0x110
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#define GPU_TILER_PRESENT_HI 0x114
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#define GPU_L2_PRESENT_LO 0x120
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#define GPU_L2_PRESENT_HI 0x124
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#define SHADER_READY_LO 0x140
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#define SHADER_READY_HI 0x144
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#define TILER_READY_LO 0x150
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#define TILER_READY_HI 0x154
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#define L2_READY_LO 0x160
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#define L2_READY_HI 0x164
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#define SHADER_PWRON_LO 0x180
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#define SHADER_PWRON_HI 0x184
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#define TILER_PWRON_LO 0x190
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#define TILER_PWRON_HI 0x194
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#define L2_PWRON_LO 0x1A0
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#define L2_PWRON_HI 0x1A4
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#define SHADER_PWROFF_LO 0x1C0
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#define SHADER_PWROFF_HI 0x1C4
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#define TILER_PWROFF_LO 0x1D0
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#define TILER_PWROFF_HI 0x1D4
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#define L2_PWROFF_LO 0x1E0
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#define L2_PWROFF_HI 0x1E4
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#define SHADER_PWRTRANS_LO 0x200
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#define SHADER_PWRTRANS_HI 0x204
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#define TILER_PWRTRANS_LO 0x210
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#define TILER_PWRTRANS_HI 0x214
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#define L2_PWRTRANS_LO 0x220
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#define L2_PWRTRANS_HI 0x224
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#define SHADER_PWRACTIVE_LO 0x240
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#define SHADER_PWRACTIVE_HI 0x244
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#define TILER_PWRACTIVE_LO 0x250
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#define TILER_PWRACTIVE_HI 0x254
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#define L2_PWRACTIVE_LO 0x260
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#define L2_PWRACTIVE_HI 0x264
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#define GPU_REVID 0x280
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#define GPU_COHERENCY_FEATURES 0x300
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#define GPU_COHERENCY_PROT_BIT(name) BIT(GPU_COHERENCY_ ## name)
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#define GPU_COHERENCY_PROTOCOL 0x304
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#define GPU_COHERENCY_ACE 0
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#define GPU_COHERENCY_ACE_LITE 1
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#define GPU_COHERENCY_NONE 31
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#define MCU_CONTROL 0x700
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#define MCU_CONTROL_ENABLE 1
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#define MCU_CONTROL_AUTO 2
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#define MCU_CONTROL_DISABLE 0
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#define MCU_STATUS 0x704
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#define MCU_STATUS_DISABLED 0
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#define MCU_STATUS_ENABLED 1
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#define MCU_STATUS_HALT 2
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#define MCU_STATUS_FATAL 3
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/* Job Control regs */
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#define JOB_INT_RAWSTAT 0x1000
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#define JOB_INT_CLEAR 0x1004
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#define JOB_INT_MASK 0x1008
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#define JOB_INT_STAT 0x100c
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#define JOB_INT_GLOBAL_IF BIT(31)
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#define JOB_INT_CSG_IF(x) BIT(x)
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/* MMU regs */
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#define MMU_INT_RAWSTAT 0x2000
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#define MMU_INT_CLEAR 0x2004
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#define MMU_INT_MASK 0x2008
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#define MMU_INT_STAT 0x200c
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/* AS_COMMAND register commands */
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#define MMU_BASE 0x2400
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#define MMU_AS_SHIFT 6
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#define MMU_AS(as) (MMU_BASE + ((as) << MMU_AS_SHIFT))
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#define AS_TRANSTAB_LO(as) (MMU_AS(as) + 0x0)
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#define AS_TRANSTAB_HI(as) (MMU_AS(as) + 0x4)
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#define AS_MEMATTR_LO(as) (MMU_AS(as) + 0x8)
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#define AS_MEMATTR_HI(as) (MMU_AS(as) + 0xC)
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#define AS_MEMATTR_AARCH64_INNER_ALLOC_IMPL (2 << 2)
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#define AS_MEMATTR_AARCH64_INNER_ALLOC_EXPL(w, r) ((3 << 2) | \
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((w) ? BIT(0) : 0) | \
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((r) ? BIT(1) : 0))
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#define AS_MEMATTR_AARCH64_SH_MIDGARD_INNER (0 << 4)
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#define AS_MEMATTR_AARCH64_SH_CPU_INNER (1 << 4)
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#define AS_MEMATTR_AARCH64_SH_CPU_INNER_SHADER_COH (2 << 4)
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#define AS_MEMATTR_AARCH64_SHARED (0 << 6)
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#define AS_MEMATTR_AARCH64_INNER_OUTER_NC (1 << 6)
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#define AS_MEMATTR_AARCH64_INNER_OUTER_WB (2 << 6)
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#define AS_MEMATTR_AARCH64_FAULT (3 << 6)
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#define AS_LOCKADDR_LO(as) (MMU_AS(as) + 0x10)
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#define AS_LOCKADDR_HI(as) (MMU_AS(as) + 0x14)
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#define AS_COMMAND(as) (MMU_AS(as) + 0x18)
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#define AS_COMMAND_NOP 0
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#define AS_COMMAND_UPDATE 1
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#define AS_COMMAND_LOCK 2
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#define AS_COMMAND_UNLOCK 3
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#define AS_COMMAND_FLUSH_PT 4
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#define AS_COMMAND_FLUSH_MEM 5
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#define AS_LOCK_REGION_MIN_SIZE (1ULL << 15)
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#define AS_FAULTSTATUS(as) (MMU_AS(as) + 0x1C)
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#define AS_FAULTSTATUS_ACCESS_TYPE_MASK (0x3 << 8)
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#define AS_FAULTSTATUS_ACCESS_TYPE_ATOMIC (0x0 << 8)
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#define AS_FAULTSTATUS_ACCESS_TYPE_EX (0x1 << 8)
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#define AS_FAULTSTATUS_ACCESS_TYPE_READ (0x2 << 8)
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#define AS_FAULTSTATUS_ACCESS_TYPE_WRITE (0x3 << 8)
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#define AS_FAULTADDRESS_LO(as) (MMU_AS(as) + 0x20)
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#define AS_FAULTADDRESS_HI(as) (MMU_AS(as) + 0x24)
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#define AS_STATUS(as) (MMU_AS(as) + 0x28)
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#define AS_STATUS_AS_ACTIVE BIT(0)
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#define AS_TRANSCFG_LO(as) (MMU_AS(as) + 0x30)
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#define AS_TRANSCFG_HI(as) (MMU_AS(as) + 0x34)
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#define AS_TRANSCFG_ADRMODE_UNMAPPED (1 << 0)
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#define AS_TRANSCFG_ADRMODE_IDENTITY (2 << 0)
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#define AS_TRANSCFG_ADRMODE_AARCH64_4K (6 << 0)
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#define AS_TRANSCFG_ADRMODE_AARCH64_64K (8 << 0)
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#define AS_TRANSCFG_INA_BITS(x) ((x) << 6)
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#define AS_TRANSCFG_OUTA_BITS(x) ((x) << 14)
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#define AS_TRANSCFG_SL_CONCAT BIT(22)
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#define AS_TRANSCFG_PTW_MEMATTR_NC (1 << 24)
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#define AS_TRANSCFG_PTW_MEMATTR_WB (2 << 24)
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#define AS_TRANSCFG_PTW_SH_NS (0 << 28)
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#define AS_TRANSCFG_PTW_SH_OS (2 << 28)
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#define AS_TRANSCFG_PTW_SH_IS (3 << 28)
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#define AS_TRANSCFG_PTW_RA BIT(30)
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#define AS_TRANSCFG_DISABLE_HIER_AP BIT(33)
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#define AS_TRANSCFG_DISABLE_AF_FAULT BIT(34)
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#define AS_TRANSCFG_WXN BIT(35)
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#define AS_TRANSCFG_XREADABLE BIT(36)
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#define AS_FAULTEXTRA_LO(as) (MMU_AS(as) + 0x38)
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#define AS_FAULTEXTRA_HI(as) (MMU_AS(as) + 0x3C)
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#define CSF_GPU_LATEST_FLUSH_ID 0x10000
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#define CSF_DOORBELL(i) (0x80000 + ((i) * 0x10000))
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#define CSF_GLB_DOORBELL_ID 0
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#define gpu_write(dev, reg, data) \
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writel(data, (dev)->iomem + (reg))
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#define gpu_read(dev, reg) \
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readl((dev)->iomem + (reg))
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#endif
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