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The DMADISABLE bit is a semi-automatic bit present in sysconfig register of some modules. When the DMA must perform read/write accesses, the DMADISABLE bit is cleared by the hardware. But when the DMA must stop for power management, software must set the DMADISABLE bit back to 1. In cases where the ROMCODE/BOOTLOADER uses dma, the hardware clears the DMADISABLE bit (but the romcode/bootloader might not set it back to 1). In order for the kernel to start in a clean state, it is necessary for the kernel to set DMADISABLE bit back to 1 (irrespective of whether it's been set to 1 in romcode or bootloader). During _reset of the (hwmod)device, the DMADISABLE bit is set so that it does not prevent idling of the system. (NOTE: having DMADISABLE to 0, prevents the system to idle) DMADISABLE bit is present in usbotgss module of omap5. Cc: Benoit Cousson <b-cousson@ti.com> Cc: Kevin Hilman <khilman@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> [paul@pwsan.com: updated to apply; fixed checkpatch warnings] Signed-off-by: Paul Walmsley <paul@pwsan.com>
57 lines
1.7 KiB
C
57 lines
1.7 KiB
C
/*
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* omap_hwmod common data structures
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*
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* Copyright (C) 2010 Texas Instruments, Inc.
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* Thara Gopinath <thara@ti.com>
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* Benoît Cousson
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*
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* Copyright (C) 2010 Nokia Corporation
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This data/structures are to be used while defining OMAP on-chip module
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* data and their integration with other OMAP modules and Linux.
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*/
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#include <plat/omap_hwmod.h>
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#include "omap_hwmod_common_data.h"
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/**
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* struct omap_hwmod_sysc_type1 - TYPE1 sysconfig scheme.
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*
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* To be used by hwmod structure to specify the sysconfig offsets
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* if the device ip is compliant with the original PRCM protocol
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* defined for OMAP2420.
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*/
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struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1 = {
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.midle_shift = SYSC_TYPE1_MIDLEMODE_SHIFT,
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.clkact_shift = SYSC_TYPE1_CLOCKACTIVITY_SHIFT,
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.sidle_shift = SYSC_TYPE1_SIDLEMODE_SHIFT,
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.enwkup_shift = SYSC_TYPE1_ENAWAKEUP_SHIFT,
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.srst_shift = SYSC_TYPE1_SOFTRESET_SHIFT,
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.autoidle_shift = SYSC_TYPE1_AUTOIDLE_SHIFT,
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};
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/**
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* struct omap_hwmod_sysc_type2 - TYPE2 sysconfig scheme.
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*
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* To be used by hwmod structure to specify the sysconfig offsets if the
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* device ip is compliant with the new PRCM protocol defined for new
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* OMAP4 IPs.
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*/
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struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2 = {
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.midle_shift = SYSC_TYPE2_MIDLEMODE_SHIFT,
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.sidle_shift = SYSC_TYPE2_SIDLEMODE_SHIFT,
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.srst_shift = SYSC_TYPE2_SOFTRESET_SHIFT,
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.dmadisable_shift = SYSC_TYPE2_DMADISABLE_SHIFT,
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};
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struct omap_dss_dispc_dev_attr omap2_3_dss_dispc_dev_attr = {
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.manager_count = 2,
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.has_framedonetv_irq = 0
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};
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