Dan Williams 6af7139c97 cxl/core: Add cxl-bus driver infrastructure
Enable devices on the 'cxl' bus to be attached to drivers. The initial
user of this functionality is a driver for an 'nvdimm-bridge' device
that anchors a libnvdimm hierarchy attached to CXL persistent memory
resources. Other device types that will leverage this include:

cxl_port: map and use component register functionality (HDM Decoders)

cxl_nvdimm: translate CXL memory expander endpoints to libnvdimm
	    'nvdimm' objects

cxl_region: translate CXL interleave sets to libnvdimm 'region' objects

The pairing of devices to drivers is handled through the cxl_device_id()
matching to cxl_driver.id values. A cxl_device_id() of '0' indicates no
driver support.

In addition to ->match(), ->probe(), and ->remove() support for the
'cxl' bus introduce MODULE_ALIAS_CXL() to autoload modules containing
cxl-drivers. Drivers are added in follow-on changes.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/162379909190.2993820.6134168109678004186.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2021-06-15 16:46:34 -07:00
..
2021-06-07 14:04:43 +02:00
2021-05-05 13:24:11 -07:00
2021-04-18 09:36:56 +03:00
2021-05-15 08:52:30 -07:00
2021-05-20 06:31:52 -10:00
2021-04-28 15:59:13 -07:00
2021-05-23 11:39:02 +02:00
2021-04-26 12:11:52 -07:00
2021-06-04 10:23:57 +10:00
2021-04-27 18:09:44 -07:00
2021-06-02 08:41:45 -10:00
2021-05-01 10:14:08 -07:00
2021-05-28 14:42:37 -10:00
2021-04-28 15:59:13 -07:00
2021-05-29 06:41:50 -10:00
2021-05-01 10:14:08 -07:00
2021-04-29 11:57:23 -07:00
2021-05-05 12:53:16 -07:00
2021-04-28 15:59:13 -07:00
2021-05-04 11:13:33 -07:00
2021-05-05 13:24:11 -07:00
2021-05-03 12:15:21 -07:00
2021-06-06 15:39:56 -07:00
2021-06-05 15:43:11 -07:00
2021-05-05 13:31:39 -07:00
2021-04-28 15:59:13 -07:00
2021-05-05 13:31:39 -07:00