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94329ce6e3
Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM6375 SoCs. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230208091340.124641-8-konrad.dybcio@linaro.org
37 lines
934 B
C
37 lines
934 B
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2023, Linaro Limited
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_BLAIR_H
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#define _DT_BINDINGS_CLK_QCOM_GPU_CC_BLAIR_H
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/* GPU CC clocks */
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#define GPU_CC_PLL0 0
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#define GPU_CC_PLL1 1
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#define GPU_CC_AHB_CLK 2
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#define GPU_CC_CX_GFX3D_CLK 3
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#define GPU_CC_CX_GFX3D_SLV_CLK 4
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#define GPU_CC_CX_GMU_CLK 5
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#define GPU_CC_CX_SNOC_DVM_CLK 6
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#define GPU_CC_CXO_AON_CLK 7
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#define GPU_CC_CXO_CLK 8
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#define GPU_CC_GMU_CLK_SRC 9
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#define GPU_CC_GX_CXO_CLK 10
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#define GPU_CC_GX_GFX3D_CLK 11
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#define GPU_CC_GX_GFX3D_CLK_SRC 12
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#define GPU_CC_GX_GMU_CLK 13
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#define GPU_CC_SLEEP_CLK 14
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/* GDSCs */
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#define GPU_CX_GDSC 0
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#define GPU_GX_GDSC 1
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/* Resets */
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#define GPU_GX_BCR 0
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#define GPU_ACD_BCR 1
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#define GPU_GX_ACD_MISC_BCR 2
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#endif
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