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Add JSON metrics for Sandy Bridge. Committer testing: # grep "model name" /proc/cpuinfo | head -1 model name : Intel(R) Core(TM) i5-2400 CPU @ 3.10GHz # perf list metricgroup List of pre-defined events (to be used in -e): Metric Groups: DSB FLOPS Frontend Frontend_Bandwidth Pipeline Ports_Utilization Power SMT Summary TopDownL1 # perf stat -M Power --metric-only -a sleep 1 Performance counter stats for 'system wide': Turbo_Utilization C3_Core_Residency C6_Core_Residency C7_Core_Residency C2_Pkg_Residency C3_Pkg_Residency C6_Pkg_Residency C7_Pkg_Residency 0.8 0.0 98.1 0.0 0.0 0.0 23.4 0.0 1.001153658 seconds time elapsed # perf stat -v -M Power --metric-only -a sleep 1 Using CPUID GenuineIntel-6-2A metric expr cpu_clk_unhalted.thread / cpu_clk_unhalted.ref_tsc for Turbo_Utilization found event cpu_clk_unhalted.thread found event cpu_clk_unhalted.ref_tsc metric expr (cstate_core@c3\-residency@ / msr@tsc@) * 100 for C3_Core_Residency found event cstate_core/c3-residency/ found event msr/tsc/ metric expr (cstate_core@c6\-residency@ / msr@tsc@) * 100 for C6_Core_Residency found event cstate_core/c6-residency/ found event msr/tsc/ metric expr (cstate_core@c7\-residency@ / msr@tsc@) * 100 for C7_Core_Residency found event cstate_core/c7-residency/ found event msr/tsc/ metric expr (cstate_pkg@c2\-residency@ / msr@tsc@) * 100 for C2_Pkg_Residency found event cstate_pkg/c2-residency/ found event msr/tsc/ metric expr (cstate_pkg@c3\-residency@ / msr@tsc@) * 100 for C3_Pkg_Residency found event cstate_pkg/c3-residency/ found event msr/tsc/ metric expr (cstate_pkg@c6\-residency@ / msr@tsc@) * 100 for C6_Pkg_Residency found event cstate_pkg/c6-residency/ found event msr/tsc/ metric expr (cstate_pkg@c7\-residency@ / msr@tsc@) * 100 for C7_Pkg_Residency found event cstate_pkg/c7-residency/ found event msr/tsc/ adding {cpu_clk_unhalted.thread,cpu_clk_unhalted.ref_tsc}:W,{cstate_core/c3-residency/,msr/tsc/}:W,{cstate_core/c6-residency/,msr/tsc/}:W,{cstate_core/c7-residency/,msr/tsc/}:W,{cstate_pkg/c2-residency/,msr/tsc/}:W,{cstate_pkg/c3-residency/,msr/tsc/}:W,{cstate_pkg/c6-residency/,msr/tsc/}:W,{cstate_pkg/c7-residency/,msr/tsc/}:W cpu_clk_unhalted.thread -> cpu/event=0x3c/ cpu_clk_unhalted.ref_tsc -> cpu/umask=0x3,period=2000003,event=0/ Weak group for cstate_pkg/c2-residency//2 failed Weak group for cstate_pkg/c3-residency//2 failed Weak group for cstate_pkg/c6-residency//2 failed Weak group for cstate_pkg/c7-residency//2 failed cpu_clk_unhalted.thread: 5564185 4002833569 4002833569 cpu_clk_unhalted.ref_tsc: 7325424 4002833569 4002833569 cstate_core/c3-residency/: 68293 4003027101 4003027101 msr/tsc/: 12451294472 4003027101 4003027101 cstate_core/c6-residency/: 12238830163 4003260984 4003260984 msr/tsc/: 12452017806 4003260984 4003260984 cstate_core/c7-residency/: 0 4003489648 4003489648 msr/tsc/: 12452725162 4003489648 4003489648 cstate_pkg/c2-residency/: 1830054 1000913138 1000913138 msr/tsc/: 12453441079 4003717513 4003717513 cstate_pkg/c3-residency/: 0 1000973570 1000973570 msr/tsc/: 12454177865 4003954758 4003954758 cstate_pkg/c6-residency/: 2940448859 1001032370 1001032370 msr/tsc/: 12454833890 4004166118 4004166118 cstate_pkg/c7-residency/: 0 1001049818 1001049818 msr/tsc/: 12454919470 4004194204 4004194204 Performance counter stats for 'system wide': Turbo_Utilization C3_Core_Residency C6_Core_Residency C7_Core_Residency C2_Pkg_Residency C3_Pkg_Residency C6_Pkg_Residency C7_Pkg_Residency 0.8 0.0 98.3 0.0 0.0 0.0 23.6 0.0 1.001126519 seconds time elapsed # Signed-off-by: Andi Kleen <ak@linux.intel.com> Tested-by: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Jiri Olsa <jolsa@redhat.com> Link: http://lkml.kernel.org/r/20170905195235.GW2482@two.firstfloor.org Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
The contents of this directory allow users to specify PMU events in their CPUs by their symbolic names rather than raw event codes (see example below). The main program in this directory, is the 'jevents', which is built and executed _BEFORE_ the perf binary itself is built. The 'jevents' program tries to locate and process JSON files in the directory tree tools/perf/pmu-events/arch/foo. - Regular files with '.json' extension in the name are assumed to be JSON files, each of which describes a set of PMU events. - Regular files with basename starting with 'mapfile.csv' are assumed to be a CSV file that maps a specific CPU to its set of PMU events. (see below for mapfile format) - Directories are traversed, but all other files are ignored. The PMU events supported by a CPU model are expected to grouped into topics such as Pipelining, Cache, Memory, Floating-point etc. All events for a topic should be placed in a separate JSON file - where the file name identifies the topic. Eg: "Floating-point.json". All the topic JSON files for a CPU model/family should be in a separate sub directory. Thus for the Silvermont X86 CPU: $ ls tools/perf/pmu-events/arch/x86/Silvermont_core Cache.json Memory.json Virtual-Memory.json Frontend.json Pipeline.json Using the JSON files and the mapfile, 'jevents' generates the C source file, 'pmu-events.c', which encodes the two sets of tables: - Set of 'PMU events tables' for all known CPUs in the architecture, (one table like the following, per JSON file; table name 'pme_power8' is derived from JSON file name, 'power8.json'). struct pmu_event pme_power8[] = { ... { .name = "pm_1plus_ppc_cmpl", .event = "event=0x100f2", .desc = "1 or more ppc insts finished,", }, ... } - A 'mapping table' that maps each CPU of the architecture, to its 'PMU events table' struct pmu_events_map pmu_events_map[] = { { .cpuid = "004b0000", .version = "1", .type = "core", .table = pme_power8 }, ... }; After the 'pmu-events.c' is generated, it is compiled and the resulting 'pmu-events.o' is added to 'libperf.a' which is then used to build perf. NOTES: 1. Several CPUs can support same set of events and hence use a common JSON file. Hence several entries in the pmu_events_map[] could map to a single 'PMU events table'. 2. The 'pmu-events.h' has an extern declaration for the mapping table and the generated 'pmu-events.c' defines this table. 3. _All_ known CPU tables for architecture are included in the perf binary. At run time, perf determines the actual CPU it is running on, finds the matching events table and builds aliases for those events. This allows users to specify events by their name: $ perf stat -e pm_1plus_ppc_cmpl sleep 1 where 'pm_1plus_ppc_cmpl' is a Power8 PMU event. However some errors in processing may cause the perf build to fail. Mapfile format =============== The mapfile enables multiple CPU models to share a single set of PMU events. It is required even if such mapping is 1:1. The mapfile.csv format is expected to be: Header line CPUID,Version,Dir/path/name,Type where: Comma: is the required field delimiter (i.e other fields cannot have commas within them). Comments: Lines in which the first character is either '\n' or '#' are ignored. Header line The header line is the first line in the file, which is always _IGNORED_. It can empty. CPUID: CPUID is an arch-specific char string, that can be used to identify CPU (and associate it with a set of PMU events it supports). Multiple CPUIDS can point to the same File/path/name.json. Example: CPUID == 'GenuineIntel-6-2E' (on x86). CPUID == '004b0100' (PVR value in Powerpc) Version: is the Version of the mapfile. Dir/path/name: is the pathname to the directory containing the CPU's JSON files, relative to the directory containing the mapfile.csv Type: indicates whether the events or "core" or "uncore" events. Eg: $ grep Silvermont tools/perf/pmu-events/arch/x86/mapfile.csv GenuineIntel-6-37,V13,Silvermont_core,core GenuineIntel-6-4D,V13,Silvermont_core,core GenuineIntel-6-4C,V13,Silvermont_core,core i.e the three CPU models use the JSON files (i.e PMU events) listed in the directory 'tools/perf/pmu-events/arch/x86/Silvermont_core'.