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0d363282bb
Add the clock drivers for the entire clock tree of MediaTek Helio X10 MT6795, including system clocks (apmixedsys, infracfg, pericfg, topckgen) and multimedia clocks (mmsys, mfg, vdecsys, vencsys). Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220921091455.41327-9-angelogioacchino.delregno@collabora.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
51 lines
1.4 KiB
C
51 lines
1.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2022 Collabora Ltd.
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* Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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*/
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#include <dt-bindings/clock/mediatek,mt6795-clk.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include "clk-gate.h"
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#include "clk-mtk.h"
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static const struct mtk_gate_regs venc_cg_regs = {
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.set_ofs = 0x4,
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.clr_ofs = 0x8,
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.sta_ofs = 0x0,
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};
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#define GATE_VENC(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
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static const struct mtk_gate venc_clks[] = {
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GATE_VENC(CLK_VENC_LARB, "venc_larb", "venc_sel", 0),
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GATE_VENC(CLK_VENC_VENC, "venc_venc", "venc_sel", 4),
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GATE_VENC(CLK_VENC_JPGENC, "venc_jpgenc", "venc_sel", 8),
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GATE_VENC(CLK_VENC_JPGDEC, "venc_jpgdec", "venc_sel", 12),
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};
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static const struct mtk_clk_desc venc_desc = {
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.clks = venc_clks,
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.num_clks = ARRAY_SIZE(venc_clks),
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};
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static const struct of_device_id of_match_clk_mt6795_vencsys[] = {
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{ .compatible = "mediatek,mt6795-vencsys", .data = &venc_desc },
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{ /* sentinel */ }
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};
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static struct platform_driver clk_mt6795_vencsys_drv = {
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.driver = {
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.name = "clk-mt6795-vencsys",
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.of_match_table = of_match_clk_mt6795_vencsys,
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},
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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};
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module_platform_driver(clk_mt6795_vencsys_drv);
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MODULE_DESCRIPTION("MediaTek MT6795 vdecsys clocks driver");
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MODULE_LICENSE("GPL");
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