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ca54d06fca
Consider CPU, L2 cache, and memory clocks as critical to prevent them -- and the parent clocks -- from being automatically gated, since nothing calls clk_get() on these clocks. Gating the CPU clock hangs the processor, and gating memory makes external DRAM inaccessible. Normal kernel code can't hope to deal with either situation so those clocks have to be critical. The L2 cache is required only if caches are running, and could be gated if the kernel takes care to flush and disable caches before gating the clock. There's no mechanism to do this, and probably no reason to do it, so it's simpler to mark the L2 cache as critical. Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20220428164454.17908-3-aidanmacdonald.0x0@gmail.com Tested-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> # On X1000 and X1830 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
449 lines
11 KiB
C
449 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* JZ4760 SoC CGU driver
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* Copyright 2018, Paul Cercueil <paul@crapouillou.net>
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*/
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#include <linux/bitops.h>
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/clk.h>
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#include <dt-bindings/clock/ingenic,jz4760-cgu.h>
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#include "cgu.h"
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#include "pm.h"
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#define MHZ (1000 * 1000)
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/*
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* CPM registers offset address definition
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*/
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#define CGU_REG_CPCCR 0x00
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#define CGU_REG_LCR 0x04
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#define CGU_REG_CPPCR0 0x10
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#define CGU_REG_CLKGR0 0x20
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#define CGU_REG_OPCR 0x24
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#define CGU_REG_CLKGR1 0x28
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#define CGU_REG_CPPCR1 0x30
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#define CGU_REG_USBPCR 0x3c
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#define CGU_REG_USBCDR 0x50
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#define CGU_REG_I2SCDR 0x60
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#define CGU_REG_LPCDR 0x64
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#define CGU_REG_MSCCDR 0x68
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#define CGU_REG_UHCCDR 0x6c
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#define CGU_REG_SSICDR 0x74
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#define CGU_REG_CIMCDR 0x7c
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#define CGU_REG_GPSCDR 0x80
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#define CGU_REG_PCMCDR 0x84
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#define CGU_REG_GPUCDR 0x88
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static const s8 pll_od_encoding[8] = {
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0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3,
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};
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static const u8 jz4760_cgu_cpccr_div_table[] = {
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1, 2, 3, 4, 6, 8,
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};
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static const u8 jz4760_cgu_pll_half_div_table[] = {
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2, 1,
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};
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static void
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jz4760_cgu_calc_m_n_od(const struct ingenic_cgu_pll_info *pll_info,
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unsigned long rate, unsigned long parent_rate,
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unsigned int *pm, unsigned int *pn, unsigned int *pod)
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{
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unsigned int m, n, od, m_max = (1 << pll_info->m_bits) - 2;
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/* The frequency after the N divider must be between 1 and 50 MHz. */
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n = parent_rate / (1 * MHZ);
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/* The N divider must be >= 2. */
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n = clamp_val(n, 2, 1 << pll_info->n_bits);
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for (;; n >>= 1) {
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od = (unsigned int)-1;
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do {
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m = (rate / MHZ) * (1 << ++od) * n / (parent_rate / MHZ);
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} while ((m > m_max || m & 1) && (od < 4));
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if (od < 4 && m >= 4 && m <= m_max)
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break;
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}
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*pm = m;
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*pn = n;
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*pod = 1 << od;
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}
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static const struct ingenic_cgu_clk_info jz4760_cgu_clocks[] = {
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/* External clocks */
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[JZ4760_CLK_EXT] = { "ext", CGU_CLK_EXT },
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[JZ4760_CLK_OSC32K] = { "osc32k", CGU_CLK_EXT },
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/* PLLs */
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[JZ4760_CLK_PLL0] = {
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"pll0", CGU_CLK_PLL,
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.parents = { JZ4760_CLK_EXT },
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.pll = {
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.reg = CGU_REG_CPPCR0,
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.rate_multiplier = 1,
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.m_shift = 23,
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.m_bits = 8,
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.m_offset = 0,
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.n_shift = 18,
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.n_bits = 4,
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.n_offset = 0,
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.od_shift = 16,
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.od_bits = 2,
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.od_max = 8,
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.od_encoding = pll_od_encoding,
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.bypass_reg = CGU_REG_CPPCR0,
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.bypass_bit = 9,
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.enable_bit = 8,
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.stable_bit = 10,
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.calc_m_n_od = jz4760_cgu_calc_m_n_od,
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},
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},
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[JZ4760_CLK_PLL1] = {
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/* TODO: PLL1 can depend on PLL0 */
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"pll1", CGU_CLK_PLL,
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.parents = { JZ4760_CLK_EXT },
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.pll = {
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.reg = CGU_REG_CPPCR1,
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.rate_multiplier = 1,
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.m_shift = 23,
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.m_bits = 8,
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.m_offset = 0,
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.n_shift = 18,
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.n_bits = 4,
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.n_offset = 0,
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.od_shift = 16,
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.od_bits = 2,
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.od_max = 8,
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.od_encoding = pll_od_encoding,
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.bypass_bit = -1,
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.enable_bit = 7,
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.stable_bit = 6,
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.calc_m_n_od = jz4760_cgu_calc_m_n_od,
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},
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},
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/* Main clocks */
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[JZ4760_CLK_CCLK] = {
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"cclk", CGU_CLK_DIV,
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/*
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* Disabling the CPU clock or any parent clocks will hang the
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* system; mark it critical.
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*/
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.flags = CLK_IS_CRITICAL,
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.parents = { JZ4760_CLK_PLL0, },
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.div = {
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CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0,
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jz4760_cgu_cpccr_div_table,
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},
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},
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[JZ4760_CLK_HCLK] = {
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"hclk", CGU_CLK_DIV,
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.parents = { JZ4760_CLK_PLL0, },
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.div = {
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CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0,
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jz4760_cgu_cpccr_div_table,
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},
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},
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[JZ4760_CLK_SCLK] = {
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"sclk", CGU_CLK_DIV,
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.parents = { JZ4760_CLK_PLL0, },
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.div = {
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CGU_REG_CPCCR, 24, 1, 4, 22, -1, -1, 0,
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jz4760_cgu_cpccr_div_table,
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},
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},
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[JZ4760_CLK_H2CLK] = {
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"h2clk", CGU_CLK_DIV,
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.parents = { JZ4760_CLK_PLL0, },
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.div = {
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CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1, 0,
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jz4760_cgu_cpccr_div_table,
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},
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},
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[JZ4760_CLK_MCLK] = {
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"mclk", CGU_CLK_DIV,
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/*
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* Disabling MCLK or its parents will render DRAM
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* inaccessible; mark it critical.
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*/
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.flags = CLK_IS_CRITICAL,
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.parents = { JZ4760_CLK_PLL0, },
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.div = {
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CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0,
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jz4760_cgu_cpccr_div_table,
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},
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},
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[JZ4760_CLK_PCLK] = {
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"pclk", CGU_CLK_DIV,
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.parents = { JZ4760_CLK_PLL0, },
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.div = {
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CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0,
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jz4760_cgu_cpccr_div_table,
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},
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},
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/* Divided clocks */
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[JZ4760_CLK_PLL0_HALF] = {
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"pll0_half", CGU_CLK_DIV,
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.parents = { JZ4760_CLK_PLL0 },
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.div = {
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CGU_REG_CPCCR, 21, 1, 1, 22, -1, -1, 0,
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jz4760_cgu_pll_half_div_table,
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},
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},
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/* Those divided clocks can connect to PLL0 or PLL1 */
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[JZ4760_CLK_UHC] = {
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"uhc", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
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.parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, },
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.mux = { CGU_REG_UHCCDR, 31, 1 },
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.div = { CGU_REG_UHCCDR, 0, 1, 4, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR0, 24 },
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},
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[JZ4760_CLK_GPU] = {
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"gpu", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
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.parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, },
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.mux = { CGU_REG_GPUCDR, 31, 1 },
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.div = { CGU_REG_GPUCDR, 0, 1, 3, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR1, 9 },
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},
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[JZ4760_CLK_LPCLK_DIV] = {
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"lpclk_div", CGU_CLK_DIV | CGU_CLK_MUX,
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.parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, },
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.mux = { CGU_REG_LPCDR, 29, 1 },
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.div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 },
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},
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[JZ4760_CLK_TVE] = {
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"tve", CGU_CLK_GATE | CGU_CLK_MUX,
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.parents = { JZ4760_CLK_LPCLK_DIV, JZ4760_CLK_EXT, },
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.mux = { CGU_REG_LPCDR, 31, 1 },
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.gate = { CGU_REG_CLKGR0, 27 },
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},
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[JZ4760_CLK_LPCLK] = {
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"lpclk", CGU_CLK_GATE | CGU_CLK_MUX,
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.parents = { JZ4760_CLK_LPCLK_DIV, JZ4760_CLK_TVE, },
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.mux = { CGU_REG_LPCDR, 30, 1 },
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.gate = { CGU_REG_CLKGR0, 28 },
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},
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[JZ4760_CLK_GPS] = {
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"gps", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
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.parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, },
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.mux = { CGU_REG_GPSCDR, 31, 1 },
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.div = { CGU_REG_GPSCDR, 0, 1, 4, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR0, 22 },
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},
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/* Those divided clocks can connect to EXT, PLL0 or PLL1 */
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[JZ4760_CLK_PCM] = {
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"pcm", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
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.parents = { JZ4760_CLK_EXT, -1,
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JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1 },
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.mux = { CGU_REG_PCMCDR, 30, 2 },
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.div = { CGU_REG_PCMCDR, 0, 1, 9, -1, -1, -1, BIT(0) },
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.gate = { CGU_REG_CLKGR1, 8 },
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},
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[JZ4760_CLK_I2S] = {
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"i2s", CGU_CLK_DIV | CGU_CLK_MUX,
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.parents = { JZ4760_CLK_EXT, -1,
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JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1 },
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.mux = { CGU_REG_I2SCDR, 30, 2 },
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.div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1, BIT(0) },
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},
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[JZ4760_CLK_OTG] = {
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"usb", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
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.parents = { JZ4760_CLK_EXT, -1,
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JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1 },
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.mux = { CGU_REG_USBCDR, 30, 2 },
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.div = { CGU_REG_USBCDR, 0, 1, 8, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR0, 2 },
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},
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/* Those divided clocks can connect to EXT or PLL0 */
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[JZ4760_CLK_MMC_MUX] = {
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"mmc_mux", CGU_CLK_MUX | CGU_CLK_DIV,
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.parents = { JZ4760_CLK_EXT, JZ4760_CLK_PLL0_HALF, },
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.mux = { CGU_REG_MSCCDR, 31, 1 },
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.div = { CGU_REG_MSCCDR, 0, 1, 6, -1, -1, -1, BIT(0) },
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},
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[JZ4760_CLK_SSI_MUX] = {
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"ssi_mux", CGU_CLK_DIV | CGU_CLK_MUX,
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.parents = { JZ4760_CLK_EXT, JZ4760_CLK_PLL0_HALF, },
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.mux = { CGU_REG_SSICDR, 31, 1 },
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.div = { CGU_REG_SSICDR, 0, 1, 6, -1, -1, -1, BIT(0) },
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},
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/* These divided clock can connect to PLL0 only */
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[JZ4760_CLK_CIM] = {
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"cim", CGU_CLK_DIV | CGU_CLK_GATE,
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.parents = { JZ4760_CLK_PLL0_HALF },
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.div = { CGU_REG_CIMCDR, 0, 1, 8, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR0, 26 },
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},
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/* Gate-only clocks */
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[JZ4760_CLK_SSI0] = {
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"ssi0", CGU_CLK_GATE,
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.parents = { JZ4760_CLK_SSI_MUX, },
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.gate = { CGU_REG_CLKGR0, 4 },
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},
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[JZ4760_CLK_SSI1] = {
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"ssi1", CGU_CLK_GATE,
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.parents = { JZ4760_CLK_SSI_MUX, },
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.gate = { CGU_REG_CLKGR0, 19 },
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},
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[JZ4760_CLK_SSI2] = {
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"ssi2", CGU_CLK_GATE,
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.parents = { JZ4760_CLK_SSI_MUX, },
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.gate = { CGU_REG_CLKGR0, 20 },
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},
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[JZ4760_CLK_DMA] = {
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"dma", CGU_CLK_GATE,
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.parents = { JZ4760_CLK_H2CLK, },
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.gate = { CGU_REG_CLKGR0, 21 },
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},
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[JZ4760_CLK_MDMA] = {
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"mdma", CGU_CLK_GATE,
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.parents = { JZ4760_CLK_HCLK, },
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.gate = { CGU_REG_CLKGR0, 25 },
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},
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[JZ4760_CLK_BDMA] = {
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"bdma", CGU_CLK_GATE,
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.parents = { JZ4760_CLK_HCLK, },
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.gate = { CGU_REG_CLKGR1, 0 },
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},
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[JZ4760_CLK_I2C0] = {
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"i2c0", CGU_CLK_GATE,
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.parents = { JZ4760_CLK_EXT, },
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.gate = { CGU_REG_CLKGR0, 5 },
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},
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[JZ4760_CLK_I2C1] = {
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"i2c1", CGU_CLK_GATE,
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.parents = { JZ4760_CLK_EXT, },
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.gate = { CGU_REG_CLKGR0, 6 },
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},
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[JZ4760_CLK_UART0] = {
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"uart0", CGU_CLK_GATE,
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.parents = { JZ4760_CLK_EXT, },
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.gate = { CGU_REG_CLKGR0, 15 },
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},
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[JZ4760_CLK_UART1] = {
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"uart1", CGU_CLK_GATE,
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.parents = { JZ4760_CLK_EXT, },
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.gate = { CGU_REG_CLKGR0, 16 },
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},
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[JZ4760_CLK_UART2] = {
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"uart2", CGU_CLK_GATE,
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.parents = { JZ4760_CLK_EXT, },
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.gate = { CGU_REG_CLKGR0, 17 },
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},
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[JZ4760_CLK_UART3] = {
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"uart3", CGU_CLK_GATE,
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.parents = { JZ4760_CLK_EXT, },
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.gate = { CGU_REG_CLKGR0, 18 },
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},
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[JZ4760_CLK_IPU] = {
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"ipu", CGU_CLK_GATE,
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.parents = { JZ4760_CLK_HCLK, },
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.gate = { CGU_REG_CLKGR0, 29 },
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},
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[JZ4760_CLK_ADC] = {
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"adc", CGU_CLK_GATE,
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.parents = { JZ4760_CLK_EXT, },
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.gate = { CGU_REG_CLKGR0, 14 },
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},
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[JZ4760_CLK_AIC] = {
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"aic", CGU_CLK_GATE,
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.parents = { JZ4760_CLK_EXT, },
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.gate = { CGU_REG_CLKGR0, 8 },
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},
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[JZ4760_CLK_VPU] = {
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"vpu", CGU_CLK_GATE,
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.parents = { JZ4760_CLK_HCLK, },
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.gate = { CGU_REG_LCR, 30, false, 150 },
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},
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[JZ4760_CLK_MMC0] = {
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"mmc0", CGU_CLK_GATE,
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.parents = { JZ4760_CLK_MMC_MUX, },
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.gate = { CGU_REG_CLKGR0, 3 },
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},
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[JZ4760_CLK_MMC1] = {
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"mmc1", CGU_CLK_GATE,
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.parents = { JZ4760_CLK_MMC_MUX, },
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.gate = { CGU_REG_CLKGR0, 11 },
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},
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[JZ4760_CLK_MMC2] = {
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"mmc2", CGU_CLK_GATE,
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.parents = { JZ4760_CLK_MMC_MUX, },
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.gate = { CGU_REG_CLKGR0, 12 },
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},
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[JZ4760_CLK_UHC_PHY] = {
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"uhc_phy", CGU_CLK_GATE,
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.parents = { JZ4760_CLK_UHC, },
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.gate = { CGU_REG_OPCR, 5 },
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},
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[JZ4760_CLK_OTG_PHY] = {
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"usb_phy", CGU_CLK_GATE,
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.parents = { JZ4760_CLK_OTG },
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.gate = { CGU_REG_OPCR, 7, true, 50 },
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},
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/* Custom clocks */
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|
[JZ4760_CLK_EXT512] = {
|
|
"ext/512", CGU_CLK_FIXDIV,
|
|
.parents = { JZ4760_CLK_EXT },
|
|
.fixdiv = { 512 },
|
|
},
|
|
[JZ4760_CLK_RTC] = {
|
|
"rtc", CGU_CLK_MUX,
|
|
.parents = { JZ4760_CLK_EXT512, JZ4760_CLK_OSC32K, },
|
|
.mux = { CGU_REG_OPCR, 2, 1},
|
|
},
|
|
};
|
|
|
|
static void __init jz4760_cgu_init(struct device_node *np)
|
|
{
|
|
struct ingenic_cgu *cgu;
|
|
int retval;
|
|
|
|
cgu = ingenic_cgu_new(jz4760_cgu_clocks,
|
|
ARRAY_SIZE(jz4760_cgu_clocks), np);
|
|
if (!cgu) {
|
|
pr_err("%s: failed to initialise CGU\n", __func__);
|
|
return;
|
|
}
|
|
|
|
retval = ingenic_cgu_register_clocks(cgu);
|
|
if (retval)
|
|
pr_err("%s: failed to register CGU Clocks\n", __func__);
|
|
|
|
ingenic_cgu_register_syscore_ops(cgu);
|
|
}
|
|
|
|
/* We only probe via devicetree, no need for a platform driver */
|
|
CLK_OF_DECLARE_DRIVER(jz4760_cgu, "ingenic,jz4760-cgu", jz4760_cgu_init);
|
|
|
|
/* JZ4760B has some small differences, but we don't implement them. */
|
|
CLK_OF_DECLARE_DRIVER(jz4760b_cgu, "ingenic,jz4760b-cgu", jz4760_cgu_init);
|