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6ce48897ce
Add kexec/kdump support for Loongson64 by:
1, Provide Loongson-specific kexec functions: loongson_kexec_prepare(),
loongson_kexec_shutdown() and loongson_crash_shutdown();
2, Provide Loongson-specific assembly code in kexec_smp_wait();
To start Loongson64, The boot CPU needs 3 parameters:
fw_arg0: the number of arguments in cmdline (i.e., argc).
fw_arg1: structure holds cmdline such as "root=/dev/sda1 console=tty"
(i.e., argv).
fw_arg2: environment (i.e., envp, additional boot parameters from LEFI).
Non-boot CPUs do not need one parameter as the IPI mailbox base address.
They query their own IPI mailbox to get PC, SP and GP in a loopi, until
the boot CPU brings them up.
loongson_kexec_prepare(): Setup cmdline for kexec/kdump. The kexec/kdump
cmdline comes from kexec's "append" option string. This structure will
be parsed in fw_init_cmdline() of arch/mips/fw/lib/cmdline.c. Both image
->control_code_page and the cmdline need to be in a safe memory region
(memory allocated by the old kernel may be corrupted by the new kernel).
In order to maintain compatibility for the old firmware, the low 2MB is
reserverd and safe for Loongson. So let KEXEC_CTRL_CODE and KEXEC_ARGV_
ADDR be here. LEFI parameters may be corrupted at runtime, so backup it
at mips_reboot_setup(), and then restore it at loongson_kexec_shutdown()
/loongson_crash_shutdown().
loongson_kexec_shutdown(): Wake up all present CPUs and let them go to
reboot_code_buffer. Pass the kexec parameters to kexec_args.
loongson_crash_shutdown(): Pass the kdump parameters to kexec_args.
The assembly part in kexec_smp_wait provide a routine as BIOS does, in
order to keep secondary CPUs in a querying loop.
The layout of low 2MB memory in our design:
0x80000000, the first MB, the first 64K, Exception vectors
0x80010000, the first MB, the second 64K, STR (suspend) data
0x80020000, the first MB, the third and fourth 64K, UEFI HOB
0x80040000, the first MB, the fifth 64K, RT-Thread for SMC
0x80100000, the second MB, the first 64K, KEXEC code
0x80108000, the second MB, the second 64K, KEXEC data
Cc: Eric Biederman <ebiederm@xmission.com>
Tested-by: Jinyang He <hejinyang@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@kernel.org>
Signed-off-by: Jinyang He <hejinyang@loongson.cn>
Signed-off-by: Youling Tang <tangyouling@loongson.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
169 lines
4.0 KiB
C
169 lines
4.0 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2005-2008 Cavium Networks, Inc
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*/
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#ifndef __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H
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#define __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H
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#define CP0_CVMCTL_REG $9, 7
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#define CP0_CVMMEMCTL_REG $11,7
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#define CP0_PRID_REG $15, 0
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#define CP0_DCACHE_ERR_REG $27, 1
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#define CP0_PRID_OCTEON_PASS1 0x000d0000
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#define CP0_PRID_OCTEON_CN30XX 0x000d0200
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.macro kernel_entry_setup
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# Registers set by bootloader:
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# (only 32 bits set by bootloader, all addresses are physical
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# addresses, and need to have the appropriate memory region set
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# by the kernel
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# a0 = argc
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# a1 = argv (kseg0 compat addr)
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# a2 = 1 if init core, zero otherwise
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# a3 = address of boot descriptor block
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.set push
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.set arch=octeon
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# Read the cavium mem control register
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dmfc0 v0, CP0_CVMMEMCTL_REG
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# Clear the lower 6 bits, the CVMSEG size
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dins v0, $0, 0, 6
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ori v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
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dmtc0 v0, CP0_CVMMEMCTL_REG # Write the cavium mem control register
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dmfc0 v0, CP0_CVMCTL_REG # Read the cavium control register
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# Disable unaligned load/store support but leave HW fixup enabled
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# Needed for octeon specific memcpy
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or v0, v0, 0x5001
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xor v0, v0, 0x1001
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# First clear off CvmCtl[IPPCI] bit and move the performance
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# counters interrupt to IRQ 6
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dli v1, ~(7 << 7)
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and v0, v0, v1
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ori v0, v0, (6 << 7)
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mfc0 v1, CP0_PRID_REG
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and t1, v1, 0xfff8
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xor t1, t1, 0x9000 # 63-P1
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beqz t1, 4f
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and t1, v1, 0xfff8
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xor t1, t1, 0x9008 # 63-P2
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beqz t1, 4f
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and t1, v1, 0xfff8
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xor t1, t1, 0x9100 # 68-P1
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beqz t1, 4f
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and t1, v1, 0xff00
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xor t1, t1, 0x9200 # 66-PX
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bnez t1, 5f # Skip WAR for others.
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and t1, v1, 0x00ff
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slti t1, t1, 2 # 66-P1.2 and later good.
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beqz t1, 5f
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4: # core-16057 work around
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or v0, v0, 0x2000 # Set IPREF bit.
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5: # No core-16057 work around
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# Write the cavium control register
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dmtc0 v0, CP0_CVMCTL_REG
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sync
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# Flush dcache after config change
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cache 9, 0($0)
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# Zero all of CVMSEG to make sure parity is correct
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dli v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
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dsll v0, 7
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beqz v0, 2f
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1: dsubu v0, 8
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sd $0, -32768(v0)
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bnez v0, 1b
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2:
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mfc0 v0, CP0_PRID_REG
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bbit0 v0, 15, 1f
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# OCTEON II or better have bit 15 set. Clear the error bits.
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and t1, v0, 0xff00
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dli v0, 0x9500
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bge t1, v0, 1f # OCTEON III has no DCACHE_ERR_REG COP0
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dli v0, 0x27
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dmtc0 v0, CP0_DCACHE_ERR_REG
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1:
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# Get my core id
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rdhwr v0, $0
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# Jump the master to kernel_entry
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bne a2, zero, octeon_main_processor
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nop
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#ifdef CONFIG_SMP
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#
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# All cores other than the master need to wait here for SMP bootstrap
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# to begin
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#
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octeon_spin_wait_boot:
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#ifdef CONFIG_RELOCATABLE
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PTR_LA t0, octeon_processor_relocated_kernel_entry
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LONG_L t0, (t0)
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beq zero, t0, 1f
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nop
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jr t0
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nop
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1:
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#endif /* CONFIG_RELOCATABLE */
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# This is the variable where the next core to boot is stored
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PTR_LA t0, octeon_processor_boot
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# Get the core id of the next to be booted
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LONG_L t1, (t0)
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# Keep looping if it isn't me
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bne t1, v0, octeon_spin_wait_boot
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nop
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# Get my GP from the global variable
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PTR_LA t0, octeon_processor_gp
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LONG_L gp, (t0)
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# Get my SP from the global variable
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PTR_LA t0, octeon_processor_sp
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LONG_L sp, (t0)
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# Set the SP global variable to zero so the master knows we've started
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LONG_S zero, (t0)
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#ifdef __OCTEON__
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syncw
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syncw
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#else
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sync
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#endif
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# Jump to the normal Linux SMP entry point
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j smp_bootstrap
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nop
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#else /* CONFIG_SMP */
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#
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# Someone tried to boot SMP with a non SMP kernel. All extra cores
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# will halt here.
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#
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octeon_wait_forever:
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wait
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b octeon_wait_forever
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nop
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#endif /* CONFIG_SMP */
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octeon_main_processor:
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.set pop
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.endm
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/*
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* Do SMP slave processor setup necessary before we can safely execute C code.
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*/
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.macro smp_slave_setup
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.endm
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#define USE_KEXEC_SMP_WAIT_FINAL
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.macro kexec_smp_wait_final
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.set push
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.set noreorder
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synci 0($0)
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.set pop
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.endm
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#endif /* __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H */
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