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20498d52c9
Commit e4c23e19aa2a ("clk: mediatek: Register clock gate with device")
introduces a helper function for the sole purpose of propagating a
struct device pointer to the clk API when registering the mtk-gate
clocks to take advantage of Runtime PM when/where needed and where
a power domain is defined in devicetree.
Function mtk_clk_register_gates() then becomes a wrapper around the
new mtk_clk_register_gates_with_dev() function that will simply pass
NULL as struct device: this is essential when registering drivers
with CLK_OF_DECLARE instead of as a platform device, as there will
be no struct device to pass... but we can as well simply have only
one function that always takes such pointer as a param and pass NULL
when unavoidable.
This commit removes the mtk_clk_register_gates() wrapper and renames
mtk_clk_register_gates_with_dev() to the former and all of the calls
to either of the two functions were fixed in all drivers in order to
reflect this change; also, to improve consistency with other kernel
functions, the pointer to struct device was moved as the first param.
Since a lot of MediaTek clock drivers are actually registering as a
platform device, but were still registering the mtk-gate clocks
without passing any struct device to the clock framework, they've
been changed to pass a valid one now, as to make all those platforms
able to use runtime power management where available.
While at it, some much needed indentation changes were also done.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: Markus Schneider-Pargmann <msp@baylibre.com>
Tested-by: Miles Chen <miles.chen@mediatek.com>
Link: https://lore.kernel.org/r/20230120092053.182923-4-angelogioacchino.delregno@collabora.com
Tested-by: Mingming Su <mingming.su@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
133 lines
4.3 KiB
C
133 lines
4.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2021 MediaTek Inc.
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* Author: Sam Shih <sam.shih@mediatek.com>
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* Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include <dt-bindings/clock/mt7986-clk.h>
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static const struct mtk_gate_regs sgmii0_cg_regs = {
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.set_ofs = 0xe4,
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.clr_ofs = 0xe4,
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.sta_ofs = 0xe4,
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};
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#define GATE_SGMII0(_id, _name, _parent, _shift) \
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{ \
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.id = _id, .name = _name, .parent_name = _parent, \
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.regs = &sgmii0_cg_regs, .shift = _shift, \
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.ops = &mtk_clk_gate_ops_no_setclr_inv, \
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}
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static const struct mtk_gate sgmii0_clks[] __initconst = {
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GATE_SGMII0(CLK_SGMII0_TX250M_EN, "sgmii0_tx250m_en", "top_xtal", 2),
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GATE_SGMII0(CLK_SGMII0_RX250M_EN, "sgmii0_rx250m_en", "top_xtal", 3),
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GATE_SGMII0(CLK_SGMII0_CDR_REF, "sgmii0_cdr_ref", "top_xtal", 4),
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GATE_SGMII0(CLK_SGMII0_CDR_FB, "sgmii0_cdr_fb", "top_xtal", 5),
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};
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static const struct mtk_gate_regs sgmii1_cg_regs = {
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.set_ofs = 0xe4,
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.clr_ofs = 0xe4,
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.sta_ofs = 0xe4,
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};
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#define GATE_SGMII1(_id, _name, _parent, _shift) \
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{ \
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.id = _id, .name = _name, .parent_name = _parent, \
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.regs = &sgmii1_cg_regs, .shift = _shift, \
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.ops = &mtk_clk_gate_ops_no_setclr_inv, \
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}
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static const struct mtk_gate sgmii1_clks[] __initconst = {
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GATE_SGMII1(CLK_SGMII1_TX250M_EN, "sgmii1_tx250m_en", "top_xtal", 2),
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GATE_SGMII1(CLK_SGMII1_RX250M_EN, "sgmii1_rx250m_en", "top_xtal", 3),
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GATE_SGMII1(CLK_SGMII1_CDR_REF, "sgmii1_cdr_ref", "top_xtal", 4),
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GATE_SGMII1(CLK_SGMII1_CDR_FB, "sgmii1_cdr_fb", "top_xtal", 5),
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};
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static const struct mtk_gate_regs eth_cg_regs = {
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.set_ofs = 0x30,
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.clr_ofs = 0x30,
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.sta_ofs = 0x30,
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};
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#define GATE_ETH(_id, _name, _parent, _shift) \
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{ \
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.id = _id, .name = _name, .parent_name = _parent, \
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.regs = ð_cg_regs, .shift = _shift, \
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.ops = &mtk_clk_gate_ops_no_setclr_inv, \
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}
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static const struct mtk_gate eth_clks[] __initconst = {
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GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x_sel", 6),
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GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m_sel", 7),
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GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m_sel", 8),
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GATE_ETH(CLK_ETH_WOCPU1_EN, "eth_wocpu1_en", "netsys_mcu_sel", 14),
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GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_mcu_sel", 15),
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};
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static void __init mtk_sgmiisys_0_init(struct device_node *node)
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{
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struct clk_hw_onecell_data *clk_data;
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int r;
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clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks));
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mtk_clk_register_gates(NULL, node, sgmii0_clks,
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ARRAY_SIZE(sgmii0_clks), clk_data);
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r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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if (r)
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pr_err("%s(): could not register clock provider: %d\n",
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__func__, r);
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}
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CLK_OF_DECLARE(mtk_sgmiisys_0, "mediatek,mt7986-sgmiisys_0",
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mtk_sgmiisys_0_init);
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static void __init mtk_sgmiisys_1_init(struct device_node *node)
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{
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struct clk_hw_onecell_data *clk_data;
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int r;
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clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks));
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mtk_clk_register_gates(NULL, node, sgmii1_clks,
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ARRAY_SIZE(sgmii1_clks), clk_data);
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r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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if (r)
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pr_err("%s(): could not register clock provider: %d\n",
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__func__, r);
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}
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CLK_OF_DECLARE(mtk_sgmiisys_1, "mediatek,mt7986-sgmiisys_1",
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mtk_sgmiisys_1_init);
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static void __init mtk_ethsys_init(struct device_node *node)
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{
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struct clk_hw_onecell_data *clk_data;
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int r;
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clk_data = mtk_alloc_clk_data(ARRAY_SIZE(eth_clks));
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mtk_clk_register_gates(NULL, node, eth_clks, ARRAY_SIZE(eth_clks), clk_data);
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r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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if (r)
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pr_err("%s(): could not register clock provider: %d\n",
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__func__, r);
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}
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CLK_OF_DECLARE(mtk_ethsys, "mediatek,mt7986-ethsys", mtk_ethsys_init);
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