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e16a2c7ace
On modern Renesas SoCs, all PFC registers are 32-bit, and all callers of
sh_pfc_{read,write}_reg() already operate on 32-bit registers only.
Hence make the 32-bit width implicit, and rename the functions to
sh_pfc_{read,write}() to shorten lines.
All accesses to 8-bit or 16-bit registers are still done using
sh_pfc_{read,write}_raw_reg().
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
40 lines
1.1 KiB
C
40 lines
1.1 KiB
C
/*
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* SuperH Pin Function Controller support.
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*
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* Copyright (C) 2012 Renesas Solutions Corp.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __SH_PFC_CORE_H__
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#define __SH_PFC_CORE_H__
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#include <linux/types.h>
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#include "sh_pfc.h"
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struct sh_pfc_pin_range {
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u16 start;
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u16 end;
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};
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int sh_pfc_register_gpiochip(struct sh_pfc *pfc);
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int sh_pfc_register_pinctrl(struct sh_pfc *pfc);
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u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width);
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void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
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u32 data);
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u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg);
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void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data);
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int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin);
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int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);
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const struct sh_pfc_bias_info *
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sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info,
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unsigned int num, unsigned int pin);
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#endif /* __SH_PFC_CORE_H__ */
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