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https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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5d5d353bed
This introduces support for the remoteproc on Mediatek MT8188, and enables caches for MT8186 SCP. It adds support for PRU cores found on the TI K3 AM62x SoCs. It moves the recovery work after a firmware crash to an unbound workqueue, to allow recovery to happen in parallel. A new DMA API is introduced to release dma_mem for a device. It adds support a panic handler for the Qualcomm modem remoteproc, with the goal of having caches flushed in memory dumps for post-mortem debugging and it introduces a mechanism to wait for the modem firmware on SM8450 to decrypt part of its memory for post-mortem debugging. Qualcomm sysmon is restricted to only inform remote processors about peers that are actually running, to avoid a race where Linux tries to notify a recovering remote processor about its peers new state. A mechanism for waiting for the sysmon connection to be established is also introduced, to avoid out-of-sync updates for rapidly restarting remote processors. A number of Devicetree binding cleanups and conversions to YAML are introduced, to facilitate Devicetree validation. Lastly it introduces a number of smaller fixes and cleanups in the core and a few different drivers. -----BEGIN PGP SIGNATURE----- iQJPBAABCAA5FiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmLxXTUbHGJqb3JuLmFu ZGVyc3NvbkBsaW5hcm8ub3JnAAoJEAsfOT8Nma3F6lcQAKEAtkd7dRChx5Y11h8J BdUmqYTGrlZCfZhGePgUgm9KXvf+BwjnYgZGNPVsno0h9/taY6pWggGz1/hMeD97 oTFrzZreOEHmrB7tKCQmzKdHzlVaf1aMifzz1BkICH+TRG2t/V3ycr+KJhyCK6IV CcsQ6D4FRdVDTWHEizWRewO7uFzaA3CWlr7uSY99aDMXikxSSGU7TgkH8ac04TU/ Z1+X2uClOa7IzaQX6dSm5lzZGDACatA0+WLFBf6LlEC2XtywKxPHq60QjWQwuXth /5mljBbIyW+5Qblm1r1gaipOCd6bGUvlY+0TdqbLlK8LpNIpDjFrt1mrmT4N2T+6 OAEyXglFvqHG8qjDafew5SxOEYbmFCMJ/oY+akNmpKS7Hhwx3AHeiZJdtu+bDY3O JeMQVCqrdMbrdBTNPJEjkTnhWCu1fPTn8STGaAEHgxsOPkarEtk37DuEy6KcV4It RTFY4mfnJrTfNeFpm60tOxg/zGYTjXol7uqY7BUTB7bV82W5+UTVGlpO8ayHvxru MwtN0HIDH/liXEsbt8INATXTEiTwJmEiqga53/EEWhMtnor3/xE2e26TZwzfq3sB Ue8TXnuQEN+v/ThHHvjyOZH0MONivYiW6iHkAuzq0RdnHIVDrFD/YQusWpxj7uuM nuk9OY0SbxMvUXIFKucg7zXJ =gbAX -----END PGP SIGNATURE----- Merge tag 'rproc-v5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux Pull remoteproc updates from Bjorn Andersson: "This introduces support for the remoteproc on Mediatek MT8188, and enables caches for MT8186 SCP. It adds support for PRU cores found on the TI K3 AM62x SoCs. It moves the recovery work after a firmware crash to an unbound workqueue, to allow recovery to happen in parallel. A new DMA API is introduced to release dma_mem for a device. It adds support a panic handler for the Qualcomm modem remoteproc, with the goal of having caches flushed in memory dumps for post-mortem debugging and it introduces a mechanism to wait for the modem firmware on SM8450 to decrypt part of its memory for post-mortem debugging. Qualcomm sysmon is restricted to only inform remote processors about peers that are actually running, to avoid a race where Linux tries to notify a recovering remote processor about its peers new state. A mechanism for waiting for the sysmon connection to be established is also introduced, to avoid out-of-sync updates for rapidly restarting remote processors. A number of Devicetree binding cleanups and conversions to YAML are introduced, to facilitate Devicetree validation. Lastly it introduces a number of smaller fixes and cleanups in the core and a few different drivers" * tag 'rproc-v5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux: (42 commits) remoteproc: qcom_q6v5_pas: Do not fail if regulators are not found drivers/remoteproc: fix repeated words in comments remoteproc: Directly use ida_alloc()/free() remoteproc: Use unbounded workqueue for recovery work remoteproc: using pm_runtime_resume_and_get instead of pm_runtime_get_sync remoteproc: qcom_q6v5_pas: Deal silently with optional px and cx regulators remoteproc: sysmon: Send sysmon state only for running rprocs remoteproc: sysmon: Wait for SSCTL service to come up remoteproc: qcom: q6v5: Set q6 state to offline on receiving wdog irq remoteproc: qcom: pas: Check if coredump is enabled remoteproc: qcom: pas: Mark devices as wakeup capable remoteproc: qcom: pas: Mark va as io memory remoteproc: qcom: pas: Add decrypt shutdown support for modem remoteproc: qcom: q6v5-mss: add powerdomains to MSM8996 config remoteproc: qcom_q6v5: Introduce panic handler for MSS remoteproc: qcom_q6v5_mss: Update MBA log info remoteproc: qcom: correct kerneldoc remoteproc: qcom_q6v5_mss: map/unmap metadata region before/after use remoteproc: qcom: using pm_runtime_resume_and_get to simplify the code remoteproc: mediatek: Support MT8188 SCP ...
450 lines
15 KiB
C
450 lines
15 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* This header is for implementations of dma_map_ops and related code.
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* It should not be included in drivers just using the DMA API.
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*/
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#ifndef _LINUX_DMA_MAP_OPS_H
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#define _LINUX_DMA_MAP_OPS_H
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#include <linux/dma-mapping.h>
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#include <linux/pgtable.h>
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struct cma;
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/*
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* Values for struct dma_map_ops.flags:
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*
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* DMA_F_PCI_P2PDMA_SUPPORTED: Indicates the dma_map_ops implementation can
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* handle PCI P2PDMA pages in the map_sg/unmap_sg operation.
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*/
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#define DMA_F_PCI_P2PDMA_SUPPORTED (1 << 0)
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struct dma_map_ops {
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unsigned int flags;
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void *(*alloc)(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t gfp,
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unsigned long attrs);
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void (*free)(struct device *dev, size_t size, void *vaddr,
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dma_addr_t dma_handle, unsigned long attrs);
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struct page *(*alloc_pages)(struct device *dev, size_t size,
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dma_addr_t *dma_handle, enum dma_data_direction dir,
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gfp_t gfp);
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void (*free_pages)(struct device *dev, size_t size, struct page *vaddr,
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dma_addr_t dma_handle, enum dma_data_direction dir);
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struct sg_table *(*alloc_noncontiguous)(struct device *dev, size_t size,
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enum dma_data_direction dir, gfp_t gfp,
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unsigned long attrs);
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void (*free_noncontiguous)(struct device *dev, size_t size,
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struct sg_table *sgt, enum dma_data_direction dir);
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int (*mmap)(struct device *, struct vm_area_struct *,
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void *, dma_addr_t, size_t, unsigned long attrs);
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int (*get_sgtable)(struct device *dev, struct sg_table *sgt,
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void *cpu_addr, dma_addr_t dma_addr, size_t size,
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unsigned long attrs);
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dma_addr_t (*map_page)(struct device *dev, struct page *page,
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unsigned long offset, size_t size,
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enum dma_data_direction dir, unsigned long attrs);
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void (*unmap_page)(struct device *dev, dma_addr_t dma_handle,
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size_t size, enum dma_data_direction dir,
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unsigned long attrs);
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/*
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* map_sg should return a negative error code on error. See
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* dma_map_sgtable() for a list of appropriate error codes
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* and their meanings.
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*/
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int (*map_sg)(struct device *dev, struct scatterlist *sg, int nents,
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enum dma_data_direction dir, unsigned long attrs);
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void (*unmap_sg)(struct device *dev, struct scatterlist *sg, int nents,
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enum dma_data_direction dir, unsigned long attrs);
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dma_addr_t (*map_resource)(struct device *dev, phys_addr_t phys_addr,
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size_t size, enum dma_data_direction dir,
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unsigned long attrs);
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void (*unmap_resource)(struct device *dev, dma_addr_t dma_handle,
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size_t size, enum dma_data_direction dir,
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unsigned long attrs);
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void (*sync_single_for_cpu)(struct device *dev, dma_addr_t dma_handle,
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size_t size, enum dma_data_direction dir);
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void (*sync_single_for_device)(struct device *dev,
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dma_addr_t dma_handle, size_t size,
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enum dma_data_direction dir);
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void (*sync_sg_for_cpu)(struct device *dev, struct scatterlist *sg,
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int nents, enum dma_data_direction dir);
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void (*sync_sg_for_device)(struct device *dev, struct scatterlist *sg,
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int nents, enum dma_data_direction dir);
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void (*cache_sync)(struct device *dev, void *vaddr, size_t size,
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enum dma_data_direction direction);
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int (*dma_supported)(struct device *dev, u64 mask);
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u64 (*get_required_mask)(struct device *dev);
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size_t (*max_mapping_size)(struct device *dev);
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size_t (*opt_mapping_size)(void);
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unsigned long (*get_merge_boundary)(struct device *dev);
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};
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#ifdef CONFIG_DMA_OPS
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#include <asm/dma-mapping.h>
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static inline const struct dma_map_ops *get_dma_ops(struct device *dev)
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{
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if (dev->dma_ops)
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return dev->dma_ops;
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return get_arch_dma_ops(dev->bus);
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}
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static inline void set_dma_ops(struct device *dev,
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const struct dma_map_ops *dma_ops)
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{
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dev->dma_ops = dma_ops;
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}
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#else /* CONFIG_DMA_OPS */
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static inline const struct dma_map_ops *get_dma_ops(struct device *dev)
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{
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return NULL;
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}
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static inline void set_dma_ops(struct device *dev,
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const struct dma_map_ops *dma_ops)
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{
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}
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#endif /* CONFIG_DMA_OPS */
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#ifdef CONFIG_DMA_CMA
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extern struct cma *dma_contiguous_default_area;
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static inline struct cma *dev_get_cma_area(struct device *dev)
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{
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if (dev && dev->cma_area)
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return dev->cma_area;
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return dma_contiguous_default_area;
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}
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void dma_contiguous_reserve(phys_addr_t addr_limit);
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int __init dma_contiguous_reserve_area(phys_addr_t size, phys_addr_t base,
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phys_addr_t limit, struct cma **res_cma, bool fixed);
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struct page *dma_alloc_from_contiguous(struct device *dev, size_t count,
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unsigned int order, bool no_warn);
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bool dma_release_from_contiguous(struct device *dev, struct page *pages,
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int count);
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struct page *dma_alloc_contiguous(struct device *dev, size_t size, gfp_t gfp);
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void dma_free_contiguous(struct device *dev, struct page *page, size_t size);
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void dma_contiguous_early_fixup(phys_addr_t base, unsigned long size);
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#else /* CONFIG_DMA_CMA */
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static inline struct cma *dev_get_cma_area(struct device *dev)
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{
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return NULL;
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}
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static inline void dma_contiguous_reserve(phys_addr_t limit)
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{
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}
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static inline int dma_contiguous_reserve_area(phys_addr_t size,
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phys_addr_t base, phys_addr_t limit, struct cma **res_cma,
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bool fixed)
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{
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return -ENOSYS;
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}
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static inline struct page *dma_alloc_from_contiguous(struct device *dev,
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size_t count, unsigned int order, bool no_warn)
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{
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return NULL;
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}
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static inline bool dma_release_from_contiguous(struct device *dev,
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struct page *pages, int count)
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{
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return false;
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}
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/* Use fallback alloc() and free() when CONFIG_DMA_CMA=n */
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static inline struct page *dma_alloc_contiguous(struct device *dev, size_t size,
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gfp_t gfp)
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{
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return NULL;
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}
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static inline void dma_free_contiguous(struct device *dev, struct page *page,
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size_t size)
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{
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__free_pages(page, get_order(size));
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}
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#endif /* CONFIG_DMA_CMA*/
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#ifdef CONFIG_DMA_PERNUMA_CMA
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void dma_pernuma_cma_reserve(void);
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#else
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static inline void dma_pernuma_cma_reserve(void) { }
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#endif /* CONFIG_DMA_PERNUMA_CMA */
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#ifdef CONFIG_DMA_DECLARE_COHERENT
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int dma_declare_coherent_memory(struct device *dev, phys_addr_t phys_addr,
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dma_addr_t device_addr, size_t size);
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void dma_release_coherent_memory(struct device *dev);
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int dma_alloc_from_dev_coherent(struct device *dev, ssize_t size,
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dma_addr_t *dma_handle, void **ret);
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int dma_release_from_dev_coherent(struct device *dev, int order, void *vaddr);
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int dma_mmap_from_dev_coherent(struct device *dev, struct vm_area_struct *vma,
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void *cpu_addr, size_t size, int *ret);
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#else
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static inline int dma_declare_coherent_memory(struct device *dev,
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phys_addr_t phys_addr, dma_addr_t device_addr, size_t size)
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{
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return -ENOSYS;
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}
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#define dma_alloc_from_dev_coherent(dev, size, handle, ret) (0)
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#define dma_release_from_dev_coherent(dev, order, vaddr) (0)
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#define dma_mmap_from_dev_coherent(dev, vma, vaddr, order, ret) (0)
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static inline void dma_release_coherent_memory(struct device *dev) { }
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#endif /* CONFIG_DMA_DECLARE_COHERENT */
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#ifdef CONFIG_DMA_GLOBAL_POOL
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void *dma_alloc_from_global_coherent(struct device *dev, ssize_t size,
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dma_addr_t *dma_handle);
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int dma_release_from_global_coherent(int order, void *vaddr);
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int dma_mmap_from_global_coherent(struct vm_area_struct *vma, void *cpu_addr,
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size_t size, int *ret);
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int dma_init_global_coherent(phys_addr_t phys_addr, size_t size);
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#else
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static inline void *dma_alloc_from_global_coherent(struct device *dev,
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ssize_t size, dma_addr_t *dma_handle)
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{
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return NULL;
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}
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static inline int dma_release_from_global_coherent(int order, void *vaddr)
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{
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return 0;
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}
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static inline int dma_mmap_from_global_coherent(struct vm_area_struct *vma,
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void *cpu_addr, size_t size, int *ret)
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{
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return 0;
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}
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#endif /* CONFIG_DMA_GLOBAL_POOL */
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/*
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* This is the actual return value from the ->alloc_noncontiguous method.
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* The users of the DMA API should only care about the sg_table, but to make
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* the DMA-API internal vmaping and freeing easier we stash away the page
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* array as well (except for the fallback case). This can go away any time,
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* e.g. when a vmap-variant that takes a scatterlist comes along.
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*/
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struct dma_sgt_handle {
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struct sg_table sgt;
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struct page **pages;
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};
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#define sgt_handle(sgt) \
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container_of((sgt), struct dma_sgt_handle, sgt)
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int dma_common_get_sgtable(struct device *dev, struct sg_table *sgt,
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void *cpu_addr, dma_addr_t dma_addr, size_t size,
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unsigned long attrs);
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int dma_common_mmap(struct device *dev, struct vm_area_struct *vma,
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void *cpu_addr, dma_addr_t dma_addr, size_t size,
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unsigned long attrs);
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struct page *dma_common_alloc_pages(struct device *dev, size_t size,
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dma_addr_t *dma_handle, enum dma_data_direction dir, gfp_t gfp);
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void dma_common_free_pages(struct device *dev, size_t size, struct page *vaddr,
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dma_addr_t dma_handle, enum dma_data_direction dir);
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struct page **dma_common_find_pages(void *cpu_addr);
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void *dma_common_contiguous_remap(struct page *page, size_t size, pgprot_t prot,
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const void *caller);
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void *dma_common_pages_remap(struct page **pages, size_t size, pgprot_t prot,
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const void *caller);
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void dma_common_free_remap(void *cpu_addr, size_t size);
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struct page *dma_alloc_from_pool(struct device *dev, size_t size,
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void **cpu_addr, gfp_t flags,
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bool (*phys_addr_ok)(struct device *, phys_addr_t, size_t));
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bool dma_free_from_pool(struct device *dev, void *start, size_t size);
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int dma_direct_set_offset(struct device *dev, phys_addr_t cpu_start,
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dma_addr_t dma_start, u64 size);
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#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \
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defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \
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defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL)
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extern bool dma_default_coherent;
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static inline bool dev_is_dma_coherent(struct device *dev)
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{
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return dev->dma_coherent;
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}
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#else
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static inline bool dev_is_dma_coherent(struct device *dev)
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{
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return true;
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}
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#endif /* CONFIG_ARCH_HAS_DMA_COHERENCE_H */
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void *arch_dma_alloc(struct device *dev, size_t size, dma_addr_t *dma_handle,
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gfp_t gfp, unsigned long attrs);
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void arch_dma_free(struct device *dev, size_t size, void *cpu_addr,
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dma_addr_t dma_addr, unsigned long attrs);
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#ifdef CONFIG_MMU
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/*
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* Page protection so that devices that can't snoop CPU caches can use the
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* memory coherently. We default to pgprot_noncached which is usually used
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* for ioremap as a safe bet, but architectures can override this with less
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* strict semantics if possible.
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*/
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#ifndef pgprot_dmacoherent
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#define pgprot_dmacoherent(prot) pgprot_noncached(prot)
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#endif
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pgprot_t dma_pgprot(struct device *dev, pgprot_t prot, unsigned long attrs);
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#else
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static inline pgprot_t dma_pgprot(struct device *dev, pgprot_t prot,
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unsigned long attrs)
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{
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return prot; /* no protection bits supported without page tables */
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}
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#endif /* CONFIG_MMU */
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#ifdef CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE
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void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
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enum dma_data_direction dir);
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#else
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static inline void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
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enum dma_data_direction dir)
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{
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}
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#endif /* ARCH_HAS_SYNC_DMA_FOR_DEVICE */
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#ifdef CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU
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void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
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enum dma_data_direction dir);
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#else
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static inline void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
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enum dma_data_direction dir)
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{
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}
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#endif /* ARCH_HAS_SYNC_DMA_FOR_CPU */
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#ifdef CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
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void arch_sync_dma_for_cpu_all(void);
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#else
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static inline void arch_sync_dma_for_cpu_all(void)
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{
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}
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#endif /* CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL */
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#ifdef CONFIG_ARCH_HAS_DMA_PREP_COHERENT
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void arch_dma_prep_coherent(struct page *page, size_t size);
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#else
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static inline void arch_dma_prep_coherent(struct page *page, size_t size)
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{
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}
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#endif /* CONFIG_ARCH_HAS_DMA_PREP_COHERENT */
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#ifdef CONFIG_ARCH_HAS_DMA_MARK_CLEAN
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void arch_dma_mark_clean(phys_addr_t paddr, size_t size);
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#else
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static inline void arch_dma_mark_clean(phys_addr_t paddr, size_t size)
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{
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}
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#endif /* ARCH_HAS_DMA_MARK_CLEAN */
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|
|
|
void *arch_dma_set_uncached(void *addr, size_t size);
|
|
void arch_dma_clear_uncached(void *addr, size_t size);
|
|
|
|
#ifdef CONFIG_ARCH_HAS_DMA_MAP_DIRECT
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|
bool arch_dma_map_page_direct(struct device *dev, phys_addr_t addr);
|
|
bool arch_dma_unmap_page_direct(struct device *dev, dma_addr_t dma_handle);
|
|
bool arch_dma_map_sg_direct(struct device *dev, struct scatterlist *sg,
|
|
int nents);
|
|
bool arch_dma_unmap_sg_direct(struct device *dev, struct scatterlist *sg,
|
|
int nents);
|
|
#else
|
|
#define arch_dma_map_page_direct(d, a) (false)
|
|
#define arch_dma_unmap_page_direct(d, a) (false)
|
|
#define arch_dma_map_sg_direct(d, s, n) (false)
|
|
#define arch_dma_unmap_sg_direct(d, s, n) (false)
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_HAS_SETUP_DMA_OPS
|
|
void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
|
|
const struct iommu_ops *iommu, bool coherent);
|
|
#else
|
|
static inline void arch_setup_dma_ops(struct device *dev, u64 dma_base,
|
|
u64 size, const struct iommu_ops *iommu, bool coherent)
|
|
{
|
|
}
|
|
#endif /* CONFIG_ARCH_HAS_SETUP_DMA_OPS */
|
|
|
|
#ifdef CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS
|
|
void arch_teardown_dma_ops(struct device *dev);
|
|
#else
|
|
static inline void arch_teardown_dma_ops(struct device *dev)
|
|
{
|
|
}
|
|
#endif /* CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS */
|
|
|
|
#ifdef CONFIG_DMA_API_DEBUG
|
|
void dma_debug_add_bus(struct bus_type *bus);
|
|
void debug_dma_dump_mappings(struct device *dev);
|
|
#else
|
|
static inline void dma_debug_add_bus(struct bus_type *bus)
|
|
{
|
|
}
|
|
static inline void debug_dma_dump_mappings(struct device *dev)
|
|
{
|
|
}
|
|
#endif /* CONFIG_DMA_API_DEBUG */
|
|
|
|
extern const struct dma_map_ops dma_dummy_ops;
|
|
|
|
enum pci_p2pdma_map_type {
|
|
/*
|
|
* PCI_P2PDMA_MAP_UNKNOWN: Used internally for indicating the mapping
|
|
* type hasn't been calculated yet. Functions that return this enum
|
|
* never return this value.
|
|
*/
|
|
PCI_P2PDMA_MAP_UNKNOWN = 0,
|
|
|
|
/*
|
|
* PCI_P2PDMA_MAP_NOT_SUPPORTED: Indicates the transaction will
|
|
* traverse the host bridge and the host bridge is not in the
|
|
* allowlist. DMA Mapping routines should return an error when
|
|
* this is returned.
|
|
*/
|
|
PCI_P2PDMA_MAP_NOT_SUPPORTED,
|
|
|
|
/*
|
|
* PCI_P2PDMA_BUS_ADDR: Indicates that two devices can talk to
|
|
* each other directly through a PCI switch and the transaction will
|
|
* not traverse the host bridge. Such a mapping should program
|
|
* the DMA engine with PCI bus addresses.
|
|
*/
|
|
PCI_P2PDMA_MAP_BUS_ADDR,
|
|
|
|
/*
|
|
* PCI_P2PDMA_MAP_THRU_HOST_BRIDGE: Indicates two devices can talk
|
|
* to each other, but the transaction traverses a host bridge on the
|
|
* allowlist. In this case, a normal mapping either with CPU physical
|
|
* addresses (in the case of dma-direct) or IOVA addresses (in the
|
|
* case of IOMMUs) should be used to program the DMA engine.
|
|
*/
|
|
PCI_P2PDMA_MAP_THRU_HOST_BRIDGE,
|
|
};
|
|
|
|
struct pci_p2pdma_map_state {
|
|
struct dev_pagemap *pgmap;
|
|
int map;
|
|
u64 bus_off;
|
|
};
|
|
|
|
#ifdef CONFIG_PCI_P2PDMA
|
|
enum pci_p2pdma_map_type
|
|
pci_p2pdma_map_segment(struct pci_p2pdma_map_state *state, struct device *dev,
|
|
struct scatterlist *sg);
|
|
#else /* CONFIG_PCI_P2PDMA */
|
|
static inline enum pci_p2pdma_map_type
|
|
pci_p2pdma_map_segment(struct pci_p2pdma_map_state *state, struct device *dev,
|
|
struct scatterlist *sg)
|
|
{
|
|
return PCI_P2PDMA_MAP_NOT_SUPPORTED;
|
|
}
|
|
#endif /* CONFIG_PCI_P2PDMA */
|
|
|
|
#endif /* _LINUX_DMA_MAP_OPS_H */
|