mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
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236 lines
7.3 KiB
C
236 lines
7.3 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2023 Nuvoton Technology Corp.
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* Author: Chi-Fang Li <cfli0@nuvoton.com>
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*/
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#include <linux/bits.h>
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#include <linux/container_of.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/reboot.h>
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#include <linux/reset-controller.h>
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#include <linux/spinlock.h>
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#include <dt-bindings/reset/nuvoton,ma35d1-reset.h>
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struct ma35d1_reset_data {
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struct reset_controller_dev rcdev;
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struct notifier_block restart_handler;
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void __iomem *base;
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/* protect registers against concurrent read-modify-write */
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spinlock_t lock;
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};
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static const struct {
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u32 reg_ofs;
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u32 bit;
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} ma35d1_reset_map[] = {
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[MA35D1_RESET_CHIP] = {0x20, 0},
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[MA35D1_RESET_CA35CR0] = {0x20, 1},
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[MA35D1_RESET_CA35CR1] = {0x20, 2},
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[MA35D1_RESET_CM4] = {0x20, 3},
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[MA35D1_RESET_PDMA0] = {0x20, 4},
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[MA35D1_RESET_PDMA1] = {0x20, 5},
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[MA35D1_RESET_PDMA2] = {0x20, 6},
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[MA35D1_RESET_PDMA3] = {0x20, 7},
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[MA35D1_RESET_DISP] = {0x20, 9},
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[MA35D1_RESET_VCAP0] = {0x20, 10},
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[MA35D1_RESET_VCAP1] = {0x20, 11},
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[MA35D1_RESET_GFX] = {0x20, 12},
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[MA35D1_RESET_VDEC] = {0x20, 13},
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[MA35D1_RESET_WHC0] = {0x20, 14},
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[MA35D1_RESET_WHC1] = {0x20, 15},
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[MA35D1_RESET_GMAC0] = {0x20, 16},
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[MA35D1_RESET_GMAC1] = {0x20, 17},
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[MA35D1_RESET_HWSEM] = {0x20, 18},
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[MA35D1_RESET_EBI] = {0x20, 19},
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[MA35D1_RESET_HSUSBH0] = {0x20, 20},
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[MA35D1_RESET_HSUSBH1] = {0x20, 21},
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[MA35D1_RESET_HSUSBD] = {0x20, 22},
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[MA35D1_RESET_USBHL] = {0x20, 23},
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[MA35D1_RESET_SDH0] = {0x20, 24},
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[MA35D1_RESET_SDH1] = {0x20, 25},
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[MA35D1_RESET_NAND] = {0x20, 26},
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[MA35D1_RESET_GPIO] = {0x20, 27},
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[MA35D1_RESET_MCTLP] = {0x20, 28},
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[MA35D1_RESET_MCTLC] = {0x20, 29},
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[MA35D1_RESET_DDRPUB] = {0x20, 30},
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[MA35D1_RESET_TMR0] = {0x24, 2},
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[MA35D1_RESET_TMR1] = {0x24, 3},
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[MA35D1_RESET_TMR2] = {0x24, 4},
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[MA35D1_RESET_TMR3] = {0x24, 5},
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[MA35D1_RESET_I2C0] = {0x24, 8},
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[MA35D1_RESET_I2C1] = {0x24, 9},
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[MA35D1_RESET_I2C2] = {0x24, 10},
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[MA35D1_RESET_I2C3] = {0x24, 11},
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[MA35D1_RESET_QSPI0] = {0x24, 12},
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[MA35D1_RESET_SPI0] = {0x24, 13},
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[MA35D1_RESET_SPI1] = {0x24, 14},
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[MA35D1_RESET_SPI2] = {0x24, 15},
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[MA35D1_RESET_UART0] = {0x24, 16},
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[MA35D1_RESET_UART1] = {0x24, 17},
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[MA35D1_RESET_UART2] = {0x24, 18},
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[MA35D1_RESET_UART3] = {0x24, 19},
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[MA35D1_RESET_UART4] = {0x24, 20},
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[MA35D1_RESET_UART5] = {0x24, 21},
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[MA35D1_RESET_UART6] = {0x24, 22},
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[MA35D1_RESET_UART7] = {0x24, 23},
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[MA35D1_RESET_CANFD0] = {0x24, 24},
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[MA35D1_RESET_CANFD1] = {0x24, 25},
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[MA35D1_RESET_EADC0] = {0x24, 28},
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[MA35D1_RESET_I2S0] = {0x24, 29},
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[MA35D1_RESET_SC0] = {0x28, 0},
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[MA35D1_RESET_SC1] = {0x28, 1},
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[MA35D1_RESET_QSPI1] = {0x28, 4},
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[MA35D1_RESET_SPI3] = {0x28, 6},
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[MA35D1_RESET_EPWM0] = {0x28, 16},
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[MA35D1_RESET_EPWM1] = {0x28, 17},
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[MA35D1_RESET_QEI0] = {0x28, 22},
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[MA35D1_RESET_QEI1] = {0x28, 23},
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[MA35D1_RESET_ECAP0] = {0x28, 26},
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[MA35D1_RESET_ECAP1] = {0x28, 27},
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[MA35D1_RESET_CANFD2] = {0x28, 28},
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[MA35D1_RESET_ADC0] = {0x28, 31},
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[MA35D1_RESET_TMR4] = {0x2C, 0},
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[MA35D1_RESET_TMR5] = {0x2C, 1},
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[MA35D1_RESET_TMR6] = {0x2C, 2},
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[MA35D1_RESET_TMR7] = {0x2C, 3},
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[MA35D1_RESET_TMR8] = {0x2C, 4},
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[MA35D1_RESET_TMR9] = {0x2C, 5},
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[MA35D1_RESET_TMR10] = {0x2C, 6},
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[MA35D1_RESET_TMR11] = {0x2C, 7},
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[MA35D1_RESET_UART8] = {0x2C, 8},
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[MA35D1_RESET_UART9] = {0x2C, 9},
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[MA35D1_RESET_UART10] = {0x2C, 10},
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[MA35D1_RESET_UART11] = {0x2C, 11},
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[MA35D1_RESET_UART12] = {0x2C, 12},
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[MA35D1_RESET_UART13] = {0x2C, 13},
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[MA35D1_RESET_UART14] = {0x2C, 14},
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[MA35D1_RESET_UART15] = {0x2C, 15},
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[MA35D1_RESET_UART16] = {0x2C, 16},
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[MA35D1_RESET_I2S1] = {0x2C, 17},
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[MA35D1_RESET_I2C4] = {0x2C, 18},
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[MA35D1_RESET_I2C5] = {0x2C, 19},
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[MA35D1_RESET_EPWM2] = {0x2C, 20},
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[MA35D1_RESET_ECAP2] = {0x2C, 21},
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[MA35D1_RESET_QEI2] = {0x2C, 22},
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[MA35D1_RESET_CANFD3] = {0x2C, 23},
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[MA35D1_RESET_KPI] = {0x2C, 24},
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[MA35D1_RESET_GIC] = {0x2C, 28},
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[MA35D1_RESET_SSMCC] = {0x2C, 30},
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[MA35D1_RESET_SSPCC] = {0x2C, 31}
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};
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static int ma35d1_restart_handler(struct notifier_block *this, unsigned long mode, void *cmd)
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{
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struct ma35d1_reset_data *data =
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container_of(this, struct ma35d1_reset_data, restart_handler);
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u32 id = MA35D1_RESET_CHIP;
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writel_relaxed(BIT(ma35d1_reset_map[id].bit),
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data->base + ma35d1_reset_map[id].reg_ofs);
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return 0;
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}
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static int ma35d1_reset_update(struct reset_controller_dev *rcdev, unsigned long id, bool assert)
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{
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struct ma35d1_reset_data *data = container_of(rcdev, struct ma35d1_reset_data, rcdev);
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unsigned long flags;
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u32 reg;
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if (WARN_ON_ONCE(id >= ARRAY_SIZE(ma35d1_reset_map)))
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return -EINVAL;
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spin_lock_irqsave(&data->lock, flags);
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reg = readl_relaxed(data->base + ma35d1_reset_map[id].reg_ofs);
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if (assert)
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reg |= BIT(ma35d1_reset_map[id].bit);
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else
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reg &= ~(BIT(ma35d1_reset_map[id].bit));
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writel_relaxed(reg, data->base + ma35d1_reset_map[id].reg_ofs);
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spin_unlock_irqrestore(&data->lock, flags);
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return 0;
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}
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static int ma35d1_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
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{
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return ma35d1_reset_update(rcdev, id, true);
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}
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static int ma35d1_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
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{
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return ma35d1_reset_update(rcdev, id, false);
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}
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static int ma35d1_reset_status(struct reset_controller_dev *rcdev, unsigned long id)
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{
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struct ma35d1_reset_data *data = container_of(rcdev, struct ma35d1_reset_data, rcdev);
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u32 reg;
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if (WARN_ON_ONCE(id >= ARRAY_SIZE(ma35d1_reset_map)))
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return -EINVAL;
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reg = readl_relaxed(data->base + ma35d1_reset_map[id].reg_ofs);
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return !!(reg & BIT(ma35d1_reset_map[id].bit));
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}
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static const struct reset_control_ops ma35d1_reset_ops = {
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.assert = ma35d1_reset_assert,
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.deassert = ma35d1_reset_deassert,
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.status = ma35d1_reset_status,
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};
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static const struct of_device_id ma35d1_reset_dt_ids[] = {
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{ .compatible = "nuvoton,ma35d1-reset" },
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{ },
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};
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static int ma35d1_reset_probe(struct platform_device *pdev)
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{
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struct ma35d1_reset_data *reset_data;
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struct device *dev = &pdev->dev;
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int err;
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if (!pdev->dev.of_node) {
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dev_err(&pdev->dev, "Device tree node not found\n");
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return -EINVAL;
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}
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reset_data = devm_kzalloc(dev, sizeof(*reset_data), GFP_KERNEL);
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if (!reset_data)
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return -ENOMEM;
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reset_data->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(reset_data->base))
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return PTR_ERR(reset_data->base);
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reset_data->rcdev.owner = THIS_MODULE;
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reset_data->rcdev.nr_resets = MA35D1_RESET_COUNT;
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reset_data->rcdev.ops = &ma35d1_reset_ops;
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reset_data->rcdev.of_node = dev->of_node;
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reset_data->restart_handler.notifier_call = ma35d1_restart_handler;
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reset_data->restart_handler.priority = 192;
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spin_lock_init(&reset_data->lock);
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err = register_restart_handler(&reset_data->restart_handler);
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if (err)
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dev_warn(&pdev->dev, "failed to register restart handler\n");
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return devm_reset_controller_register(dev, &reset_data->rcdev);
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}
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static struct platform_driver ma35d1_reset_driver = {
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.probe = ma35d1_reset_probe,
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.driver = {
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.name = "ma35d1-reset",
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.of_match_table = ma35d1_reset_dt_ids,
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},
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};
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builtin_platform_driver(ma35d1_reset_driver);
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