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linux-next/drivers/counter/Makefile

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treewide: Add SPDX license identifier - Makefile/Kconfig Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-19 13:07:45 +01:00
# SPDX-License-Identifier: GPL-2.0-only
counter: Introduce the Generic Counter interface This patch introduces the Generic Counter interface for supporting counter devices. In the context of the Generic Counter interface, a counter is defined as a device that reports one or more "counts" based on the state changes of one or more "signals" as evaluated by a defined "count function." Driver callbacks should be provided to communicate with the device: to read and write various Signals and Counts, and to set and get the "action mode" and "count function" for various Synapses and Counts respectively. To support a counter device, a driver must first allocate the available Counter Signals via counter_signal structures. These Signals should be stored as an array and set to the signals array member of an allocated counter_device structure before the Counter is registered to the system. Counter Counts may be allocated via counter_count structures, and respective Counter Signal associations (Synapses) made via counter_synapse structures. Associated counter_synapse structures are stored as an array and set to the the synapses array member of the respective counter_count structure. These counter_count structures are set to the counts array member of an allocated counter_device structure before the Counter is registered to the system. A counter device is registered to the system by passing the respective initialized counter_device structure to the counter_register function; similarly, the counter_unregister function unregisters the respective Counter. The devm_counter_register and devm_counter_unregister functions serve as device memory-managed versions of the counter_register and counter_unregister functions respectively. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-04-02 15:30:36 +09:00
#
# Makefile for Counter devices
#
obj-$(CONFIG_COUNTER) += counter.o
counter: Add character device interface This patch introduces a character device interface for the Counter subsystem. Device data is exposed through standard character device read operations. Device data is gathered when a Counter event is pushed by the respective Counter device driver. Configuration is handled via ioctl operations on the respective Counter character device node. Cc: David Lechner <david@lechnology.com> Cc: Gwendal Grignou <gwendal@chromium.org> Cc: Dan Carpenter <dan.carpenter@oracle.com> Cc: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com> Link: https://lore.kernel.org/r/b8b8c64b4065aedff43699ad1f0e2f8d1419c15b.1632884256.git.vilhelm.gray@gmail.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2021-09-29 12:15:59 +09:00
counter-y := counter-core.o counter-sysfs.o counter-chrdev.o
counter: 104-quad-8: Add Generic Counter interface support This patch adds support for the Generic Counter interface to the 104-QUAD-8 driver. The existing 104-QUAD-8 device interface should not be affected by this patch; all changes are intended as supplemental additions as perceived by the user. Generic Counter Counts are created for the eight quadrature channel counts, as well as their respective quadrature A and B Signals (which are associated via respective Synapse structures) and respective index Signals. The new Generic Counter interface sysfs attributes are intended to expose the same functionality and data available via the existing 104-QUAD-8 IIO device interface; the Generic Counter interface serves to provide the respective functionality and data in a standard way expected of counter devices. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-04-02 15:30:40 +09:00
obj-$(CONFIG_104_QUAD_8) += 104-quad-8.o
counter: add IRQ or GPIO based counter Add simple IRQ or GPIO base counter. This device is used to measure rotation speed of some agricultural devices, so no high frequency on the counter pin is expected. The maximal measurement frequency depends on the CPU and system load. On the idle iMX6S I was able to measure up to 20kHz without count drops. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Reviewed-by: William Breathitt Gray <vilhelm.gray@gmail.com> Link: https://lore.kernel.org/r/20210301080401.22190-3-o.rempel@pengutronix.de Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2021-03-01 09:04:01 +01:00
obj-$(CONFIG_INTERRUPT_CNT) += interrupt-cnt.o
counter: Add Renesas RZ/G2L MTU3a counter driver Add RZ/G2L MTU3a counter driver. This IP supports the following phase counting modes on MTU1 and MTU2 channels 1) 16-bit phase counting modes on MTU1 and MTU2 channels. 2) 32-bit phase counting mode by cascading MTU1 and MTU2 channels. This patch adds 3 counter value channels. count0: 16-bit phase counter value channel on MTU1 count1: 16-bit phase counter value channel on MTU2 count2: 32-bit phase counter value channel by cascading MTU1 and MTU2 channels. The external input phase clock pin for the counter value channels are as follows: count0: "MTCLKA-MTCLKB" count1: "MTCLKA-MTCLKB" or "MTCLKC-MTCLKD" count2: "MTCLKA-MTCLKB" or "MTCLKC-MTCLKD" Use the sysfs variable "external_input_phase_clock_select" to select the external input phase clock pin and "cascade_counts_enable" to enable/ disable cascading of channels. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: William Breathitt Gray <william.gray@linaro.org> Acked-by: William Breathitt Gray <william.gray@linaro.org> Signed-off-by: Lee Jones <lee@kernel.org> Link: https://lore.kernel.org/r/20230330111632.169434-5-biju.das.jz@bp.renesas.com
2023-03-30 12:16:30 +01:00
obj-$(CONFIG_RZ_MTU3_CNT) += rz-mtu3-cnt.o
counter: Add STM32 Timer quadrature encoder Implement counter part of the STM32 timer hardware block by using counter API. Hardware only supports X2 and X4 quadrature modes. A ceiling value can be set to define the maximum value reachable by the counter. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Co-authored-by: Fabrice Gasnier <fabrice.gasnier@st.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-04-02 15:30:42 +09:00
obj-$(CONFIG_STM32_TIMER_CNT) += stm32-timer-cnt.o
counter: stm32-lptimer: add counter device Add support for new counter device to stm32-lptimer. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-04-02 15:30:44 +09:00
obj-$(CONFIG_STM32_LPTIMER_CNT) += stm32-lptimer-cnt.o
counter: new TI eQEP driver This adds a new counter driver for the Texas Instruments Enhanced Quadrature Encoder Pulse (eQEP) module. Only very basic functionality is currently implemented - only enough to be able to read the position. The actual device has many more features which can be added to the driver on an as-needed basis. It is not possible to read the QEPA/B signal values in hardware, so that feature is omitted. The TI_PWMSS kernel option is selected in Kconfig to enable the parent bus, which is needed for power management. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2019-09-01 17:58:24 -05:00
obj-$(CONFIG_TI_EQEP) += ti-eqep.o
counter: add FlexTimer Module Quadrature decoder counter driver This driver exposes the counter for the quadrature decoder of the FlexTimer Module, present in the LS1021A soc. Signed-off-by: Patrick Havelange <patrick.havelange@essensium.com> Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-04-02 15:30:51 +09:00
obj-$(CONFIG_FTM_QUADDEC) += ftm-quaddec.o
counter: Add microchip TCB capture counter This drivers allows to use the capture mode of the Timer Counter Block hardware block available in Microchip SoCs through the counter subsystem. Two functions of the counter are supported for the moment: period capture and quadrature decoder. The latter is only supported by the SAMA5 series of SoCs. For the period capture mode a basic setup has been chosen that will reset the counter each time the period is actually reached. Of course the device offers much more possibilities. For quadrature mode, both channel 0 and 1 must be configured even if we only capture the position (no revolution/rotation). Signed-off-by: Kamel Bouhara <kamel.bouhara@bootlin.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-07-06 13:43:47 +02:00
obj-$(CONFIG_MICROCHIP_TCB_CAPTURE) += microchip-tcb-capture.o
counter: Add support for Intel Quadrature Encoder Peripheral Add support for Intel Quadrature Encoder Peripheral found on Intel Elkhart Lake platform. Initial implementation was done by Felipe Balbi while he was working at Intel with later changes from Raymond Tan and me. Co-developed-by: Felipe Balbi (Intel) <balbi@kernel.org> Signed-off-by: Felipe Balbi (Intel) <balbi@kernel.org> Co-developed-by: Raymond Tan <raymond.tan@intel.com> Signed-off-by: Raymond Tan <raymond.tan@intel.com> Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Acked-by: William Breathitt Gray <vilhelm.gray@gmail.com> Link: https://lore.kernel.org/r/20210602113259.158674-1-jarkko.nikula@linux.intel.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2021-06-02 14:32:59 +03:00
obj-$(CONFIG_INTEL_QEP) += intel-qep.o
counter: ti-ecap-capture: capture driver support for ECAP ECAP hardware on TI AM62x SoC supports capture feature. It can be used to timestamp events (falling/rising edges) detected on input signal. This commit adds capture driver support for ECAP hardware on AM62x SoC. In the ECAP hardware, capture pin can also be configured to be in PWM mode. Current implementation only supports capture operating mode. Hardware also supports timebase sync between multiple instances, but this driver supports simple independent capture functionality. Signed-off-by: Julien Panis <jpanis@baylibre.com> Link: https://lore.kernel.org/r/20220923142437.271328-4-jpanis@baylibre.com/ Signed-off-by: William Breathitt Gray <william.gray@linaro.org> Link: https://lore.kernel.org/r/25644ce1f2fd15d116977770ede20e024f658513.1664318353.git.william.gray@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-09-27 18:53:45 -04:00
obj-$(CONFIG_TI_ECAP_CAPTURE) += ti-ecap-capture.o
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