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66 lines
1.8 KiB
C
66 lines
1.8 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018 SiFive
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* Copyright (C) 2018 Andes Technology Corporation
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* Copyright (C) 2021 Western Digital Corporation or its affiliates.
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*
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*/
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#ifndef _ASM_RISCV_PERF_EVENT_H
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#define _ASM_RISCV_PERF_EVENT_H
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#include <linux/perf_event.h>
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#include <linux/ptrace.h>
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#include <linux/interrupt.h>
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#ifdef CONFIG_RISCV_PMU
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/*
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* The RISCV_MAX_COUNTERS parameter should be specified.
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*/
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#define RISCV_MAX_COUNTERS 64
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#define RISCV_OP_UNSUPP (-EOPNOTSUPP)
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#define RISCV_PMU_PDEV_NAME "riscv-pmu"
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#define RISCV_PMU_STOP_FLAG_RESET 1
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struct cpu_hw_events {
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/* currently enabled events */
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int n_events;
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/* currently enabled events */
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struct perf_event *events[RISCV_MAX_COUNTERS];
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/* currently enabled counters */
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DECLARE_BITMAP(used_event_ctrs, RISCV_MAX_COUNTERS);
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};
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struct riscv_pmu {
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struct pmu pmu;
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char *name;
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irqreturn_t (*handle_irq)(int irq_num, void *dev);
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int num_counters;
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u64 (*ctr_read)(struct perf_event *event);
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int (*ctr_get_idx)(struct perf_event *event);
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int (*ctr_get_width)(int idx);
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void (*ctr_clear_idx)(struct perf_event *event);
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void (*ctr_start)(struct perf_event *event, u64 init_val);
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void (*ctr_stop)(struct perf_event *event, unsigned long flag);
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int (*event_map)(struct perf_event *event, u64 *config);
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struct cpu_hw_events __percpu *hw_events;
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struct hlist_node node;
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};
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#define to_riscv_pmu(p) (container_of(p, struct riscv_pmu, pmu))
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unsigned long riscv_pmu_ctr_read_csr(unsigned long csr);
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int riscv_pmu_event_set_period(struct perf_event *event);
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uint64_t riscv_pmu_ctr_get_width_mask(struct perf_event *event);
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u64 riscv_pmu_event_update(struct perf_event *event);
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struct riscv_pmu *riscv_pmu_alloc(void);
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#endif /* CONFIG_RISCV_PMU */
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#endif /* _ASM_RISCV_PERF_EVENT_H */
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