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a few more cleanups/fixes

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Merge tag 'mips_6.3_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

Pull more MIPS updates from Thomas Bogendoerfer:
 "A few more cleanups and fixes"

* tag 'mips_6.3_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux:
  MIPS: Workaround clang inline compat branch issue
  mips: dts: ralink: mt7621: add phandle to system controller node for watchdog
  mips: dts: ralink: mt7621: rename watchdog node from 'wdt' into 'watchdog'
  mips: ralink: make SOC_MT7621 select PINCTRL
  mips: remove SYS_HAS_CPU_MIPS32_R1 from RALINK
  MIPS: cevt-r4k: Offset the value used to clear compare interrupt
  MIPS: smp-cps: Don't rely on CP0_CMGCRBASE
  MIPS: Remove DMA_PERDEV_COHERENT
This commit is contained in:
Linus Torvalds 2023-03-02 10:34:14 -08:00
commit 04a357b1f6
8 changed files with 31 additions and 31 deletions
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10
arch/mips/Kconfig
View File

@ -610,7 +610,6 @@ config RALINK
select DMA_NONCOHERENT
select IRQ_MIPS_CPU
select USE_OF
select SYS_HAS_CPU_MIPS32_R1
select SYS_HAS_CPU_MIPS32_R2
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_LITTLE_ENDIAN
@ -1080,11 +1079,6 @@ config FW_CFE
config ARCH_SUPPORTS_UPROBES
bool
config DMA_PERDEV_COHERENT
bool
select ARCH_HAS_SETUP_DMA_OPS
select DMA_NONCOHERENT
config DMA_NONCOHERENT
bool
#
@ -3206,6 +3200,10 @@ config CC_HAS_MNO_BRANCH_LIKELY
def_bool y
depends on $(cc-option,-mno-branch-likely)
# https://github.com/llvm/llvm-project/issues/61045
config CC_HAS_BROKEN_INLINE_COMPAT_BRANCH
def_bool y if CC_IS_CLANG
menu "Power management options"
config ARCH_HIBERNATION_POSSIBLE

3
arch/mips/boot/dts/ralink/mt7621.dtsi
View File

@ -70,9 +70,10 @@
"250m", "270m";
};
wdt: wdt@100 {
wdt: watchdog@100 {
compatible = "mediatek,mt7621-wdt";
reg = <0x100 0x100>;
mediatek,sysctl = <&sysc>;
};
gpio: gpio@600 {

2
arch/mips/include/asm/asm.h
View File

@ -336,7 +336,7 @@ symbol = value
*/
#ifdef CONFIG_WAR_R10000_LLSC
# define SC_BEQZ beqzl
#elif MIPS_ISA_REV >= 6
#elif !defined(CONFIG_CC_HAS_BROKEN_INLINE_COMPAT_BRANCH) && MIPS_ISA_REV >= 6
# define SC_BEQZ beqzc
#else
# define SC_BEQZ beqz

4
arch/mips/include/asm/smp-cps.h
View File

@ -7,6 +7,8 @@
#ifndef __MIPS_ASM_SMP_CPS_H__
#define __MIPS_ASM_SMP_CPS_H__
#define CPS_ENTRY_PATCH_INSNS 6
#ifndef __ASSEMBLY__
struct vpe_boot_config {
@ -30,6 +32,8 @@ extern void mips_cps_boot_vpes(struct core_boot_config *cfg, unsigned vpe);
extern void mips_cps_pm_save(void);
extern void mips_cps_pm_restore(void);
extern void *mips_cps_core_entry_patch_end;
#ifdef CONFIG_MIPS_CPS
extern bool mips_cps_smp_in_use(void);

4
arch/mips/kernel/cevt-r4k.c
View File

@ -200,7 +200,7 @@ int c0_compare_int_usable(void)
*/
if (c0_compare_int_pending()) {
cnt = read_c0_count();
write_c0_compare(cnt);
write_c0_compare(cnt - 1);
back_to_back_c0_hazard();
while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS))
if (!c0_compare_int_pending())
@ -228,7 +228,7 @@ int c0_compare_int_usable(void)
if (!c0_compare_int_pending())
return 0;
cnt = read_c0_count();
write_c0_compare(cnt);
write_c0_compare(cnt - 1);
back_to_back_c0_hazard();
while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS))
if (!c0_compare_int_pending())

35
arch/mips/kernel/cps-vec.S
View File

@ -13,6 +13,7 @@
#include <asm/mipsregs.h>
#include <asm/mipsmtregs.h>
#include <asm/pm.h>
#include <asm/smp-cps.h>
#define GCR_CPC_BASE_OFS 0x0088
#define GCR_CL_COHERENCE_OFS 0x2008
@ -80,25 +81,20 @@
nop
.endm
/* Calculate an uncached address for the CM GCRs */
.macro cmgcrb dest
.set push
.set noat
MFC0 $1, CP0_CMGCRBASE
PTR_SLL $1, $1, 4
PTR_LI \dest, UNCAC_BASE
PTR_ADDU \dest, \dest, $1
.set pop
.endm
.balign 0x1000
LEAF(mips_cps_core_entry)
/*
* These first 4 bytes will be patched by cps_smp_setup to load the
* CCA to use into register s0.
* These first several instructions will be patched by cps_smp_setup to load the
* CCA to use into register s0 and GCR base address to register s1.
*/
.word 0
.rept CPS_ENTRY_PATCH_INSNS
nop
.endr
.global mips_cps_core_entry_patch_end
mips_cps_core_entry_patch_end:
/* Check whether we're here due to an NMI */
mfc0 k0, CP0_STATUS
@ -121,8 +117,7 @@ not_nmi:
mtc0 t0, CP0_STATUS
/* Skip cache & coherence setup if we're already coherent */
cmgcrb v1
lw s7, GCR_CL_COHERENCE_OFS(v1)
lw s7, GCR_CL_COHERENCE_OFS(s1)
bnez s7, 1f
nop
@ -132,7 +127,7 @@ not_nmi:
/* Enter the coherent domain */
li t0, 0xff
sw t0, GCR_CL_COHERENCE_OFS(v1)
sw t0, GCR_CL_COHERENCE_OFS(s1)
ehb
/* Set Kseg0 CCA to that in s0 */
@ -305,8 +300,7 @@ LEAF(mips_cps_core_init)
*/
LEAF(mips_cps_get_bootcfg)
/* Calculate a pointer to this cores struct core_boot_config */
cmgcrb t0
lw t0, GCR_CL_ID_OFS(t0)
lw t0, GCR_CL_ID_OFS(s1)
li t1, COREBOOTCFG_SIZE
mul t0, t0, t1
PTR_LA t1, mips_cps_core_bootcfg
@ -366,8 +360,9 @@ LEAF(mips_cps_boot_vpes)
has_vp t0, 5f
/* Find base address of CPC */
cmgcrb t3
PTR_L t1, GCR_CPC_BASE_OFS(t3)
PTR_LA t1, mips_gcr_base
PTR_L t1, 0(t1)
PTR_L t1, GCR_CPC_BASE_OFS(t1)
PTR_LI t2, ~0x7fff
and t1, t1, t2
PTR_LI t2, UNCAC_BASE

2
arch/mips/kernel/smp-cps.c
View File

@ -162,6 +162,8 @@ static void __init cps_prepare_cpus(unsigned int max_cpus)
*/
entry_code = (u32 *)&mips_cps_core_entry;
uasm_i_addiu(&entry_code, 16, 0, cca);
UASM_i_LA(&entry_code, 17, (long)mips_gcr_base);
BUG_ON((void *)entry_code > (void *)&mips_cps_core_entry_patch_end);
blast_dcache_range((unsigned long)&mips_cps_core_entry,
(unsigned long)entry_code);
bc_wback_inv((unsigned long)&mips_cps_core_entry,

2
arch/mips/ralink/Kconfig
View File

@ -54,7 +54,7 @@ choice
select HAVE_PCI
select PCI_DRIVERS_GENERIC
select SOC_BUS
select PINCTRL_MT7621
select PINCTRL
help
The MT7621 system-on-a-chip includes an 880 MHz MIPS1004Kc