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s390/pci: Convert to use flag output macros
Use flag output macros in inline asm to allow for better code generation if the compiler has support for the flag output constraint. Reviewed-by: Niklas Schnelle <schnelle@linux.ibm.com> Tested-by: Niklas Schnelle <schnelle@linux.ibm.com> Reviewed-by: Juergen Christ <jchrist@linux.ibm.com> Signed-off-by: Heiko Carstens <hca@linux.ibm.com>
This commit is contained in:
Heiko Carstens
parent
4e20996f0d
commit
0eb597bd81
@ -20,6 +20,7 @@
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#include <asm/asm-extable.h>
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#include <asm/pci_debug.h>
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#include <asm/pci_clp.h>
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#include <asm/asm.h>
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#include <asm/clp.h>
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#include <uapi/asm/clp.h>
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@ -52,18 +53,20 @@ static inline void zpci_err_clp(unsigned int rsp, int rc)
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static inline int clp_get_ilp(unsigned long *ilp)
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{
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unsigned long mask;
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int cc = 3;
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int cc, exception;
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exception = 1;
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asm volatile (
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" .insn rrf,0xb9a00000,%[mask],%[cmd],8,0\n"
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"0: ipm %[cc]\n"
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" srl %[cc],28\n"
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"0: lhi %[exc],0\n"
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"1:\n"
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CC_IPM(cc)
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EX_TABLE(0b, 1b)
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: [cc] "+d" (cc), [mask] "=d" (mask) : [cmd] "a" (1)
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: "cc");
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: CC_OUT(cc, cc), [mask] "=d" (mask), [exc] "+d" (exception)
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: [cmd] "a" (1)
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: CC_CLOBBER);
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*ilp = mask;
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return cc;
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return exception ? 3 : CC_TRANSFORM(cc);
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}
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/*
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@ -72,19 +75,20 @@ static inline int clp_get_ilp(unsigned long *ilp)
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static __always_inline int clp_req(void *data, unsigned int lps)
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{
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struct { u8 _[CLP_BLK_SIZE]; } *req = data;
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int cc, exception;
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u64 ignored;
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int cc = 3;
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exception = 1;
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asm volatile (
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" .insn rrf,0xb9a00000,%[ign],%[req],0,%[lps]\n"
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"0: ipm %[cc]\n"
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" srl %[cc],28\n"
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"0: lhi %[exc],0\n"
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"1:\n"
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CC_IPM(cc)
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EX_TABLE(0b, 1b)
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: [cc] "+d" (cc), [ign] "=d" (ignored), "+m" (*req)
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: CC_OUT(cc, cc), [ign] "=d" (ignored), "+m" (*req), [exc] "+d" (exception)
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: [req] "a" (req), [lps] "i" (lps)
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: "cc");
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return cc;
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: CC_CLOBBER);
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return exception ? 3 : CC_TRANSFORM(cc);
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}
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static void *clp_alloc_block(gfp_t gfp_mask)
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@ -15,6 +15,7 @@
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#include <asm/pci_debug.h>
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#include <asm/pci_io.h>
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#include <asm/processor.h>
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#include <asm/asm.h>
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#define ZPCI_INSN_BUSY_DELAY 1 /* 1 microsecond */
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@ -57,16 +58,16 @@ static inline void zpci_err_insn_addr(int lvl, u8 insn, u8 cc, u8 status,
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/* Modify PCI Function Controls */
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static inline u8 __mpcifc(u64 req, struct zpci_fib *fib, u8 *status)
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{
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u8 cc;
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int cc;
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asm volatile (
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" .insn rxy,0xe300000000d0,%[req],%[fib]\n"
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" ipm %[cc]\n"
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" srl %[cc],28\n"
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: [cc] "=d" (cc), [req] "+d" (req), [fib] "+Q" (*fib)
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: : "cc");
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CC_IPM(cc)
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: CC_OUT(cc, cc), [req] "+d" (req), [fib] "+Q" (*fib)
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:
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: CC_CLOBBER);
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*status = req >> 24 & 0xff;
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return cc;
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return CC_TRANSFORM(cc);
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}
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u8 zpci_mod_fc(u64 req, struct zpci_fib *fib, u8 *status)
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@ -98,17 +99,16 @@ EXPORT_SYMBOL_GPL(zpci_mod_fc);
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static inline u8 __rpcit(u64 fn, u64 addr, u64 range, u8 *status)
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{
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union register_pair addr_range = {.even = addr, .odd = range};
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u8 cc;
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int cc;
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asm volatile (
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" .insn rre,0xb9d30000,%[fn],%[addr_range]\n"
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" ipm %[cc]\n"
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" srl %[cc],28\n"
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: [cc] "=d" (cc), [fn] "+d" (fn)
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CC_IPM(cc)
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: CC_OUT(cc, cc), [fn] "+d" (fn)
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: [addr_range] "d" (addr_range.pair)
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: "cc");
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: CC_CLOBBER);
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*status = fn >> 24 & 0xff;
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return cc;
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return CC_TRANSFORM(cc);
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}
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int zpci_refresh_trans(u64 fn, u64 addr, u64 range)
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@ -156,20 +156,23 @@ EXPORT_SYMBOL_GPL(zpci_set_irq_ctrl);
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static inline int ____pcilg(u64 *data, u64 req, u64 offset, u8 *status)
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{
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union register_pair req_off = {.even = req, .odd = offset};
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int cc = -ENXIO;
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int cc, exception;
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u64 __data;
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exception = 1;
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asm volatile (
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" .insn rre,0xb9d20000,%[data],%[req_off]\n"
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"0: ipm %[cc]\n"
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" srl %[cc],28\n"
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"0: lhi %[exc],0\n"
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"1:\n"
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CC_IPM(cc)
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EX_TABLE(0b, 1b)
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: [cc] "+d" (cc), [data] "=d" (__data),
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[req_off] "+&d" (req_off.pair) :: "cc");
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: CC_OUT(cc, cc), [data] "=d" (__data),
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[req_off] "+d" (req_off.pair), [exc] "+d" (exception)
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:
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: CC_CLOBBER);
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*status = req_off.even >> 24 & 0xff;
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*data = __data;
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return cc;
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return exception ? -ENXIO : CC_TRANSFORM(cc);
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}
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static inline int __pcilg(u64 *data, u64 req, u64 offset, u8 *status)
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@ -222,20 +225,23 @@ static inline int zpci_load_fh(u64 *data, const volatile void __iomem *addr,
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static inline int __pcilg_mio(u64 *data, u64 ioaddr, u64 len, u8 *status)
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{
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union register_pair ioaddr_len = {.even = ioaddr, .odd = len};
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int cc = -ENXIO;
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int cc, exception;
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u64 __data;
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exception = 1;
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asm volatile (
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" .insn rre,0xb9d60000,%[data],%[ioaddr_len]\n"
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"0: ipm %[cc]\n"
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" srl %[cc],28\n"
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"0: lhi %[exc],0\n"
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"1:\n"
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CC_IPM(cc)
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EX_TABLE(0b, 1b)
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: [cc] "+d" (cc), [data] "=d" (__data),
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[ioaddr_len] "+&d" (ioaddr_len.pair) :: "cc");
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: CC_OUT(cc, cc), [data] "=d" (__data),
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[ioaddr_len] "+d" (ioaddr_len.pair), [exc] "+d" (exception)
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:
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: CC_CLOBBER);
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*status = ioaddr_len.odd >> 24 & 0xff;
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*data = __data;
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return cc;
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return exception ? -ENXIO : CC_TRANSFORM(cc);
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}
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int zpci_load(u64 *data, const volatile void __iomem *addr, unsigned long len)
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@ -258,19 +264,20 @@ EXPORT_SYMBOL_GPL(zpci_load);
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static inline int __pcistg(u64 data, u64 req, u64 offset, u8 *status)
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{
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union register_pair req_off = {.even = req, .odd = offset};
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int cc = -ENXIO;
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int cc, exception;
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exception = 1;
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asm volatile (
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" .insn rre,0xb9d00000,%[data],%[req_off]\n"
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"0: ipm %[cc]\n"
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" srl %[cc],28\n"
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"0: lhi %[exc],0\n"
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"1:\n"
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CC_IPM(cc)
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EX_TABLE(0b, 1b)
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: [cc] "+d" (cc), [req_off] "+&d" (req_off.pair)
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: CC_OUT(cc, cc), [req_off] "+d" (req_off.pair), [exc] "+d" (exception)
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: [data] "d" (data)
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: "cc");
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: CC_CLOBBER);
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*status = req_off.even >> 24 & 0xff;
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return cc;
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return exception ? -ENXIO : CC_TRANSFORM(cc);
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}
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int __zpci_store(u64 data, u64 req, u64 offset)
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@ -311,19 +318,20 @@ static inline int zpci_store_fh(const volatile void __iomem *addr, u64 data,
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static inline int __pcistg_mio(u64 data, u64 ioaddr, u64 len, u8 *status)
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{
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union register_pair ioaddr_len = {.even = ioaddr, .odd = len};
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int cc = -ENXIO;
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int cc, exception;
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exception = 1;
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asm volatile (
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" .insn rre,0xb9d40000,%[data],%[ioaddr_len]\n"
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"0: ipm %[cc]\n"
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" srl %[cc],28\n"
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"0: lhi %[exc],0\n"
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"1:\n"
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CC_IPM(cc)
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EX_TABLE(0b, 1b)
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: [cc] "+d" (cc), [ioaddr_len] "+&d" (ioaddr_len.pair)
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: CC_OUT(cc, cc), [ioaddr_len] "+d" (ioaddr_len.pair), [exc] "+d" (exception)
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: [data] "d" (data)
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: "cc", "memory");
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: CC_CLOBBER_LIST("memory"));
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*status = ioaddr_len.odd >> 24 & 0xff;
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return cc;
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return exception ? -ENXIO : CC_TRANSFORM(cc);
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}
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int zpci_store(const volatile void __iomem *addr, u64 data, unsigned long len)
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@ -345,19 +353,20 @@ EXPORT_SYMBOL_GPL(zpci_store);
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/* PCI Store Block */
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static inline int __pcistb(const u64 *data, u64 req, u64 offset, u8 *status)
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{
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int cc = -ENXIO;
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int cc, exception;
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exception = 1;
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asm volatile (
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" .insn rsy,0xeb00000000d0,%[req],%[offset],%[data]\n"
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"0: ipm %[cc]\n"
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" srl %[cc],28\n"
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"0: lhi %[exc],0\n"
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"1:\n"
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CC_IPM(cc)
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EX_TABLE(0b, 1b)
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: [cc] "+d" (cc), [req] "+d" (req)
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: CC_OUT(cc, cc), [req] "+d" (req), [exc] "+d" (exception)
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: [offset] "d" (offset), [data] "Q" (*data)
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: "cc");
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: CC_CLOBBER);
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*status = req >> 24 & 0xff;
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return cc;
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return exception ? -ENXIO : CC_TRANSFORM(cc);
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}
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int __zpci_store_block(const u64 *data, u64 req, u64 offset)
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@ -398,19 +407,20 @@ static inline int zpci_write_block_fh(volatile void __iomem *dst,
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static inline int __pcistb_mio(const u64 *data, u64 ioaddr, u64 len, u8 *status)
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{
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int cc = -ENXIO;
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int cc, exception;
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exception = 1;
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asm volatile (
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" .insn rsy,0xeb00000000d4,%[len],%[ioaddr],%[data]\n"
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"0: ipm %[cc]\n"
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" srl %[cc],28\n"
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"0: lhi %[exc],0\n"
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"1:\n"
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CC_IPM(cc)
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EX_TABLE(0b, 1b)
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: [cc] "+d" (cc), [len] "+d" (len)
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: CC_OUT(cc, cc), [len] "+d" (len), [exc] "+d" (exception)
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: [ioaddr] "d" (ioaddr), [data] "Q" (*data)
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: "cc");
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: CC_CLOBBER);
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*status = len >> 24 & 0xff;
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return cc;
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return exception ? -ENXIO : CC_TRANSFORM(cc);
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}
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int zpci_write_block(volatile void __iomem *dst,
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@ -14,6 +14,7 @@
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#include <asm/asm-extable.h>
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#include <asm/pci_io.h>
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#include <asm/pci_debug.h>
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#include <asm/asm.h>
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static inline void zpci_err_mmio(u8 cc, u8 status, u64 offset)
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{
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@ -30,20 +31,21 @@ static inline int __pcistb_mio_inuser(
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void __iomem *ioaddr, const void __user *src,
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u64 len, u8 *status)
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{
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int cc = -ENXIO;
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int cc, exception;
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exception = 1;
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asm volatile (
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" sacf 256\n"
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"0: .insn rsy,0xeb00000000d4,%[len],%[ioaddr],%[src]\n"
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"1: ipm %[cc]\n"
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" srl %[cc],28\n"
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"2: sacf 768\n"
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" sacf 256\n"
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"0: .insn rsy,0xeb00000000d4,%[len],%[ioaddr],%[src]\n"
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"1: lhi %[exc],0\n"
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"2: sacf 768\n"
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CC_IPM(cc)
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EX_TABLE(0b, 2b) EX_TABLE(1b, 2b)
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: [cc] "+d" (cc), [len] "+d" (len)
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: CC_OUT(cc, cc), [len] "+d" (len), [exc] "+d" (exception)
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: [ioaddr] "a" (ioaddr), [src] "Q" (*((u8 __force *)src))
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: "cc", "memory");
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: CC_CLOBBER_LIST("memory"));
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*status = len >> 24 & 0xff;
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return cc;
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return exception ? -ENXIO : CC_TRANSFORM(cc);
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}
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static inline int __pcistg_mio_inuser(
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@ -51,7 +53,7 @@ static inline int __pcistg_mio_inuser(
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u64 ulen, u8 *status)
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{
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union register_pair ioaddr_len = {.even = (u64 __force)ioaddr, .odd = ulen};
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int cc = -ENXIO;
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int cc, exception;
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u64 val = 0;
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u64 cnt = ulen;
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u8 tmp;
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@ -61,25 +63,27 @@ static inline int __pcistg_mio_inuser(
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* a register, then store it to PCI at @ioaddr while in secondary
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* address space. pcistg then uses the user mappings.
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*/
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exception = 1;
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asm volatile (
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" sacf 256\n"
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"0: llgc %[tmp],0(%[src])\n"
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" sacf 256\n"
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"0: llgc %[tmp],0(%[src])\n"
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"4: sllg %[val],%[val],8\n"
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" aghi %[src],1\n"
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" ogr %[val],%[tmp]\n"
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" brctg %[cnt],0b\n"
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"1: .insn rre,0xb9d40000,%[val],%[ioaddr_len]\n"
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"2: ipm %[cc]\n"
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" srl %[cc],28\n"
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"3: sacf 768\n"
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" aghi %[src],1\n"
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" ogr %[val],%[tmp]\n"
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" brctg %[cnt],0b\n"
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"1: .insn rre,0xb9d40000,%[val],%[ioaddr_len]\n"
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"2: lhi %[exc],0\n"
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"3: sacf 768\n"
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CC_IPM(cc)
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EX_TABLE(0b, 3b) EX_TABLE(4b, 3b) EX_TABLE(1b, 3b) EX_TABLE(2b, 3b)
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: [src] "+a" (src), [cnt] "+d" (cnt),
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[val] "+d" (val), [tmp] "=d" (tmp), [exc] "+d" (exception),
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CC_OUT(cc, cc), [ioaddr_len] "+&d" (ioaddr_len.pair)
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:
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[src] "+a" (src), [cnt] "+d" (cnt),
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[val] "+d" (val), [tmp] "=d" (tmp),
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[cc] "+d" (cc), [ioaddr_len] "+&d" (ioaddr_len.pair)
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:: "cc", "memory");
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: CC_CLOBBER_LIST("memory"));
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*status = ioaddr_len.odd >> 24 & 0xff;
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cc = exception ? -ENXIO : CC_TRANSFORM(cc);
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/* did we read everything from user memory? */
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if (!cc && cnt != 0)
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cc = -EFAULT;
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@ -198,7 +202,7 @@ static inline int __pcilg_mio_inuser(
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union register_pair ioaddr_len = {.even = (u64 __force)ioaddr, .odd = ulen};
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u64 cnt = ulen;
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int shift = ulen * 8;
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int cc = -ENXIO;
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int cc, exception;
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u64 val, tmp;
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/*
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@ -206,27 +210,33 @@ static inline int __pcilg_mio_inuser(
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* user space) into a register using pcilg then store these bytes at
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* user address @dst
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*/
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exception = 1;
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asm volatile (
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" sacf 256\n"
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"0: .insn rre,0xb9d60000,%[val],%[ioaddr_len]\n"
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"1: ipm %[cc]\n"
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" srl %[cc],28\n"
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" ltr %[cc],%[cc]\n"
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" jne 4f\n"
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"2: ahi %[shift],-8\n"
|
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" srlg %[tmp],%[val],0(%[shift])\n"
|
||||
"3: stc %[tmp],0(%[dst])\n"
|
||||
" sacf 256\n"
|
||||
"0: .insn rre,0xb9d60000,%[val],%[ioaddr_len]\n"
|
||||
"1: lhi %[exc],0\n"
|
||||
" jne 4f\n"
|
||||
"2: ahi %[shift],-8\n"
|
||||
" srlg %[tmp],%[val],0(%[shift])\n"
|
||||
"3: stc %[tmp],0(%[dst])\n"
|
||||
"5: aghi %[dst],1\n"
|
||||
" brctg %[cnt],2b\n"
|
||||
"4: sacf 768\n"
|
||||
" brctg %[cnt],2b\n"
|
||||
/*
|
||||
* Use xr to clear exc and set condition code to zero
|
||||
* to ensure flag output is correct for this branch.
|
||||
*/
|
||||
" xr %[exc],%[exc]\n"
|
||||
"4: sacf 768\n"
|
||||
CC_IPM(cc)
|
||||
EX_TABLE(0b, 4b) EX_TABLE(1b, 4b) EX_TABLE(3b, 4b) EX_TABLE(5b, 4b)
|
||||
: [ioaddr_len] "+&d" (ioaddr_len.pair), [exc] "+d" (exception),
|
||||
CC_OUT(cc, cc), [val] "=d" (val),
|
||||
[dst] "+a" (dst), [cnt] "+d" (cnt), [tmp] "=d" (tmp),
|
||||
[shift] "+d" (shift)
|
||||
:
|
||||
[ioaddr_len] "+&d" (ioaddr_len.pair),
|
||||
[cc] "+d" (cc), [val] "=d" (val),
|
||||
[dst] "+a" (dst), [cnt] "+d" (cnt), [tmp] "=d" (tmp),
|
||||
[shift] "+d" (shift)
|
||||
:: "cc", "memory");
|
||||
: CC_CLOBBER_LIST("memory"));
|
||||
|
||||
cc = exception ? -ENXIO : CC_TRANSFORM(cc);
|
||||
/* did we write everything to the user space buffer? */
|
||||
if (!cc && cnt != 0)
|
||||
cc = -EFAULT;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user