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rsxx: Moving pci_map_page to prevent overflow.
The pci_map_page function has been moved into our issued workqueue to prevent an us running out of mappable addresses on non-HWWD PCIe x8 slots. The maximum amount that can possible be mapped at one time now is: 255 dmas X 4 dma channels X 4096 Bytes. Signed-off-by: Philip J Kelleher <pjk1939@linux.vnet.ibm.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
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@ -749,10 +749,6 @@ static pci_ers_result_t rsxx_slot_reset(struct pci_dev *dev)
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card->eeh_state = 0;
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st = rsxx_eeh_remap_dmas(card);
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if (st)
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goto failed_remap_dmas;
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spin_lock_irqsave(&card->irq_lock, flags);
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if (card->n_targets & RSXX_MAX_TARGETS)
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rsxx_enable_ier_and_isr(card, CR_INTR_ALL_G);
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@ -779,7 +775,6 @@ static pci_ers_result_t rsxx_slot_reset(struct pci_dev *dev)
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return PCI_ERS_RESULT_RECOVERED;
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failed_hw_buffers_init:
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failed_remap_dmas:
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for (i = 0; i < card->n_targets; i++) {
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if (card->ctrl[i].status.buf)
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pci_free_consistent(card->dev,
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@ -397,6 +397,7 @@ static void rsxx_issue_dmas(struct rsxx_dma_ctrl *ctrl)
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int tag;
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int cmds_pending = 0;
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struct hw_cmd *hw_cmd_buf;
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int dir;
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hw_cmd_buf = ctrl->cmd.buf;
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@ -433,6 +434,28 @@ static void rsxx_issue_dmas(struct rsxx_dma_ctrl *ctrl)
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continue;
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}
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if (dma->cmd == HW_CMD_BLK_WRITE)
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dir = PCI_DMA_TODEVICE;
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else
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dir = PCI_DMA_FROMDEVICE;
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/*
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* The function pci_map_page is placed here because we can
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* only, by design, issue up to 255 commands to the hardware
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* at one time per DMA channel. So the maximum amount of mapped
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* memory would be 255 * 4 channels * 4096 Bytes which is less
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* than 2GB, the limit of a x8 Non-HWWD PCIe slot. This way the
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* pci_map_page function should never fail because of a
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* lack of mappable memory.
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*/
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dma->dma_addr = pci_map_page(ctrl->card->dev, dma->page,
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dma->pg_off, dma->sub_page.cnt << 9, dir);
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if (pci_dma_mapping_error(ctrl->card->dev, dma->dma_addr)) {
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push_tracker(ctrl->trackers, tag);
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rsxx_complete_dma(ctrl, dma, DMA_CANCELLED);
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continue;
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}
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set_tracker_dma(ctrl->trackers, tag, dma);
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hw_cmd_buf[ctrl->cmd.idx].command = dma->cmd;
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hw_cmd_buf[ctrl->cmd.idx].tag = tag;
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@ -629,14 +652,6 @@ static int rsxx_queue_dma(struct rsxx_cardinfo *card,
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if (!dma)
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return -ENOMEM;
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dma->dma_addr = pci_map_page(card->dev, page, pg_off, dma_len,
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dir ? PCI_DMA_TODEVICE :
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PCI_DMA_FROMDEVICE);
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if (pci_dma_mapping_error(card->dev, dma->dma_addr)) {
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kmem_cache_free(rsxx_dma_pool, dma);
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return -ENOMEM;
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}
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dma->cmd = dir ? HW_CMD_BLK_WRITE : HW_CMD_BLK_READ;
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dma->laddr = laddr;
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dma->sub_page.off = (dma_off >> 9);
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@ -1039,6 +1054,11 @@ int rsxx_eeh_save_issued_dmas(struct rsxx_cardinfo *card)
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else
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card->ctrl[i].stats.reads_issued--;
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pci_unmap_page(card->dev, dma->dma_addr,
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get_dma_size(dma),
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dma->cmd == HW_CMD_BLK_WRITE ?
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PCI_DMA_TODEVICE :
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PCI_DMA_FROMDEVICE);
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list_add_tail(&dma->list, &issued_dmas[i]);
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push_tracker(card->ctrl[i].trackers, j);
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cnt++;
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@ -1050,15 +1070,6 @@ int rsxx_eeh_save_issued_dmas(struct rsxx_cardinfo *card)
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atomic_sub(cnt, &card->ctrl[i].stats.hw_q_depth);
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card->ctrl[i].stats.sw_q_depth += cnt;
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card->ctrl[i].e_cnt = 0;
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list_for_each_entry(dma, &card->ctrl[i].queue, list) {
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if (!pci_dma_mapping_error(card->dev, dma->dma_addr))
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pci_unmap_page(card->dev, dma->dma_addr,
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get_dma_size(dma),
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dma->cmd == HW_CMD_BLK_WRITE ?
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PCI_DMA_TODEVICE :
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PCI_DMA_FROMDEVICE);
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}
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spin_unlock_bh(&card->ctrl[i].queue_lock);
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}
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@ -1067,31 +1078,6 @@ int rsxx_eeh_save_issued_dmas(struct rsxx_cardinfo *card)
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return 0;
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}
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int rsxx_eeh_remap_dmas(struct rsxx_cardinfo *card)
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{
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struct rsxx_dma *dma;
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int i;
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for (i = 0; i < card->n_targets; i++) {
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spin_lock_bh(&card->ctrl[i].queue_lock);
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list_for_each_entry(dma, &card->ctrl[i].queue, list) {
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dma->dma_addr = pci_map_page(card->dev, dma->page,
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dma->pg_off, get_dma_size(dma),
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dma->cmd == HW_CMD_BLK_WRITE ?
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PCI_DMA_TODEVICE :
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PCI_DMA_FROMDEVICE);
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if (pci_dma_mapping_error(card->dev, dma->dma_addr)) {
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spin_unlock_bh(&card->ctrl[i].queue_lock);
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kmem_cache_free(rsxx_dma_pool, dma);
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return -ENOMEM;
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}
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}
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spin_unlock_bh(&card->ctrl[i].queue_lock);
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}
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return 0;
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}
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int rsxx_dma_init(void)
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{
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rsxx_dma_pool = KMEM_CACHE(rsxx_dma, SLAB_HWCACHE_ALIGN);
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