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spi: spi-cadence-qspi: Disable STIG mode for Altera SoCFPGA.
STIG mode is enabled by default for less than 8 bytes data read/write. STIG mode doesn't work with Altera SocFPGA platform due hardware limitation. Add a quirks to disable STIG mode for Altera SoCFPGA platform. Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com> Link: https://patch.msgid.link/20241204063338.296959-1-niravkumar.l.rabara@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -43,6 +43,7 @@ static_assert(CQSPI_MAX_CHIPSELECT <= SPI_CS_CNT_MAX);
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#define CQSPI_SLOW_SRAM BIT(4)
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#define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5)
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#define CQSPI_RD_NO_IRQ BIT(6)
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#define CQSPI_DISABLE_STIG_MODE BIT(7)
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/* Capabilities */
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#define CQSPI_SUPPORTS_OCTAL BIT(0)
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@ -103,6 +104,7 @@ struct cqspi_st {
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bool apb_ahb_hazard;
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bool is_jh7110; /* Flag for StarFive JH7110 SoC */
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bool disable_stig_mode;
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const struct cqspi_driver_platdata *ddata;
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};
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@ -1416,7 +1418,8 @@ static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op)
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* reads, prefer STIG mode for such small reads.
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*/
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if (!op->addr.nbytes ||
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op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX)
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(op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX &&
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!cqspi->disable_stig_mode))
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return cqspi_command_read(f_pdata, op);
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return cqspi_read(f_pdata, op);
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@ -1880,6 +1883,8 @@ static int cqspi_probe(struct platform_device *pdev)
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if (ret)
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goto probe_reset_failed;
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}
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if (ddata->quirks & CQSPI_DISABLE_STIG_MODE)
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cqspi->disable_stig_mode = true;
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if (of_device_is_compatible(pdev->dev.of_node,
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"xlnx,versal-ospi-1.0")) {
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@ -2043,7 +2048,8 @@ static const struct cqspi_driver_platdata intel_lgm_qspi = {
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static const struct cqspi_driver_platdata socfpga_qspi = {
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.quirks = CQSPI_DISABLE_DAC_MODE
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| CQSPI_NO_SUPPORT_WR_COMPLETION
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| CQSPI_SLOW_SRAM,
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| CQSPI_SLOW_SRAM
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| CQSPI_DISABLE_STIG_MODE,
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};
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static const struct cqspi_driver_platdata versal_ospi = {
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