mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
synced 2024-12-29 01:02:08 +00:00
Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git
This commit is contained in:
Stephen Rothwell
commit
311e20a8a3
40
Documentation/devicetree/bindings/arm/blaize.yaml
Normal file
40
Documentation/devicetree/bindings/arm/blaize.yaml
Normal file
@ -0,0 +1,40 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/blaize.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Blaize Platforms
|
||||
|
||||
maintainers:
|
||||
- James Cowgill <james.cowgill@blaize.com>
|
||||
- Matt Redfearn <matt.redfearn@blaize.com>
|
||||
- Neil Jones <neil.jones@blaize.com>
|
||||
- Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
|
||||
|
||||
description: |
|
||||
Blaize Platforms using SoCs designed by Blaize Inc.
|
||||
|
||||
The products based on the BLZP1600 SoC:
|
||||
|
||||
- BLZP1600-SoM: SoM (System on Module)
|
||||
- BLZP1600-CB2: Development board CB2 based on BLZP1600-SoM
|
||||
|
||||
BLZP1600 SoC integrates a dual core ARM Cortex A53 cluster
|
||||
and a Blaize Graph Streaming Processor for AI and ML workloads,
|
||||
plus a suite of connectivity and other peripherals.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: Blaize BLZP1600 based boards
|
||||
items:
|
||||
- enum:
|
||||
- blaize,blzp1600-cb2
|
||||
- const: blaize,blzp1600
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
...
|
||||
@ -218,6 +218,8 @@ patternProperties:
|
||||
description: Shenzhen BigTree Tech Co., LTD
|
||||
"^bitmain,.*":
|
||||
description: Bitmain Technologies
|
||||
"^blaize,.*":
|
||||
description: Blaize, Inc.
|
||||
"^blutek,.*":
|
||||
description: BluTek Power
|
||||
"^boe,.*":
|
||||
|
||||
@ -2283,6 +2283,15 @@ F: arch/arm64/boot/dts/bitmain/
|
||||
F: drivers/clk/clk-bm1880.c
|
||||
F: drivers/pinctrl/pinctrl-bm1880.c
|
||||
|
||||
ARM/BLAIZE ARCHITECTURE
|
||||
M: James Cowgill <james.cowgill@blaize.com>
|
||||
M: Matt Redfearn <matt.redfearn@blaize.com>
|
||||
M: Neil Jones <neil.jones@blaize.com>
|
||||
M: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/arm/blaize.yaml
|
||||
F: arch/arm64/boot/dts/blaize/
|
||||
|
||||
ARM/CALXEDA HIGHBANK ARCHITECTURE
|
||||
M: Andre Przywara <andre.przywara@arm.com>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
|
||||
@ -661,7 +661,7 @@ &i2c5 {
|
||||
clock-frequency = <100000>;
|
||||
status = "okay";
|
||||
|
||||
mb_fru@50 {
|
||||
eeprom@50 {
|
||||
compatible = "atmel,24c64";
|
||||
reg = <0x50>;
|
||||
};
|
||||
@ -704,7 +704,7 @@ max31725@5d {
|
||||
reg = <0x5d>;
|
||||
status = "okay";
|
||||
};
|
||||
fan_fru@51 {
|
||||
eeprom@51 {
|
||||
compatible = "atmel,24c64";
|
||||
reg = <0x51>;
|
||||
};
|
||||
@ -714,7 +714,7 @@ i2c5_hsbp_fru_3: i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
hsbp_fru@52 {
|
||||
eeprom@52 {
|
||||
compatible = "atmel,24c64";
|
||||
reg = <0x52>;
|
||||
status = "okay";
|
||||
|
||||
@ -824,7 +824,7 @@ tmp75@4a {
|
||||
reg = <0x4a>;
|
||||
status = "okay";
|
||||
};
|
||||
m24128_fru@51 {
|
||||
eeprom@51 {
|
||||
compatible = "atmel,24c128";
|
||||
reg = <0x51>;
|
||||
pagesize = <64>;
|
||||
|
||||
@ -101,6 +101,11 @@ config ARCH_BITMAIN
|
||||
help
|
||||
This enables support for the Bitmain SoC Family.
|
||||
|
||||
config ARCH_BLAIZE
|
||||
bool "Blaize SoC Platforms"
|
||||
help
|
||||
This enables support for the Blaize SoC family
|
||||
|
||||
config ARCH_EXYNOS
|
||||
bool "Samsung Exynos SoC family"
|
||||
select COMMON_CLK_SAMSUNG
|
||||
|
||||
@ -10,6 +10,7 @@ subdir-y += apm
|
||||
subdir-y += apple
|
||||
subdir-y += arm
|
||||
subdir-y += bitmain
|
||||
subdir-y += blaize
|
||||
subdir-y += broadcom
|
||||
subdir-y += cavium
|
||||
subdir-y += exynos
|
||||
|
||||
2
arch/arm64/boot/dts/blaize/Makefile
Normal file
2
arch/arm64/boot/dts/blaize/Makefile
Normal file
@ -0,0 +1,2 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
dtb-$(CONFIG_ARCH_BLAIZE) += blaize-blzp1600-cb2.dtb
|
||||
83
arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts
Normal file
83
arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts
Normal file
@ -0,0 +1,83 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (c) 2024 Blaize, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "blaize-blzp1600-som.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Blaize BLZP1600 SoM1600P CB2 Development Board";
|
||||
|
||||
compatible = "blaize,blzp1600-cb2", "blaize,blzp1600";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200";
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
clock-frequency = <100000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <100000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
clock-frequency = <100000>;
|
||||
status = "okay";
|
||||
|
||||
gpio_expander: gpio@74 {
|
||||
compatible = "ti,tca9539";
|
||||
reg = <0x74>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-line-names = "RSP_PIN_7", /* GPIO_0 */
|
||||
"RSP_PIN_11", /* GPIO_1 */
|
||||
"RSP_PIN_13", /* GPIO_2 */
|
||||
"RSP_PIN_15", /* GPIO_3 */
|
||||
"RSP_PIN_27", /* GPIO_4 */
|
||||
"RSP_PIN_29", /* GPIO_5 */
|
||||
"RSP_PIN_31", /* GPIO_6 */
|
||||
"RSP_PIN_33", /* GPIO_7 */
|
||||
"RSP_PIN_37", /* GPIO_8 */
|
||||
"RSP_PIN_16", /* GPIO_9 */
|
||||
"RSP_PIN_18", /* GPIO_10 */
|
||||
"RSP_PIN_22", /* GPIO_11 */
|
||||
"RSP_PIN_28", /* GPIO_12 */
|
||||
"RSP_PIN_32", /* GPIO_13 */
|
||||
"RSP_PIN_36", /* GPIO_14 */
|
||||
"TP31"; /* GPIO_15 */
|
||||
};
|
||||
|
||||
gpio_expander_m2: gpio@75 {
|
||||
compatible = "ti,tca9539";
|
||||
reg = <0x75>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-line-names = "M2_W_DIS1_N", /* GPIO_0 */
|
||||
"M2_W_DIS2_N", /* GPIO_1 */
|
||||
"M2_UART_WAKE_N", /* GPIO_2 */
|
||||
"M2_COEX3", /* GPIO_3 */
|
||||
"M2_COEX_RXD", /* GPIO_4 */
|
||||
"M2_COEX_TXD", /* GPIO_5 */
|
||||
"M2_VENDOR_PIN40", /* GPIO_6 */
|
||||
"M2_VENDOR_PIN42", /* GPIO_7 */
|
||||
"M2_VENDOR_PIN38", /* GPIO_8 */
|
||||
"M2_SDIO_RST_N", /* GPIO_9 */
|
||||
"M2_SDIO_WAKE_N", /* GPIO_10 */
|
||||
"M2_PETN1", /* GPIO_11 */
|
||||
"M2_PERP1", /* GPIO_12 */
|
||||
"M2_PERN1", /* GPIO_13 */
|
||||
"UIM_SWP", /* GPIO_14 */
|
||||
"UART1_TO_RSP"; /* GPIO_15 */
|
||||
};
|
||||
};
|
||||
23
arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi
Normal file
23
arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi
Normal file
@ -0,0 +1,23 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (c) 2024 Blaize, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "blaize-blzp1600.dtsi"
|
||||
|
||||
/ {
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x1 0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
/* i2c4 bus is available only on the SoM, not on the board */
|
||||
&i2c4 {
|
||||
clock-frequency = <100000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
205
arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi
Normal file
205
arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi
Normal file
@ -0,0 +1,205 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (c) 2024 Blaize, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0 0x0>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&l2>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0 0x1>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&l2>;
|
||||
};
|
||||
|
||||
l2: l2-cache0 {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
};
|
||||
};
|
||||
|
||||
firmware {
|
||||
scmi {
|
||||
compatible = "arm,scmi-smc";
|
||||
arm,smc-id = <0x82002000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
shmem = <&scmi0_shm>;
|
||||
|
||||
scmi_clk: protocol@14 {
|
||||
reg = <0x14>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
scmi_rst: protocol@16 {
|
||||
reg = <0x16>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&cpu0>, <&cpu1>;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0", "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
/* SCMI reserved buffer space on DDR space */
|
||||
scmi0_shm: scmi-shmem@800 {
|
||||
compatible = "arm,scmi-shmem";
|
||||
reg = <0x0 0x800 0x0 0x80>;
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = /* Physical Secure PPI */
|
||||
<GIC_PPI 13 (GIC_CPU_MASK_RAW(0x3) |
|
||||
IRQ_TYPE_LEVEL_LOW)>,
|
||||
/* Physical Non-Secure PPI */
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_RAW(0x3) |
|
||||
IRQ_TYPE_LEVEL_LOW)>,
|
||||
/* Hypervisor PPI */
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_RAW(0x3) |
|
||||
IRQ_TYPE_LEVEL_LOW)>,
|
||||
/* Virtual PPI */
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_RAW(0x3) |
|
||||
IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
soc@200000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x2 0x0 0x850000>;
|
||||
|
||||
gic: interrupt-controller@410000 {
|
||||
compatible = "arm,gic-400";
|
||||
reg = <0x410000 0x20000>,
|
||||
<0x420000 0x20000>,
|
||||
<0x440000 0x20000>,
|
||||
<0x460000 0x20000>;
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0x3) |
|
||||
IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
uart0: serial@4d0000 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x4d0000 0x1000>;
|
||||
clocks = <&scmi_clk 59>;
|
||||
resets = <&scmi_rst 59>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@4e0000 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x4e0000 0x1000>;
|
||||
clocks = <&scmi_clk 60>;
|
||||
resets = <&scmi_rst 60>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@4f0000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0x4f0000 0x1000>;
|
||||
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&scmi_clk 54>;
|
||||
resets = <&scmi_rst 54>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@500000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0x500000 0x1000>;
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&scmi_clk 55>;
|
||||
resets = <&scmi_rst 55>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@510000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0x510000 0x1000>;
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&scmi_clk 56>;
|
||||
resets = <&scmi_rst 56>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@520000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0x520000 0x1000>;
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&scmi_clk 57>;
|
||||
resets = <&scmi_rst 57>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@530000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0x530000 0x1000>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&scmi_clk 58>;
|
||||
resets = <&scmi_rst 58>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
arm_cc712: crypto@550000 {
|
||||
compatible = "arm,cryptocell-712-ree";
|
||||
reg = <0x550000 0x1000>;
|
||||
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&scmi_clk 7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -44,6 +44,7 @@ CONFIG_ARCH_BCM_IPROC=y
|
||||
CONFIG_ARCH_BCMBCA=y
|
||||
CONFIG_ARCH_BRCMSTB=y
|
||||
CONFIG_ARCH_BERLIN=y
|
||||
CONFIG_ARCH_BLAIZE=y
|
||||
CONFIG_ARCH_EXYNOS=y
|
||||
CONFIG_ARCH_SPARX5=y
|
||||
CONFIG_ARCH_K3=y
|
||||
@ -330,6 +331,7 @@ CONFIG_VIRTIO_NET=y
|
||||
CONFIG_MHI_NET=m
|
||||
CONFIG_NET_DSA_BCM_SF2=m
|
||||
CONFIG_NET_DSA_MSCC_FELIX=m
|
||||
CONFIG_ENA_ETHERNET=m
|
||||
CONFIG_AMD_XGBE=y
|
||||
CONFIG_NET_XGENE=y
|
||||
CONFIG_ATL1C=m
|
||||
|
||||
Loading…
Reference in New Issue
Block a user