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ata: ahci_imx: Clean up code by using i.MX8Q HSIO PHY driver
Clean up code by using PHY interface provided by the PHY driver under PHY subsystem(drivers/phy/freescale/phy-fsl-imx8qm-hsio.c). Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/1723428055-27021-3-git-send-email-hongxing.zhu@nxp.com Signed-off-by: Niklas Cassel <cassel@kernel.org>
This commit is contained in:
Richard Zhu
Niklas Cassel
parent
5ff80684fb
commit
4147e9d240
@ -19,6 +19,7 @@
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#include <linux/libata.h>
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#include <linux/hwmon.h>
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#include <linux/hwmon-sysfs.h>
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#include <linux/phy/phy.h>
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#include <linux/thermal.h>
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#include "ahci.h"
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@ -44,42 +45,6 @@ enum {
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/* Clock Reset Register */
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IMX_CLOCK_RESET = 0x7f3f,
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IMX_CLOCK_RESET_RESET = 1 << 0,
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/* IMX8QM HSIO AHCI definitions */
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IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET = 0x03,
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IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET = 0x09,
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IMX8QM_SATA_PHY_IMPED_RATIO_85OHM = 0x6c,
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IMX8QM_LPCG_PHYX2_OFFSET = 0x00000,
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IMX8QM_CSR_PHYX2_OFFSET = 0x90000,
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IMX8QM_CSR_PHYX1_OFFSET = 0xa0000,
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IMX8QM_CSR_PHYX_STTS0_OFFSET = 0x4,
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IMX8QM_CSR_PCIEA_OFFSET = 0xb0000,
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IMX8QM_CSR_PCIEB_OFFSET = 0xc0000,
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IMX8QM_CSR_SATA_OFFSET = 0xd0000,
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IMX8QM_CSR_PCIE_CTRL2_OFFSET = 0x8,
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IMX8QM_CSR_MISC_OFFSET = 0xe0000,
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IMX8QM_LPCG_PHYX2_PCLK0_MASK = (0x3 << 16),
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IMX8QM_LPCG_PHYX2_PCLK1_MASK = (0x3 << 20),
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IMX8QM_PHY_APB_RSTN_0 = BIT(0),
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IMX8QM_PHY_MODE_SATA = BIT(19),
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IMX8QM_PHY_MODE_MASK = (0xf << 17),
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IMX8QM_PHY_PIPE_RSTN_0 = BIT(24),
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IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0 = BIT(25),
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IMX8QM_PHY_PIPE_RSTN_1 = BIT(26),
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IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1 = BIT(27),
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IMX8QM_STTS0_LANE0_TX_PLL_LOCK = BIT(4),
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IMX8QM_MISC_IOB_RXENA = BIT(0),
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IMX8QM_MISC_IOB_TXENA = BIT(1),
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IMX8QM_MISC_PHYX1_EPCS_SEL = BIT(12),
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IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1 = BIT(24),
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IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0 = BIT(25),
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IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1 = BIT(28),
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IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0 = BIT(29),
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IMX8QM_SATA_CTRL_RESET_N = BIT(12),
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IMX8QM_SATA_CTRL_EPCS_PHYRESET_N = BIT(7),
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IMX8QM_CTRL_BUTTON_RST_N = BIT(21),
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IMX8QM_CTRL_POWER_UP_RST_N = BIT(23),
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IMX8QM_CTRL_LTSSM_ENABLE = BIT(4),
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};
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enum ahci_imx_type {
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@ -95,14 +60,10 @@ struct imx_ahci_priv {
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struct clk *sata_clk;
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struct clk *sata_ref_clk;
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struct clk *ahb_clk;
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struct clk *epcs_tx_clk;
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struct clk *epcs_rx_clk;
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struct clk *phy_apbclk;
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struct clk *phy_pclk0;
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struct clk *phy_pclk1;
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void __iomem *phy_base;
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struct gpio_desc *clkreq_gpiod;
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struct regmap *gpr;
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struct phy *sata_phy;
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struct phy *cali_phy0;
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struct phy *cali_phy1;
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bool no_device;
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bool first_time;
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u32 phy_params;
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@ -450,201 +411,73 @@ ATTRIBUTE_GROUPS(fsl_sata_ahci);
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static int imx8_sata_enable(struct ahci_host_priv *hpriv)
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{
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u32 val, reg;
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int i, ret;
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u32 val;
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int ret;
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struct imx_ahci_priv *imxpriv = hpriv->plat_data;
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struct device *dev = &imxpriv->ahci_pdev->dev;
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/* configure the hsio for sata */
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ret = clk_prepare_enable(imxpriv->phy_pclk0);
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if (ret < 0) {
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dev_err(dev, "can't enable phy_pclk0.\n");
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/*
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* Since "REXT" pin is only present for first lane of i.MX8QM
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* PHY, its calibration results will be stored, passed through
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* to the second lane PHY, and shared with all three lane PHYs.
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*
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* Initialize the first two lane PHYs here, although only the
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* third lane PHY is used by SATA.
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*/
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ret = phy_init(imxpriv->cali_phy0);
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if (ret) {
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dev_err(dev, "cali PHY init failed\n");
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return ret;
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}
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ret = clk_prepare_enable(imxpriv->phy_pclk1);
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if (ret < 0) {
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dev_err(dev, "can't enable phy_pclk1.\n");
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goto disable_phy_pclk0;
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ret = phy_power_on(imxpriv->cali_phy0);
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if (ret) {
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dev_err(dev, "cali PHY power on failed\n");
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goto err_cali_phy0_exit;
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}
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ret = clk_prepare_enable(imxpriv->epcs_tx_clk);
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if (ret < 0) {
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dev_err(dev, "can't enable epcs_tx_clk.\n");
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goto disable_phy_pclk1;
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ret = phy_init(imxpriv->cali_phy1);
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if (ret) {
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dev_err(dev, "cali PHY1 init failed\n");
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goto err_cali_phy0_off;
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}
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ret = clk_prepare_enable(imxpriv->epcs_rx_clk);
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if (ret < 0) {
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dev_err(dev, "can't enable epcs_rx_clk.\n");
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goto disable_epcs_tx_clk;
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ret = phy_power_on(imxpriv->cali_phy1);
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if (ret) {
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dev_err(dev, "cali PHY1 power on failed\n");
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goto err_cali_phy1_exit;
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}
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ret = clk_prepare_enable(imxpriv->phy_apbclk);
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if (ret < 0) {
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dev_err(dev, "can't enable phy_apbclk.\n");
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goto disable_epcs_rx_clk;
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ret = phy_init(imxpriv->sata_phy);
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if (ret) {
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dev_err(dev, "sata PHY init failed\n");
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goto err_cali_phy1_off;
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}
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/* Configure PHYx2 PIPE_RSTN */
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regmap_read(imxpriv->gpr, IMX8QM_CSR_PCIEA_OFFSET +
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IMX8QM_CSR_PCIE_CTRL2_OFFSET, &val);
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if ((val & IMX8QM_CTRL_LTSSM_ENABLE) == 0) {
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/* The link of the PCIEA of HSIO is down */
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regmap_update_bits(imxpriv->gpr,
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IMX8QM_CSR_PHYX2_OFFSET,
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IMX8QM_PHY_PIPE_RSTN_0 |
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IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0,
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IMX8QM_PHY_PIPE_RSTN_0 |
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IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0);
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ret = phy_set_mode(imxpriv->sata_phy, PHY_MODE_SATA);
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if (ret) {
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dev_err(dev, "unable to set SATA PHY mode\n");
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goto err_sata_phy_exit;
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}
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regmap_read(imxpriv->gpr, IMX8QM_CSR_PCIEB_OFFSET +
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IMX8QM_CSR_PCIE_CTRL2_OFFSET, ®);
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if ((reg & IMX8QM_CTRL_LTSSM_ENABLE) == 0) {
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/* The link of the PCIEB of HSIO is down */
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regmap_update_bits(imxpriv->gpr,
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IMX8QM_CSR_PHYX2_OFFSET,
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IMX8QM_PHY_PIPE_RSTN_1 |
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IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1,
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IMX8QM_PHY_PIPE_RSTN_1 |
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IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1);
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}
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if (((reg | val) & IMX8QM_CTRL_LTSSM_ENABLE) == 0) {
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/* The links of both PCIA and PCIEB of HSIO are down */
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regmap_update_bits(imxpriv->gpr,
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IMX8QM_LPCG_PHYX2_OFFSET,
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IMX8QM_LPCG_PHYX2_PCLK0_MASK |
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IMX8QM_LPCG_PHYX2_PCLK1_MASK,
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0);
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ret = phy_power_on(imxpriv->sata_phy);
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if (ret) {
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dev_err(dev, "sata PHY power up failed\n");
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goto err_sata_phy_exit;
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}
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/* set PWR_RST and BT_RST of csr_pciea */
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val = IMX8QM_CSR_PCIEA_OFFSET + IMX8QM_CSR_PCIE_CTRL2_OFFSET;
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regmap_update_bits(imxpriv->gpr,
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val,
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IMX8QM_CTRL_BUTTON_RST_N,
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IMX8QM_CTRL_BUTTON_RST_N);
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regmap_update_bits(imxpriv->gpr,
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val,
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IMX8QM_CTRL_POWER_UP_RST_N,
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IMX8QM_CTRL_POWER_UP_RST_N);
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/* The cali_phy# can be turned off after SATA PHY is initialized. */
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phy_power_off(imxpriv->cali_phy1);
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phy_exit(imxpriv->cali_phy1);
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phy_power_off(imxpriv->cali_phy0);
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phy_exit(imxpriv->cali_phy0);
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/* PHYX1_MODE to SATA */
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regmap_update_bits(imxpriv->gpr,
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IMX8QM_CSR_PHYX1_OFFSET,
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IMX8QM_PHY_MODE_MASK,
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IMX8QM_PHY_MODE_SATA);
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return 0;
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/*
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* BIT0 RXENA 1, BIT1 TXENA 0
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* BIT12 PHY_X1_EPCS_SEL 1.
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*/
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regmap_update_bits(imxpriv->gpr,
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IMX8QM_CSR_MISC_OFFSET,
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IMX8QM_MISC_IOB_RXENA,
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IMX8QM_MISC_IOB_RXENA);
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regmap_update_bits(imxpriv->gpr,
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IMX8QM_CSR_MISC_OFFSET,
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IMX8QM_MISC_IOB_TXENA,
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0);
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regmap_update_bits(imxpriv->gpr,
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IMX8QM_CSR_MISC_OFFSET,
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IMX8QM_MISC_PHYX1_EPCS_SEL,
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IMX8QM_MISC_PHYX1_EPCS_SEL);
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/*
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* It is possible, for PCIe and SATA are sharing
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* the same clock source, HPLL or external oscillator.
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* When PCIe is in low power modes (L1.X or L2 etc),
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* the clock source can be turned off. In this case,
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* if this clock source is required to be toggling by
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* SATA, then SATA functions will be abnormal.
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* Set the override here to avoid it.
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*/
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regmap_update_bits(imxpriv->gpr,
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IMX8QM_CSR_MISC_OFFSET,
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IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1 |
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IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0 |
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IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1 |
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IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0,
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IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1 |
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IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0 |
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IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1 |
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IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0);
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/* clear PHY RST, then set it */
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regmap_update_bits(imxpriv->gpr,
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IMX8QM_CSR_SATA_OFFSET,
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IMX8QM_SATA_CTRL_EPCS_PHYRESET_N,
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0);
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regmap_update_bits(imxpriv->gpr,
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IMX8QM_CSR_SATA_OFFSET,
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IMX8QM_SATA_CTRL_EPCS_PHYRESET_N,
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IMX8QM_SATA_CTRL_EPCS_PHYRESET_N);
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/* CTRL RST: SET -> delay 1 us -> CLEAR -> SET */
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regmap_update_bits(imxpriv->gpr,
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IMX8QM_CSR_SATA_OFFSET,
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IMX8QM_SATA_CTRL_RESET_N,
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IMX8QM_SATA_CTRL_RESET_N);
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udelay(1);
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regmap_update_bits(imxpriv->gpr,
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IMX8QM_CSR_SATA_OFFSET,
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IMX8QM_SATA_CTRL_RESET_N,
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0);
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regmap_update_bits(imxpriv->gpr,
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IMX8QM_CSR_SATA_OFFSET,
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IMX8QM_SATA_CTRL_RESET_N,
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IMX8QM_SATA_CTRL_RESET_N);
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/* APB reset */
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regmap_update_bits(imxpriv->gpr,
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IMX8QM_CSR_PHYX1_OFFSET,
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IMX8QM_PHY_APB_RSTN_0,
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IMX8QM_PHY_APB_RSTN_0);
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for (i = 0; i < 100; i++) {
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reg = IMX8QM_CSR_PHYX1_OFFSET +
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IMX8QM_CSR_PHYX_STTS0_OFFSET;
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regmap_read(imxpriv->gpr, reg, &val);
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val &= IMX8QM_STTS0_LANE0_TX_PLL_LOCK;
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if (val == IMX8QM_STTS0_LANE0_TX_PLL_LOCK)
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break;
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udelay(1);
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}
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if (val != IMX8QM_STTS0_LANE0_TX_PLL_LOCK) {
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dev_err(dev, "TX PLL of the PHY is not locked\n");
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ret = -ENODEV;
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} else {
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writeb(imxpriv->imped_ratio, imxpriv->phy_base +
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IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET);
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writeb(imxpriv->imped_ratio, imxpriv->phy_base +
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IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET);
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reg = readb(imxpriv->phy_base +
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IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET);
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if (unlikely(reg != imxpriv->imped_ratio))
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dev_info(dev, "Can't set PHY RX impedance ratio.\n");
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reg = readb(imxpriv->phy_base +
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IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET);
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if (unlikely(reg != imxpriv->imped_ratio))
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dev_info(dev, "Can't set PHY TX impedance ratio.\n");
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usleep_range(50, 100);
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/*
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* To reduce the power consumption, gate off
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* the PHY clks
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*/
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clk_disable_unprepare(imxpriv->phy_apbclk);
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clk_disable_unprepare(imxpriv->phy_pclk1);
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clk_disable_unprepare(imxpriv->phy_pclk0);
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return ret;
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}
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clk_disable_unprepare(imxpriv->phy_apbclk);
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disable_epcs_rx_clk:
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clk_disable_unprepare(imxpriv->epcs_rx_clk);
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disable_epcs_tx_clk:
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clk_disable_unprepare(imxpriv->epcs_tx_clk);
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disable_phy_pclk1:
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clk_disable_unprepare(imxpriv->phy_pclk1);
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disable_phy_pclk0:
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clk_disable_unprepare(imxpriv->phy_pclk0);
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err_sata_phy_exit:
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phy_exit(imxpriv->sata_phy);
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err_cali_phy1_off:
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phy_power_off(imxpriv->cali_phy1);
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err_cali_phy1_exit:
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phy_exit(imxpriv->cali_phy1);
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err_cali_phy0_off:
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phy_power_off(imxpriv->cali_phy0);
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err_cali_phy0_exit:
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phy_exit(imxpriv->cali_phy0);
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return ret;
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}
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@ -698,6 +531,9 @@ static int imx_sata_enable(struct ahci_host_priv *hpriv)
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}
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} else if (imxpriv->type == AHCI_IMX8QM) {
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ret = imx8_sata_enable(hpriv);
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if (ret)
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goto disable_clk;
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}
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usleep_range(1000, 2000);
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@ -736,8 +572,10 @@ static void imx_sata_disable(struct ahci_host_priv *hpriv)
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break;
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case AHCI_IMX8QM:
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clk_disable_unprepare(imxpriv->epcs_rx_clk);
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clk_disable_unprepare(imxpriv->epcs_tx_clk);
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if (imxpriv->sata_phy) {
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phy_power_off(imxpriv->sata_phy);
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phy_exit(imxpriv->sata_phy);
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}
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break;
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default:
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@ -760,6 +598,9 @@ static void ahci_imx_error_handler(struct ata_port *ap)
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ahci_error_handler(ap);
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if (imxpriv->type == AHCI_IMX8QM)
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return;
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if (!(imxpriv->first_time) || ahci_imx_hotplug)
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return;
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@ -986,65 +827,19 @@ static const struct scsi_host_template ahci_platform_sht = {
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static int imx8_sata_probe(struct device *dev, struct imx_ahci_priv *imxpriv)
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{
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struct resource *phy_res;
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struct platform_device *pdev = imxpriv->ahci_pdev;
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struct device_node *np = dev->of_node;
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if (of_property_read_u32(np, "fsl,phy-imp", &imxpriv->imped_ratio))
|
||||
imxpriv->imped_ratio = IMX8QM_SATA_PHY_IMPED_RATIO_85OHM;
|
||||
phy_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
|
||||
if (phy_res) {
|
||||
imxpriv->phy_base = devm_ioremap(dev, phy_res->start,
|
||||
resource_size(phy_res));
|
||||
if (!imxpriv->phy_base) {
|
||||
dev_err(dev, "error with ioremap\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
} else {
|
||||
dev_err(dev, "missing *phy* reg region.\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
imxpriv->gpr =
|
||||
syscon_regmap_lookup_by_phandle(np, "hsio");
|
||||
if (IS_ERR(imxpriv->gpr)) {
|
||||
dev_err(dev, "unable to find gpr registers\n");
|
||||
return PTR_ERR(imxpriv->gpr);
|
||||
}
|
||||
|
||||
imxpriv->epcs_tx_clk = devm_clk_get(dev, "epcs_tx");
|
||||
if (IS_ERR(imxpriv->epcs_tx_clk)) {
|
||||
dev_err(dev, "can't get epcs_tx_clk clock.\n");
|
||||
return PTR_ERR(imxpriv->epcs_tx_clk);
|
||||
}
|
||||
imxpriv->epcs_rx_clk = devm_clk_get(dev, "epcs_rx");
|
||||
if (IS_ERR(imxpriv->epcs_rx_clk)) {
|
||||
dev_err(dev, "can't get epcs_rx_clk clock.\n");
|
||||
return PTR_ERR(imxpriv->epcs_rx_clk);
|
||||
}
|
||||
imxpriv->phy_pclk0 = devm_clk_get(dev, "phy_pclk0");
|
||||
if (IS_ERR(imxpriv->phy_pclk0)) {
|
||||
dev_err(dev, "can't get phy_pclk0 clock.\n");
|
||||
return PTR_ERR(imxpriv->phy_pclk0);
|
||||
}
|
||||
imxpriv->phy_pclk1 = devm_clk_get(dev, "phy_pclk1");
|
||||
if (IS_ERR(imxpriv->phy_pclk1)) {
|
||||
dev_err(dev, "can't get phy_pclk1 clock.\n");
|
||||
return PTR_ERR(imxpriv->phy_pclk1);
|
||||
}
|
||||
imxpriv->phy_apbclk = devm_clk_get(dev, "phy_apbclk");
|
||||
if (IS_ERR(imxpriv->phy_apbclk)) {
|
||||
dev_err(dev, "can't get phy_apbclk clock.\n");
|
||||
return PTR_ERR(imxpriv->phy_apbclk);
|
||||
}
|
||||
|
||||
/* Fetch GPIO, then enable the external OSC */
|
||||
imxpriv->clkreq_gpiod = devm_gpiod_get_optional(dev, "clkreq",
|
||||
GPIOD_OUT_LOW | GPIOD_FLAGS_BIT_NONEXCLUSIVE);
|
||||
if (IS_ERR(imxpriv->clkreq_gpiod))
|
||||
return PTR_ERR(imxpriv->clkreq_gpiod);
|
||||
if (imxpriv->clkreq_gpiod)
|
||||
gpiod_set_consumer_name(imxpriv->clkreq_gpiod, "SATA CLKREQ");
|
||||
imxpriv->sata_phy = devm_phy_get(dev, "sata-phy");
|
||||
if (IS_ERR(imxpriv->sata_phy))
|
||||
return dev_err_probe(dev, PTR_ERR(imxpriv->sata_phy),
|
||||
"Failed to get sata_phy\n");
|
||||
|
||||
imxpriv->cali_phy0 = devm_phy_get(dev, "cali-phy0");
|
||||
if (IS_ERR(imxpriv->cali_phy0))
|
||||
return dev_err_probe(dev, PTR_ERR(imxpriv->cali_phy0),
|
||||
"Failed to get cali_phy0\n");
|
||||
imxpriv->cali_phy1 = devm_phy_get(dev, "cali-phy1");
|
||||
if (IS_ERR(imxpriv->cali_phy1))
|
||||
return dev_err_probe(dev, PTR_ERR(imxpriv->cali_phy1),
|
||||
"Failed to get cali_phy1\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user