dt-bindings: phy: socionext,uniphier: add top-level constraints

Properties with variable number of items per each device are expected to
have widest constraints in top-level "properties:" block and further
customized (narrowed) in "if:then:".  Add missing top-level constraints
for clock-names and reset-names.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20240818172835.121757-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Krzysztof Kozlowski 2024-08-18 19:28:35 +02:00 committed by Vinod Koul
parent 9dab00ee95
commit 45a4237b9b
4 changed files with 22 additions and 8 deletions

View File

@ -30,13 +30,17 @@ properties:
minItems: 1
maxItems: 2
clock-names: true
clock-names:
minItems: 1
maxItems: 6
resets:
minItems: 2
maxItems: 6
reset-names: true
reset-names:
minItems: 2
maxItems: 6
allOf:
- if:

View File

@ -31,13 +31,17 @@ properties:
minItems: 1
maxItems: 2
clock-names: true
clock-names:
minItems: 1
maxItems: 2
resets:
minItems: 1
maxItems: 2
reset-names: true
reset-names:
minItems: 1
maxItems: 2
socionext,syscon:
$ref: /schemas/types.yaml#/definitions/phandle

View File

@ -34,12 +34,15 @@ properties:
minItems: 2
maxItems: 3
clock-names: true
clock-names:
minItems: 2
maxItems: 3
resets:
maxItems: 2
reset-names: true
reset-names:
maxItems: 2
vbus-supply:
description: A phandle to the regulator for USB VBUS

View File

@ -35,12 +35,15 @@ properties:
minItems: 2
maxItems: 3
clock-names: true
clock-names:
minItems: 2
maxItems: 3
resets:
maxItems: 2
reset-names: true
reset-names:
maxItems: 2
vbus-supply:
description: A phandle to the regulator for USB VBUS, only for USB host