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staging: et131x: Replace magic numbers in et1310_phy.c with defines
Replaced et131x_phy.c magic numbers specifying registers and their values with defines, defined in et131x_phy.h Signed-off-by: Mark Einon <mark.einon@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Mark Einon
Greg Kroah-Hartman
parent
88982cb1b1
commit
46df22bd12
@ -122,12 +122,11 @@ int et131x_mdio_reset(struct mii_bus *bus)
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struct net_device *netdev = bus->priv;
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struct et131x_adapter *adapter = netdev_priv(netdev);
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et131x_mii_write(adapter, MII_BMCR, 0x8000);
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et131x_mii_write(adapter, MII_BMCR, BMCR_RESET);
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return 0;
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}
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int et131x_mii_read(struct et131x_adapter *adapter, u8 reg, u16 *value)
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{
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struct phy_device *phydev = adapter->phydev;
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@ -293,9 +292,9 @@ void et1310_phy_power_down(struct et131x_adapter *adapter, bool down)
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u16 data;
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et131x_mii_read(adapter, MII_BMCR, &data);
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data &= ~0x0800; /* Power UP */
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if (down) /* Power DOWN */
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data |= 0x0800;
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data &= ~BMCR_PDOWN;
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if (down)
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data |= BMCR_PDOWN;
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et131x_mii_write(adapter, MII_BMCR, data);
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}
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@ -333,19 +332,20 @@ static void et1310_phy_link_status(struct et131x_adapter *adapter,
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et131x_mii_read(adapter, PHY_PHY_STATUS, &vmi_phystatus);
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et131x_mii_read(adapter, MII_BMCR, &control);
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*link_status = (vmi_phystatus & 0x0040) ? 1 : 0;
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*autoneg = (control & 0x1000) ? ((vmi_phystatus & 0x0020) ?
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*link_status = (vmi_phystatus & ET_PHY_LSTATUS) ? 1 : 0;
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*autoneg = (control & ET_PHY_AUTONEG_STATUS) ?
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((vmi_phystatus & ET_PHY_AUTONEG_ENABLE) ?
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TRUEPHY_ANEG_COMPLETE :
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TRUEPHY_ANEG_NOT_COMPLETE) :
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TRUEPHY_ANEG_DISABLED;
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*linkspeed = (vmi_phystatus & 0x0300) >> 8;
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*duplex_mode = (vmi_phystatus & 0x0080) >> 7;
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*linkspeed = (vmi_phystatus & ET_PHY_SPEED_STATUS) >> 8;
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*duplex_mode = (vmi_phystatus & ET_PHY_DUPLEX_STATUS) >> 7;
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/* NOTE: Need to complete this */
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*mdi_mdix = 0;
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*masterslave = (is1000BaseT & 0x4000) ?
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*masterslave = (is1000BaseT & ET_1000BT_MSTR_SLV) ?
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TRUEPHY_CFG_MASTER : TRUEPHY_CFG_SLAVE;
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*polarity = (vmi_phystatus & 0x0400) ?
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*polarity = (vmi_phystatus & ET_PHY_POLARITY_STATUS) ?
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TRUEPHY_POLARITY_INVERTED : TRUEPHY_POLARITY_NORMAL;
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}
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@ -402,15 +402,17 @@ void et131x_xcvr_init(struct et131x_adapter *adapter)
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/* Zero out the adapter structure variable representing BMSR */
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adapter->bmsr = 0;
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et131x_mii_read(adapter, (u8) offsetof(struct mi_regs, isr), &isr);
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et131x_mii_read(adapter, (u8) offsetof(struct mi_regs, imr), &imr);
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et131x_mii_read(adapter, PHY_INTERRUPT_STATUS, &isr);
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et131x_mii_read(adapter, PHY_INTERRUPT_MASK, &imr);
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/* Set the link status interrupt only. Bad behavior when link status
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* and auto neg are set, we run into a nested interrupt problem
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*/
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imr |= 0x0105;
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imr |= (ET_PHY_INT_MASK_AUTONEGSTAT &
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ET_PHY_INT_MASK_LINKSTAT &
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ET_PHY_INT_MASK_ENABLE);
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et131x_mii_write(adapter, (u8) offsetof(struct mi_regs, imr), imr);
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et131x_mii_write(adapter, PHY_INTERRUPT_MASK, imr);
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/* Set the LED behavior such that LED 1 indicates speed (off =
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* 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates
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@ -421,19 +423,17 @@ void et131x_xcvr_init(struct et131x_adapter *adapter)
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* EEPROM. However, the above description is the default.
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*/
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if ((adapter->eeprom_data[1] & 0x4) == 0) {
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et131x_mii_read(adapter, (u8) offsetof(struct mi_regs, lcr2),
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&lcr2);
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et131x_mii_read(adapter, PHY_LED_2, &lcr2);
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lcr2 &= 0x00FF;
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lcr2 |= 0xA000; /* led link */
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lcr2 &= (ET_LED2_LED_100TX & ET_LED2_LED_1000T);
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lcr2 |= (LED_VAL_LINKON_ACTIVE << LED_LINK_SHIFT);
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if ((adapter->eeprom_data[1] & 0x8) == 0)
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lcr2 |= 0x0300;
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lcr2 |= (LED_VAL_1000BT_100BTX << LED_TXRX_SHIFT);
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else
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lcr2 |= 0x0400;
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lcr2 |= (LED_VAL_LINKON << LED_TXRX_SHIFT);
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et131x_mii_write(adapter, (u8) offsetof(struct mi_regs, lcr2),
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lcr2);
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et131x_mii_write(adapter, PHY_LED_2, lcr2);
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}
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}
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@ -464,14 +464,16 @@ void et131x_mii_check(struct et131x_adapter *adapter,
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*/
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u16 register18;
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et131x_mii_read(adapter, 0x12, ®ister18);
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et131x_mii_write(adapter, 0x12,
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et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG,
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®ister18);
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et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG,
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register18 | 0x4);
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et131x_mii_write(adapter, 0x10,
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et131x_mii_write(adapter, PHY_INDEX_REG,
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register18 | 0x8402);
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et131x_mii_write(adapter, 0x11,
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et131x_mii_write(adapter, PHY_DATA_REG,
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register18 | 511);
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et131x_mii_write(adapter, 0x12, register18);
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et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG,
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register18);
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}
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/* Free the packets being actively sent & stopped */
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@ -516,22 +518,25 @@ void et131x_mii_check(struct et131x_adapter *adapter,
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*/
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u16 register18;
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et131x_mii_read(adapter, 0x12, ®ister18);
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et131x_mii_write(adapter, 0x12,
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et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG,
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®ister18);
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et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG,
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register18 | 0x4);
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et131x_mii_write(adapter, 0x10,
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et131x_mii_write(adapter, PHY_INDEX_REG,
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register18 | 0x8402);
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et131x_mii_write(adapter, 0x11,
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et131x_mii_write(adapter, PHY_DATA_REG,
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register18 | 511);
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et131x_mii_write(adapter, 0x12, register18);
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et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG,
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register18);
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}
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et1310_config_flow_control(adapter);
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if (phydev && phydev->speed == SPEED_1000 &&
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adapter->registry_jumbo_packet > 2048)
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et1310_phy_and_or_reg(adapter, 0x16, 0xcfff,
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0x2000);
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et1310_phy_and_or_reg(adapter, PHY_CONFIG,
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~ET_PHY_CONFIG_TX_FIFO_DEPTH,
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ET_PHY_CONFIG_FIFO_DEPTH_32);
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et131x_set_rx_dma_timer(adapter);
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et1310_config_mac_regs2(adapter);
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@ -61,6 +61,25 @@
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#include "et1310_address_map.h"
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/* some defines for modem registers that seem to be 'reserved' */
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#define PHY_INDEX_REG 0x10
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#define PHY_DATA_REG 0x11
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#define PHY_MPHY_CONTROL_REG 0x12
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/* defines for specified registers */
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#define PHY_LOOPBACK_CONTROL 0x13 /* TRU_VMI_LOOPBACK_CONTROL_1_REG 19 */
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/* TRU_VMI_LOOPBACK_CONTROL_2_REG 20 */
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#define PHY_REGISTER_MGMT_CONTROL 0x15 /* TRU_VMI_MI_SEQ_CONTROL_REG 21 */
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#define PHY_CONFIG 0x16 /* TRU_VMI_CONFIGURATION_REG 22 */
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#define PHY_PHY_CONTROL 0x17 /* TRU_VMI_PHY_CONTROL_REG 23 */
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#define PHY_INTERRUPT_MASK 0x18 /* TRU_VMI_INTERRUPT_MASK_REG 24 */
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#define PHY_INTERRUPT_STATUS 0x19 /* TRU_VMI_INTERRUPT_STATUS_REG 25 */
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#define PHY_PHY_STATUS 0x1A /* TRU_VMI_PHY_STATUS_REG 26 */
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#define PHY_LED_1 0x1B /* TRU_VMI_LED_CONTROL_1_REG 27 */
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#define PHY_LED_2 0x1C /* TRU_VMI_LED_CONTROL_2_REG 28 */
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/* TRU_VMI_LINK_CONTROL_REG 29 */
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/* TRU_VMI_TIMING_CONTROL_REG */
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/* PHY Register Mapping(MI) Management Interface Regs */
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struct mi_regs {
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u8 bmcr; /* Basic mode control reg(Reg 0x00) */
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@ -90,6 +109,9 @@ struct mi_regs {
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u8 mi_res4[3]; /* Future use by MI working group(Reg 0x1D - 0x1F) */
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};
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/* MI Register 10: Gigabit basic mode status reg(Reg 0x0A) */
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#define ET_1000BT_MSTR_SLV 0x4000
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/* MI Register 16 - 18: Reserved Reg(0x10-0x12) */
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/* MI Register 19: Loopback Control Reg(0x13)
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@ -128,6 +150,13 @@ struct mi_regs {
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* 2-0: mac_if_mode
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*/
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#define ET_PHY_CONFIG_TX_FIFO_DEPTH 0x3000
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#define ET_PHY_CONFIG_FIFO_DEPTH_8 0x0000
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#define ET_PHY_CONFIG_FIFO_DEPTH_16 0x1000
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#define ET_PHY_CONFIG_FIFO_DEPTH_32 0x2000
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#define ET_PHY_CONFIG_FIFO_DEPTH_64 0x3000
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/* MI Register 23: PHY CONTROL Reg(0x17)
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* 15: reserved
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* 14: tdr_en
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@ -156,6 +185,9 @@ struct mi_regs {
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* 0: int_en
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*/
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#define ET_PHY_INT_MASK_AUTONEGSTAT 0x0100
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#define ET_PHY_INT_MASK_LINKSTAT 0x0004
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#define ET_PHY_INT_MASK_ENABLE 0x0001
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/* MI Register 25: Interrupt Status Reg(0x19)
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* 15-10: reserved
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@ -187,6 +219,12 @@ struct mi_regs {
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* 1: pause_en
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* 0: asymmetric_dir
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*/
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#define ET_PHY_AUTONEG_STATUS 0x1000
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#define ET_PHY_POLARITY_STATUS 0x0400
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#define ET_PHY_SPEED_STATUS 0x0300
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#define ET_PHY_DUPLEX_STATUS 0x0080
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#define ET_PHY_LSTATUS 0x0040
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#define ET_PHY_AUTONEG_ENABLE 0x0020
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/* MI Register 27: LED Control Reg 1(0x1B)
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* 15-14: reserved
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@ -205,11 +243,35 @@ struct mi_regs {
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* 7-4: led_100BaseTX
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* 3-0: led_1000BaseT
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*/
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#define ET_LED2_LED_LINK 0xF000
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#define ET_LED2_LED_TXRX 0x0F00
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#define ET_LED2_LED_100TX 0x00F0
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#define ET_LED2_LED_1000T 0x000F
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/* defines for LED control reg 2 values */
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#define LED_VAL_1000BT 0x0
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#define LED_VAL_100BTX 0x1
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#define LED_VAL_10BT 0x2
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#define LED_VAL_1000BT_100BTX 0x3 /* 1000BT on, 100BTX blink */
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#define LED_VAL_LINKON 0x4
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#define LED_VAL_TX 0x5
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#define LED_VAL_RX 0x6
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#define LED_VAL_TXRX 0x7 /* TX or RX */
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#define LED_VAL_DUPLEXFULL 0x8
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#define LED_VAL_COLLISION 0x9
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#define LED_VAL_LINKON_ACTIVE 0xA /* Link on, activity blink */
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#define LED_VAL_LINKON_RECV 0xB /* Link on, receive blink */
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#define LED_VAL_DUPLEXFULL_COLLISION 0xC /* Duplex on, collision blink */
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#define LED_VAL_BLINK 0xD
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#define LED_VAL_ON 0xE
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#define LED_VAL_OFF 0xF
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#define LED_LINK_SHIFT 12
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#define LED_TXRX_SHIFT 8
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#define LED_100TX_SHIFT 4
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/* MI Register 29 - 31: Reserved Reg(0x1D - 0x1E) */
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/* Prototypes for ET1310_phy.c */
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/* Defines for PHY access routines */
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/* Define bit operation flags */
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@ -249,22 +311,4 @@ struct mi_regs {
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#define TRUEPHY_ADV_DUPLEX_BOTH \
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(TRUEPHY_ADV_DUPLEX_FULL | TRUEPHY_ADV_DUPLEX_HALF)
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/* some defines for modem registers that seem to be 'reserved' */
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#define PHY_INDEX_REG 0x10
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#define PHY_DATA_REG 0x11
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#define PHY_MPHY_CONTROL_REG 0x12
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#define PHY_LOOPBACK_CONTROL 0x13 /* TRU_VMI_LOOPBACK_CONTROL_1_REG 19 */
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/* TRU_VMI_LOOPBACK_CONTROL_2_REG 20 */
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#define PHY_REGISTER_MGMT_CONTROL 0x15 /* TRU_VMI_MI_SEQ_CONTROL_REG 21 */
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#define PHY_CONFIG 0x16 /* TRU_VMI_CONFIGURATION_REG 22 */
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#define PHY_PHY_CONTROL 0x17 /* TRU_VMI_PHY_CONTROL_REG 23 */
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#define PHY_INTERRUPT_MASK 0x18 /* TRU_VMI_INTERRUPT_MASK_REG 24 */
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#define PHY_INTERRUPT_STATUS 0x19 /* TRU_VMI_INTERRUPT_STATUS_REG 25 */
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#define PHY_PHY_STATUS 0x1A /* TRU_VMI_PHY_STATUS_REG 26 */
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#define PHY_LED_1 0x1B /* TRU_VMI_LED_CONTROL_1_REG 27 */
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#define PHY_LED_2 0x1C /* TRU_VMI_LED_CONTROL_2_REG 28 */
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/* TRU_VMI_LINK_CONTROL_REG 29 */
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/* TRU_VMI_TIMING_CONTROL_REG */
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#endif /* _ET1310_PHY_H_ */
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