mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
synced 2024-12-29 17:22:07 +00:00
MIPS: AR7: remove platform
After a discussion about removing VLYNQ support from the Kernel, it was concluded that its only user, the AR7 platform can go [1]. Even OpenWRT has removed support because these devices are "stuck with 3.18" [2]. [1] https://lore.kernel.org/r/3395161f-2543-46f0-83d9-b918800305e1@gmail.com [2] https://openwrt.org/docs/techref/targets/ar7 Suggested-by: Jonas Gorski <jonas.gorski@gmail.com> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Wolfram Sang
Thomas Bogendoerfer
parent
1bc6e01372
commit
4b7d3ab445
@ -2,7 +2,6 @@
|
||||
# All platforms listed in alphabetic order
|
||||
|
||||
platform-$(CONFIG_MIPS_ALCHEMY) += alchemy/
|
||||
platform-$(CONFIG_AR7) += ar7/
|
||||
platform-$(CONFIG_ATH25) += ath25/
|
||||
platform-$(CONFIG_ATH79) += ath79/
|
||||
platform-$(CONFIG_BCM47XX) += bcm47xx/
|
||||
|
||||
@ -202,28 +202,6 @@ config MIPS_ALCHEMY
|
||||
select SYS_SUPPORTS_ZBOOT
|
||||
select COMMON_CLK
|
||||
|
||||
config AR7
|
||||
bool "Texas Instruments AR7"
|
||||
select BOOT_ELF32
|
||||
select COMMON_CLK
|
||||
select DMA_NONCOHERENT
|
||||
select CEVT_R4K
|
||||
select CSRC_R4K
|
||||
select IRQ_MIPS_CPU
|
||||
select NO_EXCEPT_FILL
|
||||
select SWAP_IO_SPACE
|
||||
select SYS_HAS_CPU_MIPS32_R1
|
||||
select SYS_HAS_EARLY_PRINTK
|
||||
select SYS_SUPPORTS_32BIT_KERNEL
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
select SYS_SUPPORTS_MIPS16
|
||||
select SYS_SUPPORTS_ZBOOT_UART16550
|
||||
select GPIOLIB
|
||||
select VLYNQ
|
||||
help
|
||||
Support for the Texas Instruments AR7 System-on-a-Chip
|
||||
family: TNETD7100, 7200 and 7300.
|
||||
|
||||
config ATH25
|
||||
bool "Atheros AR231x/AR531x SoC support"
|
||||
select CEVT_R4K
|
||||
|
||||
@ -1,11 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
obj-y := \
|
||||
prom.o \
|
||||
setup.o \
|
||||
memory.o \
|
||||
irq.o \
|
||||
time.o \
|
||||
platform.o \
|
||||
gpio.o \
|
||||
clock.o
|
||||
@ -1,5 +0,0 @@
|
||||
#
|
||||
# Texas Instruments AR7
|
||||
#
|
||||
cflags-$(CONFIG_AR7) += -I$(srctree)/arch/mips/include/asm/mach-ar7
|
||||
load-$(CONFIG_AR7) += 0xffffffff94100000
|
||||
@ -1,439 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
|
||||
* Copyright (C) 2007 Eugene Konev <ejka@openwrt.org>
|
||||
* Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/export.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/gcd.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/mach-ar7/ar7.h>
|
||||
|
||||
#define BOOT_PLL_SOURCE_MASK 0x3
|
||||
#define CPU_PLL_SOURCE_SHIFT 16
|
||||
#define BUS_PLL_SOURCE_SHIFT 14
|
||||
#define USB_PLL_SOURCE_SHIFT 18
|
||||
#define DSP_PLL_SOURCE_SHIFT 22
|
||||
#define BOOT_PLL_SOURCE_AFE 0
|
||||
#define BOOT_PLL_SOURCE_BUS 0
|
||||
#define BOOT_PLL_SOURCE_REF 1
|
||||
#define BOOT_PLL_SOURCE_XTAL 2
|
||||
#define BOOT_PLL_SOURCE_CPU 3
|
||||
#define BOOT_PLL_BYPASS 0x00000020
|
||||
#define BOOT_PLL_ASYNC_MODE 0x02000000
|
||||
#define BOOT_PLL_2TO1_MODE 0x00008000
|
||||
|
||||
#define TNETD7200_CLOCK_ID_CPU 0
|
||||
#define TNETD7200_CLOCK_ID_DSP 1
|
||||
#define TNETD7200_CLOCK_ID_USB 2
|
||||
|
||||
#define TNETD7200_DEF_CPU_CLK 211000000
|
||||
#define TNETD7200_DEF_DSP_CLK 125000000
|
||||
#define TNETD7200_DEF_USB_CLK 48000000
|
||||
|
||||
struct tnetd7300_clock {
|
||||
u32 ctrl;
|
||||
#define PREDIV_MASK 0x001f0000
|
||||
#define PREDIV_SHIFT 16
|
||||
#define POSTDIV_MASK 0x0000001f
|
||||
u32 unused1[3];
|
||||
u32 pll;
|
||||
#define MUL_MASK 0x0000f000
|
||||
#define MUL_SHIFT 12
|
||||
#define PLL_MODE_MASK 0x00000001
|
||||
#define PLL_NDIV 0x00000800
|
||||
#define PLL_DIV 0x00000002
|
||||
#define PLL_STATUS 0x00000001
|
||||
u32 unused2[3];
|
||||
};
|
||||
|
||||
struct tnetd7300_clocks {
|
||||
struct tnetd7300_clock bus;
|
||||
struct tnetd7300_clock cpu;
|
||||
struct tnetd7300_clock usb;
|
||||
struct tnetd7300_clock dsp;
|
||||
};
|
||||
|
||||
struct tnetd7200_clock {
|
||||
u32 ctrl;
|
||||
u32 unused1[3];
|
||||
#define DIVISOR_ENABLE_MASK 0x00008000
|
||||
u32 mul;
|
||||
u32 prediv;
|
||||
u32 postdiv;
|
||||
u32 postdiv2;
|
||||
u32 unused2[6];
|
||||
u32 cmd;
|
||||
u32 status;
|
||||
u32 cmden;
|
||||
u32 padding[15];
|
||||
};
|
||||
|
||||
struct tnetd7200_clocks {
|
||||
struct tnetd7200_clock cpu;
|
||||
struct tnetd7200_clock dsp;
|
||||
struct tnetd7200_clock usb;
|
||||
};
|
||||
|
||||
struct clk_rate {
|
||||
u32 rate;
|
||||
};
|
||||
static struct clk_rate bus_clk = {
|
||||
.rate = 125000000,
|
||||
};
|
||||
|
||||
static struct clk_rate cpu_clk = {
|
||||
.rate = 150000000,
|
||||
};
|
||||
|
||||
static void approximate(int base, int target, int *prediv,
|
||||
int *postdiv, int *mul)
|
||||
{
|
||||
int i, j, k, freq, res = target;
|
||||
for (i = 1; i <= 16; i++)
|
||||
for (j = 1; j <= 32; j++)
|
||||
for (k = 1; k <= 32; k++) {
|
||||
freq = abs(base / j * i / k - target);
|
||||
if (freq < res) {
|
||||
res = freq;
|
||||
*mul = i;
|
||||
*prediv = j;
|
||||
*postdiv = k;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void calculate(int base, int target, int *prediv, int *postdiv,
|
||||
int *mul)
|
||||
{
|
||||
int tmp_gcd, tmp_base, tmp_freq;
|
||||
|
||||
for (*prediv = 1; *prediv <= 32; (*prediv)++) {
|
||||
tmp_base = base / *prediv;
|
||||
tmp_gcd = gcd(target, tmp_base);
|
||||
*mul = target / tmp_gcd;
|
||||
*postdiv = tmp_base / tmp_gcd;
|
||||
if ((*mul < 1) || (*mul >= 16))
|
||||
continue;
|
||||
if ((*postdiv > 0) & (*postdiv <= 32))
|
||||
break;
|
||||
}
|
||||
|
||||
if (base / *prediv * *mul / *postdiv != target) {
|
||||
approximate(base, target, prediv, postdiv, mul);
|
||||
tmp_freq = base / *prediv * *mul / *postdiv;
|
||||
printk(KERN_WARNING
|
||||
"Adjusted requested frequency %d to %d\n",
|
||||
target, tmp_freq);
|
||||
}
|
||||
|
||||
printk(KERN_DEBUG "Clocks: prediv: %d, postdiv: %d, mul: %d\n",
|
||||
*prediv, *postdiv, *mul);
|
||||
}
|
||||
|
||||
static int tnetd7300_dsp_clock(void)
|
||||
{
|
||||
u32 didr1, didr2;
|
||||
u8 rev = ar7_chip_rev();
|
||||
didr1 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x18));
|
||||
didr2 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x1c));
|
||||
if (didr2 & (1 << 23))
|
||||
return 0;
|
||||
if ((rev >= 0x23) && (rev != 0x57))
|
||||
return 250000000;
|
||||
if ((((didr2 & 0x1fff) << 10) | ((didr1 & 0xffc00000) >> 22))
|
||||
> 4208000)
|
||||
return 250000000;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tnetd7300_get_clock(u32 shift, struct tnetd7300_clock *clock,
|
||||
u32 *bootcr, u32 bus_clock)
|
||||
{
|
||||
int product;
|
||||
int base_clock = AR7_REF_CLOCK;
|
||||
u32 ctrl = readl(&clock->ctrl);
|
||||
u32 pll = readl(&clock->pll);
|
||||
int prediv = ((ctrl & PREDIV_MASK) >> PREDIV_SHIFT) + 1;
|
||||
int postdiv = (ctrl & POSTDIV_MASK) + 1;
|
||||
int divisor = prediv * postdiv;
|
||||
int mul = ((pll & MUL_MASK) >> MUL_SHIFT) + 1;
|
||||
|
||||
switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
|
||||
case BOOT_PLL_SOURCE_BUS:
|
||||
base_clock = bus_clock;
|
||||
break;
|
||||
case BOOT_PLL_SOURCE_REF:
|
||||
base_clock = AR7_REF_CLOCK;
|
||||
break;
|
||||
case BOOT_PLL_SOURCE_XTAL:
|
||||
base_clock = AR7_XTAL_CLOCK;
|
||||
break;
|
||||
case BOOT_PLL_SOURCE_CPU:
|
||||
base_clock = cpu_clk.rate;
|
||||
break;
|
||||
}
|
||||
|
||||
if (*bootcr & BOOT_PLL_BYPASS)
|
||||
return base_clock / divisor;
|
||||
|
||||
if ((pll & PLL_MODE_MASK) == 0)
|
||||
return (base_clock >> (mul / 16 + 1)) / divisor;
|
||||
|
||||
if ((pll & (PLL_NDIV | PLL_DIV)) == (PLL_NDIV | PLL_DIV)) {
|
||||
product = (mul & 1) ?
|
||||
(base_clock * mul) >> 1 :
|
||||
(base_clock * (mul - 1)) >> 2;
|
||||
return product / divisor;
|
||||
}
|
||||
|
||||
if (mul == 16)
|
||||
return base_clock / divisor;
|
||||
|
||||
return base_clock * mul / divisor;
|
||||
}
|
||||
|
||||
static void tnetd7300_set_clock(u32 shift, struct tnetd7300_clock *clock,
|
||||
u32 *bootcr, u32 frequency)
|
||||
{
|
||||
int prediv, postdiv, mul;
|
||||
int base_clock = bus_clk.rate;
|
||||
|
||||
switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
|
||||
case BOOT_PLL_SOURCE_BUS:
|
||||
base_clock = bus_clk.rate;
|
||||
break;
|
||||
case BOOT_PLL_SOURCE_REF:
|
||||
base_clock = AR7_REF_CLOCK;
|
||||
break;
|
||||
case BOOT_PLL_SOURCE_XTAL:
|
||||
base_clock = AR7_XTAL_CLOCK;
|
||||
break;
|
||||
case BOOT_PLL_SOURCE_CPU:
|
||||
base_clock = cpu_clk.rate;
|
||||
break;
|
||||
}
|
||||
|
||||
calculate(base_clock, frequency, &prediv, &postdiv, &mul);
|
||||
|
||||
writel(((prediv - 1) << PREDIV_SHIFT) | (postdiv - 1), &clock->ctrl);
|
||||
mdelay(1);
|
||||
writel(4, &clock->pll);
|
||||
while (readl(&clock->pll) & PLL_STATUS)
|
||||
;
|
||||
writel(((mul - 1) << MUL_SHIFT) | (0xff << 3) | 0x0e, &clock->pll);
|
||||
mdelay(75);
|
||||
}
|
||||
|
||||
static void __init tnetd7300_init_clocks(void)
|
||||
{
|
||||
u32 *bootcr = (u32 *)ioremap(AR7_REGS_DCL, 4);
|
||||
struct tnetd7300_clocks *clocks =
|
||||
ioremap(UR8_REGS_CLOCKS,
|
||||
sizeof(struct tnetd7300_clocks));
|
||||
u32 dsp_clk;
|
||||
struct clk *clk;
|
||||
|
||||
bus_clk.rate = tnetd7300_get_clock(BUS_PLL_SOURCE_SHIFT,
|
||||
&clocks->bus, bootcr, AR7_AFE_CLOCK);
|
||||
|
||||
if (*bootcr & BOOT_PLL_ASYNC_MODE)
|
||||
cpu_clk.rate = tnetd7300_get_clock(CPU_PLL_SOURCE_SHIFT,
|
||||
&clocks->cpu, bootcr, AR7_AFE_CLOCK);
|
||||
else
|
||||
cpu_clk.rate = bus_clk.rate;
|
||||
|
||||
dsp_clk = tnetd7300_dsp_clock();
|
||||
if (dsp_clk == 250000000)
|
||||
tnetd7300_set_clock(DSP_PLL_SOURCE_SHIFT, &clocks->dsp,
|
||||
bootcr, dsp_clk);
|
||||
|
||||
iounmap(clocks);
|
||||
iounmap(bootcr);
|
||||
|
||||
clk = clk_register_fixed_rate(NULL, "cpu", NULL, 0, cpu_clk.rate);
|
||||
clkdev_create(clk, "cpu", NULL);
|
||||
clk = clk_register_fixed_rate(NULL, "dsp", NULL, 0, dsp_clk);
|
||||
clkdev_create(clk, "dsp", NULL);
|
||||
}
|
||||
|
||||
static void tnetd7200_set_clock(int base, struct tnetd7200_clock *clock,
|
||||
int prediv, int postdiv, int postdiv2, int mul, u32 frequency)
|
||||
{
|
||||
printk(KERN_INFO
|
||||
"Clocks: base = %d, frequency = %u, prediv = %d, "
|
||||
"postdiv = %d, postdiv2 = %d, mul = %d\n",
|
||||
base, frequency, prediv, postdiv, postdiv2, mul);
|
||||
|
||||
writel(0, &clock->ctrl);
|
||||
writel(DIVISOR_ENABLE_MASK | ((prediv - 1) & 0x1F), &clock->prediv);
|
||||
writel((mul - 1) & 0xF, &clock->mul);
|
||||
|
||||
while (readl(&clock->status) & 0x1)
|
||||
; /* nop */
|
||||
|
||||
writel(DIVISOR_ENABLE_MASK | ((postdiv - 1) & 0x1F), &clock->postdiv);
|
||||
|
||||
writel(readl(&clock->cmden) | 1, &clock->cmden);
|
||||
writel(readl(&clock->cmd) | 1, &clock->cmd);
|
||||
|
||||
while (readl(&clock->status) & 0x1)
|
||||
; /* nop */
|
||||
|
||||
writel(DIVISOR_ENABLE_MASK | ((postdiv2 - 1) & 0x1F), &clock->postdiv2);
|
||||
|
||||
writel(readl(&clock->cmden) | 1, &clock->cmden);
|
||||
writel(readl(&clock->cmd) | 1, &clock->cmd);
|
||||
|
||||
while (readl(&clock->status) & 0x1)
|
||||
; /* nop */
|
||||
|
||||
writel(readl(&clock->ctrl) | 1, &clock->ctrl);
|
||||
}
|
||||
|
||||
static int tnetd7200_get_clock_base(int clock_id, u32 *bootcr)
|
||||
{
|
||||
if (*bootcr & BOOT_PLL_ASYNC_MODE)
|
||||
/* Async */
|
||||
switch (clock_id) {
|
||||
case TNETD7200_CLOCK_ID_DSP:
|
||||
return AR7_REF_CLOCK;
|
||||
default:
|
||||
return AR7_AFE_CLOCK;
|
||||
}
|
||||
else
|
||||
/* Sync */
|
||||
if (*bootcr & BOOT_PLL_2TO1_MODE)
|
||||
/* 2:1 */
|
||||
switch (clock_id) {
|
||||
case TNETD7200_CLOCK_ID_DSP:
|
||||
return AR7_REF_CLOCK;
|
||||
default:
|
||||
return AR7_AFE_CLOCK;
|
||||
}
|
||||
else
|
||||
/* 1:1 */
|
||||
return AR7_REF_CLOCK;
|
||||
}
|
||||
|
||||
|
||||
static void __init tnetd7200_init_clocks(void)
|
||||
{
|
||||
u32 *bootcr = (u32 *)ioremap(AR7_REGS_DCL, 4);
|
||||
struct tnetd7200_clocks *clocks =
|
||||
ioremap(AR7_REGS_CLOCKS,
|
||||
sizeof(struct tnetd7200_clocks));
|
||||
int cpu_base, cpu_mul, cpu_prediv, cpu_postdiv;
|
||||
int dsp_base, dsp_mul, dsp_prediv, dsp_postdiv;
|
||||
int usb_base, usb_mul, usb_prediv, usb_postdiv;
|
||||
struct clk *clk;
|
||||
|
||||
cpu_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_CPU, bootcr);
|
||||
dsp_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_DSP, bootcr);
|
||||
|
||||
if (*bootcr & BOOT_PLL_ASYNC_MODE) {
|
||||
printk(KERN_INFO "Clocks: Async mode\n");
|
||||
|
||||
printk(KERN_INFO "Clocks: Setting DSP clock\n");
|
||||
calculate(dsp_base, TNETD7200_DEF_DSP_CLK,
|
||||
&dsp_prediv, &dsp_postdiv, &dsp_mul);
|
||||
bus_clk.rate =
|
||||
((dsp_base / dsp_prediv) * dsp_mul) / dsp_postdiv;
|
||||
tnetd7200_set_clock(dsp_base, &clocks->dsp,
|
||||
dsp_prediv, dsp_postdiv * 2, dsp_postdiv, dsp_mul * 2,
|
||||
bus_clk.rate);
|
||||
|
||||
printk(KERN_INFO "Clocks: Setting CPU clock\n");
|
||||
calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv,
|
||||
&cpu_postdiv, &cpu_mul);
|
||||
cpu_clk.rate =
|
||||
((cpu_base / cpu_prediv) * cpu_mul) / cpu_postdiv;
|
||||
tnetd7200_set_clock(cpu_base, &clocks->cpu,
|
||||
cpu_prediv, cpu_postdiv, -1, cpu_mul,
|
||||
cpu_clk.rate);
|
||||
|
||||
} else
|
||||
if (*bootcr & BOOT_PLL_2TO1_MODE) {
|
||||
printk(KERN_INFO "Clocks: Sync 2:1 mode\n");
|
||||
|
||||
printk(KERN_INFO "Clocks: Setting CPU clock\n");
|
||||
calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv,
|
||||
&cpu_postdiv, &cpu_mul);
|
||||
cpu_clk.rate = ((cpu_base / cpu_prediv) * cpu_mul)
|
||||
/ cpu_postdiv;
|
||||
tnetd7200_set_clock(cpu_base, &clocks->cpu,
|
||||
cpu_prediv, cpu_postdiv, -1, cpu_mul,
|
||||
cpu_clk.rate);
|
||||
|
||||
printk(KERN_INFO "Clocks: Setting DSP clock\n");
|
||||
calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv,
|
||||
&dsp_postdiv, &dsp_mul);
|
||||
bus_clk.rate = cpu_clk.rate / 2;
|
||||
tnetd7200_set_clock(dsp_base, &clocks->dsp,
|
||||
dsp_prediv, dsp_postdiv * 2, dsp_postdiv,
|
||||
dsp_mul * 2, bus_clk.rate);
|
||||
} else {
|
||||
printk(KERN_INFO "Clocks: Sync 1:1 mode\n");
|
||||
|
||||
printk(KERN_INFO "Clocks: Setting DSP clock\n");
|
||||
calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv,
|
||||
&dsp_postdiv, &dsp_mul);
|
||||
bus_clk.rate = ((dsp_base / dsp_prediv) * dsp_mul)
|
||||
/ dsp_postdiv;
|
||||
tnetd7200_set_clock(dsp_base, &clocks->dsp,
|
||||
dsp_prediv, dsp_postdiv * 2, dsp_postdiv,
|
||||
dsp_mul * 2, bus_clk.rate);
|
||||
|
||||
cpu_clk.rate = bus_clk.rate;
|
||||
}
|
||||
|
||||
printk(KERN_INFO "Clocks: Setting USB clock\n");
|
||||
usb_base = bus_clk.rate;
|
||||
calculate(usb_base, TNETD7200_DEF_USB_CLK, &usb_prediv,
|
||||
&usb_postdiv, &usb_mul);
|
||||
tnetd7200_set_clock(usb_base, &clocks->usb,
|
||||
usb_prediv, usb_postdiv, -1, usb_mul,
|
||||
TNETD7200_DEF_USB_CLK);
|
||||
|
||||
iounmap(clocks);
|
||||
iounmap(bootcr);
|
||||
|
||||
clk = clk_register_fixed_rate(NULL, "cpu", NULL, 0, cpu_clk.rate);
|
||||
clkdev_create(clk, "cpu", NULL);
|
||||
clkdev_create(clk, "dsp", NULL);
|
||||
}
|
||||
|
||||
void __init ar7_init_clocks(void)
|
||||
{
|
||||
struct clk *clk;
|
||||
|
||||
switch (ar7_chip_id()) {
|
||||
case AR7_CHIP_7100:
|
||||
case AR7_CHIP_7200:
|
||||
tnetd7200_init_clocks();
|
||||
break;
|
||||
case AR7_CHIP_7300:
|
||||
tnetd7300_init_clocks();
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
clk = clk_register_fixed_rate(NULL, "bus", NULL, 0, bus_clk.rate);
|
||||
clkdev_create(clk, "bus", NULL);
|
||||
/* adjust vbus clock rate */
|
||||
clk = clk_register_fixed_factor(NULL, "vbus", "bus", 0, 1, 2);
|
||||
clkdev_create(clk, "vbus", NULL);
|
||||
clkdev_create(clk, "cpmac", "cpmac.1");
|
||||
clkdev_create(clk, "cpmac", "cpmac.1");
|
||||
}
|
||||
@ -1,332 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
|
||||
* Copyright (C) 2007 Eugene Konev <ejka@openwrt.org>
|
||||
* Copyright (C) 2009-2010 Florian Fainelli <florian@openwrt.org>
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/export.h>
|
||||
#include <linux/gpio/driver.h>
|
||||
|
||||
#include <asm/mach-ar7/ar7.h>
|
||||
|
||||
#define AR7_GPIO_MAX 32
|
||||
#define TITAN_GPIO_MAX 51
|
||||
|
||||
struct ar7_gpio_chip {
|
||||
void __iomem *regs;
|
||||
struct gpio_chip chip;
|
||||
};
|
||||
|
||||
static int ar7_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
|
||||
{
|
||||
struct ar7_gpio_chip *gpch = gpiochip_get_data(chip);
|
||||
void __iomem *gpio_in = gpch->regs + AR7_GPIO_INPUT;
|
||||
|
||||
return !!(readl(gpio_in) & (1 << gpio));
|
||||
}
|
||||
|
||||
static int titan_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
|
||||
{
|
||||
struct ar7_gpio_chip *gpch = gpiochip_get_data(chip);
|
||||
void __iomem *gpio_in0 = gpch->regs + TITAN_GPIO_INPUT_0;
|
||||
void __iomem *gpio_in1 = gpch->regs + TITAN_GPIO_INPUT_1;
|
||||
|
||||
return readl(gpio >> 5 ? gpio_in1 : gpio_in0) & (1 << (gpio & 0x1f));
|
||||
}
|
||||
|
||||
static void ar7_gpio_set_value(struct gpio_chip *chip,
|
||||
unsigned gpio, int value)
|
||||
{
|
||||
struct ar7_gpio_chip *gpch = gpiochip_get_data(chip);
|
||||
void __iomem *gpio_out = gpch->regs + AR7_GPIO_OUTPUT;
|
||||
unsigned tmp;
|
||||
|
||||
tmp = readl(gpio_out) & ~(1 << gpio);
|
||||
if (value)
|
||||
tmp |= 1 << gpio;
|
||||
writel(tmp, gpio_out);
|
||||
}
|
||||
|
||||
static void titan_gpio_set_value(struct gpio_chip *chip,
|
||||
unsigned gpio, int value)
|
||||
{
|
||||
struct ar7_gpio_chip *gpch = gpiochip_get_data(chip);
|
||||
void __iomem *gpio_out0 = gpch->regs + TITAN_GPIO_OUTPUT_0;
|
||||
void __iomem *gpio_out1 = gpch->regs + TITAN_GPIO_OUTPUT_1;
|
||||
unsigned tmp;
|
||||
|
||||
tmp = readl(gpio >> 5 ? gpio_out1 : gpio_out0) & ~(1 << (gpio & 0x1f));
|
||||
if (value)
|
||||
tmp |= 1 << (gpio & 0x1f);
|
||||
writel(tmp, gpio >> 5 ? gpio_out1 : gpio_out0);
|
||||
}
|
||||
|
||||
static int ar7_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
|
||||
{
|
||||
struct ar7_gpio_chip *gpch = gpiochip_get_data(chip);
|
||||
void __iomem *gpio_dir = gpch->regs + AR7_GPIO_DIR;
|
||||
|
||||
writel(readl(gpio_dir) | (1 << gpio), gpio_dir);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int titan_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
|
||||
{
|
||||
struct ar7_gpio_chip *gpch = gpiochip_get_data(chip);
|
||||
void __iomem *gpio_dir0 = gpch->regs + TITAN_GPIO_DIR_0;
|
||||
void __iomem *gpio_dir1 = gpch->regs + TITAN_GPIO_DIR_1;
|
||||
|
||||
if (gpio >= TITAN_GPIO_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) | (1 << (gpio & 0x1f)),
|
||||
gpio >> 5 ? gpio_dir1 : gpio_dir0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ar7_gpio_direction_output(struct gpio_chip *chip,
|
||||
unsigned gpio, int value)
|
||||
{
|
||||
struct ar7_gpio_chip *gpch = gpiochip_get_data(chip);
|
||||
void __iomem *gpio_dir = gpch->regs + AR7_GPIO_DIR;
|
||||
|
||||
ar7_gpio_set_value(chip, gpio, value);
|
||||
writel(readl(gpio_dir) & ~(1 << gpio), gpio_dir);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int titan_gpio_direction_output(struct gpio_chip *chip,
|
||||
unsigned gpio, int value)
|
||||
{
|
||||
struct ar7_gpio_chip *gpch = gpiochip_get_data(chip);
|
||||
void __iomem *gpio_dir0 = gpch->regs + TITAN_GPIO_DIR_0;
|
||||
void __iomem *gpio_dir1 = gpch->regs + TITAN_GPIO_DIR_1;
|
||||
|
||||
if (gpio >= TITAN_GPIO_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
titan_gpio_set_value(chip, gpio, value);
|
||||
writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) & ~(1 <<
|
||||
(gpio & 0x1f)), gpio >> 5 ? gpio_dir1 : gpio_dir0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct ar7_gpio_chip ar7_gpio_chip = {
|
||||
.chip = {
|
||||
.label = "ar7-gpio",
|
||||
.direction_input = ar7_gpio_direction_input,
|
||||
.direction_output = ar7_gpio_direction_output,
|
||||
.set = ar7_gpio_set_value,
|
||||
.get = ar7_gpio_get_value,
|
||||
.base = 0,
|
||||
.ngpio = AR7_GPIO_MAX,
|
||||
}
|
||||
};
|
||||
|
||||
static struct ar7_gpio_chip titan_gpio_chip = {
|
||||
.chip = {
|
||||
.label = "titan-gpio",
|
||||
.direction_input = titan_gpio_direction_input,
|
||||
.direction_output = titan_gpio_direction_output,
|
||||
.set = titan_gpio_set_value,
|
||||
.get = titan_gpio_get_value,
|
||||
.base = 0,
|
||||
.ngpio = TITAN_GPIO_MAX,
|
||||
}
|
||||
};
|
||||
|
||||
static inline int ar7_gpio_enable_ar7(unsigned gpio)
|
||||
{
|
||||
void __iomem *gpio_en = ar7_gpio_chip.regs + AR7_GPIO_ENABLE;
|
||||
|
||||
writel(readl(gpio_en) | (1 << gpio), gpio_en);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int ar7_gpio_enable_titan(unsigned gpio)
|
||||
{
|
||||
void __iomem *gpio_en0 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_0;
|
||||
void __iomem *gpio_en1 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_1;
|
||||
|
||||
writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) | (1 << (gpio & 0x1f)),
|
||||
gpio >> 5 ? gpio_en1 : gpio_en0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ar7_gpio_enable(unsigned gpio)
|
||||
{
|
||||
return ar7_is_titan() ? ar7_gpio_enable_titan(gpio) :
|
||||
ar7_gpio_enable_ar7(gpio);
|
||||
}
|
||||
EXPORT_SYMBOL(ar7_gpio_enable);
|
||||
|
||||
static inline int ar7_gpio_disable_ar7(unsigned gpio)
|
||||
{
|
||||
void __iomem *gpio_en = ar7_gpio_chip.regs + AR7_GPIO_ENABLE;
|
||||
|
||||
writel(readl(gpio_en) & ~(1 << gpio), gpio_en);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int ar7_gpio_disable_titan(unsigned gpio)
|
||||
{
|
||||
void __iomem *gpio_en0 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_0;
|
||||
void __iomem *gpio_en1 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_1;
|
||||
|
||||
writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) & ~(1 << (gpio & 0x1f)),
|
||||
gpio >> 5 ? gpio_en1 : gpio_en0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ar7_gpio_disable(unsigned gpio)
|
||||
{
|
||||
return ar7_is_titan() ? ar7_gpio_disable_titan(gpio) :
|
||||
ar7_gpio_disable_ar7(gpio);
|
||||
}
|
||||
EXPORT_SYMBOL(ar7_gpio_disable);
|
||||
|
||||
struct titan_gpio_cfg {
|
||||
u32 reg;
|
||||
u32 shift;
|
||||
u32 func;
|
||||
};
|
||||
|
||||
static const struct titan_gpio_cfg titan_gpio_table[] = {
|
||||
/* reg, start bit, mux value */
|
||||
{4, 24, 1},
|
||||
{4, 26, 1},
|
||||
{4, 28, 1},
|
||||
{4, 30, 1},
|
||||
{5, 6, 1},
|
||||
{5, 8, 1},
|
||||
{5, 10, 1},
|
||||
{5, 12, 1},
|
||||
{7, 14, 3},
|
||||
{7, 16, 3},
|
||||
{7, 18, 3},
|
||||
{7, 20, 3},
|
||||
{7, 22, 3},
|
||||
{7, 26, 3},
|
||||
{7, 28, 3},
|
||||
{7, 30, 3},
|
||||
{8, 0, 3},
|
||||
{8, 2, 3},
|
||||
{8, 4, 3},
|
||||
{8, 10, 3},
|
||||
{8, 14, 3},
|
||||
{8, 16, 3},
|
||||
{8, 18, 3},
|
||||
{8, 20, 3},
|
||||
{9, 8, 3},
|
||||
{9, 10, 3},
|
||||
{9, 12, 3},
|
||||
{9, 14, 3},
|
||||
{9, 18, 3},
|
||||
{9, 20, 3},
|
||||
{9, 24, 3},
|
||||
{9, 26, 3},
|
||||
{9, 28, 3},
|
||||
{9, 30, 3},
|
||||
{10, 0, 3},
|
||||
{10, 2, 3},
|
||||
{10, 8, 3},
|
||||
{10, 10, 3},
|
||||
{10, 12, 3},
|
||||
{10, 14, 3},
|
||||
{13, 12, 3},
|
||||
{13, 14, 3},
|
||||
{13, 16, 3},
|
||||
{13, 18, 3},
|
||||
{13, 24, 3},
|
||||
{13, 26, 3},
|
||||
{13, 28, 3},
|
||||
{13, 30, 3},
|
||||
{14, 2, 3},
|
||||
{14, 6, 3},
|
||||
{14, 8, 3},
|
||||
{14, 12, 3}
|
||||
};
|
||||
|
||||
static int titan_gpio_pinsel(unsigned gpio)
|
||||
{
|
||||
struct titan_gpio_cfg gpio_cfg;
|
||||
u32 mux_status, pin_sel_reg, tmp;
|
||||
void __iomem *pin_sel = (void __iomem *)KSEG1ADDR(AR7_REGS_PINSEL);
|
||||
|
||||
if (gpio >= ARRAY_SIZE(titan_gpio_table))
|
||||
return -EINVAL;
|
||||
|
||||
gpio_cfg = titan_gpio_table[gpio];
|
||||
pin_sel_reg = gpio_cfg.reg - 1;
|
||||
|
||||
mux_status = (readl(pin_sel + pin_sel_reg) >> gpio_cfg.shift) & 0x3;
|
||||
|
||||
/* Check the mux status */
|
||||
if (!((mux_status == 0) || (mux_status == gpio_cfg.func)))
|
||||
return 0;
|
||||
|
||||
/* Set the pin sel value */
|
||||
tmp = readl(pin_sel + pin_sel_reg);
|
||||
tmp |= ((gpio_cfg.func & 0x3) << gpio_cfg.shift);
|
||||
writel(tmp, pin_sel + pin_sel_reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Perform minimal Titan GPIO configuration */
|
||||
static void titan_gpio_init(void)
|
||||
{
|
||||
unsigned i;
|
||||
|
||||
for (i = 44; i < 48; i++) {
|
||||
titan_gpio_pinsel(i);
|
||||
ar7_gpio_enable_titan(i);
|
||||
titan_gpio_direction_input(&titan_gpio_chip.chip, i);
|
||||
}
|
||||
}
|
||||
|
||||
int __init ar7_gpio_init(void)
|
||||
{
|
||||
int ret;
|
||||
struct ar7_gpio_chip *gpch;
|
||||
unsigned size;
|
||||
|
||||
if (!ar7_is_titan()) {
|
||||
gpch = &ar7_gpio_chip;
|
||||
size = 0x10;
|
||||
} else {
|
||||
gpch = &titan_gpio_chip;
|
||||
size = 0x1f;
|
||||
}
|
||||
|
||||
gpch->regs = ioremap(AR7_REGS_GPIO, size);
|
||||
if (!gpch->regs) {
|
||||
printk(KERN_ERR "%s: failed to ioremap regs\n",
|
||||
gpch->chip.label);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
ret = gpiochip_add_data(&gpch->chip, gpch);
|
||||
if (ret) {
|
||||
printk(KERN_ERR "%s: failed to add gpiochip\n",
|
||||
gpch->chip.label);
|
||||
iounmap(gpch->regs);
|
||||
return ret;
|
||||
}
|
||||
printk(KERN_INFO "%s: registered %d GPIOs\n",
|
||||
gpch->chip.label, gpch->chip.ngpio);
|
||||
|
||||
if (ar7_is_titan())
|
||||
titan_gpio_init();
|
||||
|
||||
return ret;
|
||||
}
|
||||
@ -1,165 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org>
|
||||
* Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org>
|
||||
*/
|
||||
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
|
||||
#include <asm/irq_cpu.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/mach-ar7/ar7.h>
|
||||
|
||||
#define EXCEPT_OFFSET 0x80
|
||||
#define PACE_OFFSET 0xA0
|
||||
#define CHNLS_OFFSET 0x200
|
||||
|
||||
#define REG_OFFSET(irq, reg) ((irq) / 32 * 0x4 + reg * 0x10)
|
||||
#define SEC_REG_OFFSET(reg) (EXCEPT_OFFSET + reg * 0x8)
|
||||
#define SEC_SR_OFFSET (SEC_REG_OFFSET(0)) /* 0x80 */
|
||||
#define CR_OFFSET(irq) (REG_OFFSET(irq, 1)) /* 0x10 */
|
||||
#define SEC_CR_OFFSET (SEC_REG_OFFSET(1)) /* 0x88 */
|
||||
#define ESR_OFFSET(irq) (REG_OFFSET(irq, 2)) /* 0x20 */
|
||||
#define SEC_ESR_OFFSET (SEC_REG_OFFSET(2)) /* 0x90 */
|
||||
#define ECR_OFFSET(irq) (REG_OFFSET(irq, 3)) /* 0x30 */
|
||||
#define SEC_ECR_OFFSET (SEC_REG_OFFSET(3)) /* 0x98 */
|
||||
#define PIR_OFFSET (0x40)
|
||||
#define MSR_OFFSET (0x44)
|
||||
#define PM_OFFSET(irq) (REG_OFFSET(irq, 5)) /* 0x50 */
|
||||
#define TM_OFFSET(irq) (REG_OFFSET(irq, 6)) /* 0x60 */
|
||||
|
||||
#define REG(addr) ((u32 *)(KSEG1ADDR(AR7_REGS_IRQ) + addr))
|
||||
|
||||
#define CHNL_OFFSET(chnl) (CHNLS_OFFSET + (chnl * 4))
|
||||
|
||||
static int ar7_irq_base;
|
||||
|
||||
static void ar7_unmask_irq(struct irq_data *d)
|
||||
{
|
||||
writel(1 << ((d->irq - ar7_irq_base) % 32),
|
||||
REG(ESR_OFFSET(d->irq - ar7_irq_base)));
|
||||
}
|
||||
|
||||
static void ar7_mask_irq(struct irq_data *d)
|
||||
{
|
||||
writel(1 << ((d->irq - ar7_irq_base) % 32),
|
||||
REG(ECR_OFFSET(d->irq - ar7_irq_base)));
|
||||
}
|
||||
|
||||
static void ar7_ack_irq(struct irq_data *d)
|
||||
{
|
||||
writel(1 << ((d->irq - ar7_irq_base) % 32),
|
||||
REG(CR_OFFSET(d->irq - ar7_irq_base)));
|
||||
}
|
||||
|
||||
static void ar7_unmask_sec_irq(struct irq_data *d)
|
||||
{
|
||||
writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET));
|
||||
}
|
||||
|
||||
static void ar7_mask_sec_irq(struct irq_data *d)
|
||||
{
|
||||
writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET));
|
||||
}
|
||||
|
||||
static void ar7_ack_sec_irq(struct irq_data *d)
|
||||
{
|
||||
writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET));
|
||||
}
|
||||
|
||||
static struct irq_chip ar7_irq_type = {
|
||||
.name = "AR7",
|
||||
.irq_unmask = ar7_unmask_irq,
|
||||
.irq_mask = ar7_mask_irq,
|
||||
.irq_ack = ar7_ack_irq
|
||||
};
|
||||
|
||||
static struct irq_chip ar7_sec_irq_type = {
|
||||
.name = "AR7",
|
||||
.irq_unmask = ar7_unmask_sec_irq,
|
||||
.irq_mask = ar7_mask_sec_irq,
|
||||
.irq_ack = ar7_ack_sec_irq,
|
||||
};
|
||||
|
||||
static void __init ar7_irq_init(int base)
|
||||
{
|
||||
int i;
|
||||
/*
|
||||
* Disable interrupts and clear pending
|
||||
*/
|
||||
writel(0xffffffff, REG(ECR_OFFSET(0)));
|
||||
writel(0xff, REG(ECR_OFFSET(32)));
|
||||
writel(0xffffffff, REG(SEC_ECR_OFFSET));
|
||||
writel(0xffffffff, REG(CR_OFFSET(0)));
|
||||
writel(0xff, REG(CR_OFFSET(32)));
|
||||
writel(0xffffffff, REG(SEC_CR_OFFSET));
|
||||
|
||||
ar7_irq_base = base;
|
||||
|
||||
for (i = 0; i < 40; i++) {
|
||||
writel(i, REG(CHNL_OFFSET(i)));
|
||||
/* Primary IRQ's */
|
||||
irq_set_chip_and_handler(base + i, &ar7_irq_type,
|
||||
handle_level_irq);
|
||||
/* Secondary IRQ's */
|
||||
if (i < 32)
|
||||
irq_set_chip_and_handler(base + i + 40,
|
||||
&ar7_sec_irq_type,
|
||||
handle_level_irq);
|
||||
}
|
||||
|
||||
if (request_irq(2, no_action, IRQF_NO_THREAD, "AR7 cascade interrupt",
|
||||
NULL))
|
||||
pr_err("Failed to request irq 2 (AR7 cascade interrupt)\n");
|
||||
if (request_irq(ar7_irq_base, no_action, IRQF_NO_THREAD,
|
||||
"AR7 cascade interrupt", NULL)) {
|
||||
pr_err("Failed to request irq %d (AR7 cascade interrupt)\n",
|
||||
ar7_irq_base);
|
||||
}
|
||||
set_c0_status(IE_IRQ0);
|
||||
}
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
{
|
||||
mips_cpu_irq_init();
|
||||
ar7_irq_init(8);
|
||||
}
|
||||
|
||||
static void ar7_cascade(void)
|
||||
{
|
||||
u32 status;
|
||||
int i, irq;
|
||||
|
||||
/* Primary IRQ's */
|
||||
irq = readl(REG(PIR_OFFSET)) & 0x3f;
|
||||
if (irq) {
|
||||
do_IRQ(ar7_irq_base + irq);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Secondary IRQ's are cascaded through primary '0' */
|
||||
writel(1, REG(CR_OFFSET(irq)));
|
||||
status = readl(REG(SEC_SR_OFFSET));
|
||||
for (i = 0; i < 32; i++) {
|
||||
if (status & 1) {
|
||||
do_IRQ(ar7_irq_base + i + 40);
|
||||
return;
|
||||
}
|
||||
status >>= 1;
|
||||
}
|
||||
|
||||
spurious_interrupt();
|
||||
}
|
||||
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
|
||||
if (pending & STATUSF_IP7) /* cpu timer */
|
||||
do_IRQ(7);
|
||||
else if (pending & STATUSF_IP2) /* int0 hardware line */
|
||||
ar7_cascade();
|
||||
else
|
||||
spurious_interrupt();
|
||||
}
|
||||
@ -1,51 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
|
||||
* Copyright (C) 2007 Eugene Konev <ejka@openwrt.org>
|
||||
*/
|
||||
#include <linux/memblock.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/pfn.h>
|
||||
#include <linux/proc_fs.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/swap.h>
|
||||
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/sections.h>
|
||||
|
||||
#include <asm/mach-ar7/ar7.h>
|
||||
|
||||
static int __init memsize(void)
|
||||
{
|
||||
u32 size = (64 << 20);
|
||||
u32 *addr = (u32 *)KSEG1ADDR(AR7_SDRAM_BASE + size - 4);
|
||||
u32 *kernel_end = (u32 *)KSEG1ADDR(CPHYSADDR((u32)&_end));
|
||||
u32 *tmpaddr = addr;
|
||||
|
||||
while (tmpaddr > kernel_end) {
|
||||
*tmpaddr = (u32)tmpaddr;
|
||||
size >>= 1;
|
||||
tmpaddr -= size >> 2;
|
||||
}
|
||||
|
||||
do {
|
||||
tmpaddr += size >> 2;
|
||||
if (*tmpaddr != (u32)tmpaddr)
|
||||
break;
|
||||
size <<= 1;
|
||||
} while (size < (64 << 20));
|
||||
|
||||
writel((u32)tmpaddr, &addr);
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
void __init prom_meminit(void)
|
||||
{
|
||||
unsigned long pages;
|
||||
|
||||
pages = memsize() >> PAGE_SHIFT;
|
||||
memblock_add(PHYS_OFFSET, pages << PAGE_SHIFT);
|
||||
}
|
||||
@ -1,722 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org>
|
||||
* Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org>
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/mtd/physmap.h>
|
||||
#include <linux/serial.h>
|
||||
#include <linux/serial_8250.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/vlynq.h>
|
||||
#include <linux/leds.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/etherdevice.h>
|
||||
#include <linux/phy.h>
|
||||
#include <linux/phy_fixed.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/clk.h>
|
||||
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/mach-ar7/ar7.h>
|
||||
#include <asm/mach-ar7/prom.h>
|
||||
|
||||
/*****************************************************************************
|
||||
* VLYNQ Bus
|
||||
****************************************************************************/
|
||||
struct plat_vlynq_data {
|
||||
struct plat_vlynq_ops ops;
|
||||
int gpio_bit;
|
||||
int reset_bit;
|
||||
};
|
||||
|
||||
static int vlynq_on(struct vlynq_device *dev)
|
||||
{
|
||||
int ret;
|
||||
struct plat_vlynq_data *pdata = dev->dev.platform_data;
|
||||
|
||||
ret = gpio_request(pdata->gpio_bit, "vlynq");
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
ar7_device_reset(pdata->reset_bit);
|
||||
|
||||
ret = ar7_gpio_disable(pdata->gpio_bit);
|
||||
if (ret)
|
||||
goto out_enabled;
|
||||
|
||||
ret = ar7_gpio_enable(pdata->gpio_bit);
|
||||
if (ret)
|
||||
goto out_enabled;
|
||||
|
||||
ret = gpio_direction_output(pdata->gpio_bit, 0);
|
||||
if (ret)
|
||||
goto out_gpio_enabled;
|
||||
|
||||
msleep(50);
|
||||
|
||||
gpio_set_value(pdata->gpio_bit, 1);
|
||||
|
||||
msleep(50);
|
||||
|
||||
return 0;
|
||||
|
||||
out_gpio_enabled:
|
||||
ar7_gpio_disable(pdata->gpio_bit);
|
||||
out_enabled:
|
||||
ar7_device_disable(pdata->reset_bit);
|
||||
gpio_free(pdata->gpio_bit);
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void vlynq_off(struct vlynq_device *dev)
|
||||
{
|
||||
struct plat_vlynq_data *pdata = dev->dev.platform_data;
|
||||
|
||||
ar7_gpio_disable(pdata->gpio_bit);
|
||||
gpio_free(pdata->gpio_bit);
|
||||
ar7_device_disable(pdata->reset_bit);
|
||||
}
|
||||
|
||||
static struct resource vlynq_low_res[] = {
|
||||
{
|
||||
.name = "regs",
|
||||
.flags = IORESOURCE_MEM,
|
||||
.start = AR7_REGS_VLYNQ0,
|
||||
.end = AR7_REGS_VLYNQ0 + 0xff,
|
||||
},
|
||||
{
|
||||
.name = "irq",
|
||||
.flags = IORESOURCE_IRQ,
|
||||
.start = 29,
|
||||
.end = 29,
|
||||
},
|
||||
{
|
||||
.name = "mem",
|
||||
.flags = IORESOURCE_MEM,
|
||||
.start = 0x04000000,
|
||||
.end = 0x04ffffff,
|
||||
},
|
||||
{
|
||||
.name = "devirq",
|
||||
.flags = IORESOURCE_IRQ,
|
||||
.start = 80,
|
||||
.end = 111,
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource vlynq_high_res[] = {
|
||||
{
|
||||
.name = "regs",
|
||||
.flags = IORESOURCE_MEM,
|
||||
.start = AR7_REGS_VLYNQ1,
|
||||
.end = AR7_REGS_VLYNQ1 + 0xff,
|
||||
},
|
||||
{
|
||||
.name = "irq",
|
||||
.flags = IORESOURCE_IRQ,
|
||||
.start = 33,
|
||||
.end = 33,
|
||||
},
|
||||
{
|
||||
.name = "mem",
|
||||
.flags = IORESOURCE_MEM,
|
||||
.start = 0x0c000000,
|
||||
.end = 0x0cffffff,
|
||||
},
|
||||
{
|
||||
.name = "devirq",
|
||||
.flags = IORESOURCE_IRQ,
|
||||
.start = 112,
|
||||
.end = 143,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_vlynq_data vlynq_low_data = {
|
||||
.ops = {
|
||||
.on = vlynq_on,
|
||||
.off = vlynq_off,
|
||||
},
|
||||
.reset_bit = 20,
|
||||
.gpio_bit = 18,
|
||||
};
|
||||
|
||||
static struct plat_vlynq_data vlynq_high_data = {
|
||||
.ops = {
|
||||
.on = vlynq_on,
|
||||
.off = vlynq_off,
|
||||
},
|
||||
.reset_bit = 16,
|
||||
.gpio_bit = 19,
|
||||
};
|
||||
|
||||
static struct platform_device vlynq_low = {
|
||||
.id = 0,
|
||||
.name = "vlynq",
|
||||
.dev = {
|
||||
.platform_data = &vlynq_low_data,
|
||||
},
|
||||
.resource = vlynq_low_res,
|
||||
.num_resources = ARRAY_SIZE(vlynq_low_res),
|
||||
};
|
||||
|
||||
static struct platform_device vlynq_high = {
|
||||
.id = 1,
|
||||
.name = "vlynq",
|
||||
.dev = {
|
||||
.platform_data = &vlynq_high_data,
|
||||
},
|
||||
.resource = vlynq_high_res,
|
||||
.num_resources = ARRAY_SIZE(vlynq_high_res),
|
||||
};
|
||||
|
||||
/*****************************************************************************
|
||||
* Flash
|
||||
****************************************************************************/
|
||||
static struct resource physmap_flash_resource = {
|
||||
.name = "mem",
|
||||
.flags = IORESOURCE_MEM,
|
||||
.start = 0x10000000,
|
||||
.end = 0x107fffff,
|
||||
};
|
||||
|
||||
static const char *ar7_probe_types[] = { "ar7part", NULL };
|
||||
|
||||
static struct physmap_flash_data physmap_flash_data = {
|
||||
.width = 2,
|
||||
.part_probe_types = ar7_probe_types,
|
||||
};
|
||||
|
||||
static struct platform_device physmap_flash = {
|
||||
.name = "physmap-flash",
|
||||
.dev = {
|
||||
.platform_data = &physmap_flash_data,
|
||||
},
|
||||
.resource = &physmap_flash_resource,
|
||||
.num_resources = 1,
|
||||
};
|
||||
|
||||
/*****************************************************************************
|
||||
* Ethernet
|
||||
****************************************************************************/
|
||||
static struct resource cpmac_low_res[] = {
|
||||
{
|
||||
.name = "regs",
|
||||
.flags = IORESOURCE_MEM,
|
||||
.start = AR7_REGS_MAC0,
|
||||
.end = AR7_REGS_MAC0 + 0x7ff,
|
||||
},
|
||||
{
|
||||
.name = "irq",
|
||||
.flags = IORESOURCE_IRQ,
|
||||
.start = 27,
|
||||
.end = 27,
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource cpmac_high_res[] = {
|
||||
{
|
||||
.name = "regs",
|
||||
.flags = IORESOURCE_MEM,
|
||||
.start = AR7_REGS_MAC1,
|
||||
.end = AR7_REGS_MAC1 + 0x7ff,
|
||||
},
|
||||
{
|
||||
.name = "irq",
|
||||
.flags = IORESOURCE_IRQ,
|
||||
.start = 41,
|
||||
.end = 41,
|
||||
},
|
||||
};
|
||||
|
||||
static struct fixed_phy_status fixed_phy_status __initdata = {
|
||||
.link = 1,
|
||||
.speed = 100,
|
||||
.duplex = 1,
|
||||
};
|
||||
|
||||
static struct plat_cpmac_data cpmac_low_data = {
|
||||
.reset_bit = 17,
|
||||
.power_bit = 20,
|
||||
.phy_mask = 0x80000000,
|
||||
};
|
||||
|
||||
static struct plat_cpmac_data cpmac_high_data = {
|
||||
.reset_bit = 21,
|
||||
.power_bit = 22,
|
||||
.phy_mask = 0x7fffffff,
|
||||
};
|
||||
|
||||
static u64 cpmac_dma_mask = DMA_BIT_MASK(32);
|
||||
|
||||
static struct platform_device cpmac_low = {
|
||||
.id = 0,
|
||||
.name = "cpmac",
|
||||
.dev = {
|
||||
.dma_mask = &cpmac_dma_mask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
.platform_data = &cpmac_low_data,
|
||||
},
|
||||
.resource = cpmac_low_res,
|
||||
.num_resources = ARRAY_SIZE(cpmac_low_res),
|
||||
};
|
||||
|
||||
static struct platform_device cpmac_high = {
|
||||
.id = 1,
|
||||
.name = "cpmac",
|
||||
.dev = {
|
||||
.dma_mask = &cpmac_dma_mask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
.platform_data = &cpmac_high_data,
|
||||
},
|
||||
.resource = cpmac_high_res,
|
||||
.num_resources = ARRAY_SIZE(cpmac_high_res),
|
||||
};
|
||||
|
||||
static void __init cpmac_get_mac(int instance, unsigned char *dev_addr)
|
||||
{
|
||||
char name[5], *mac;
|
||||
|
||||
sprintf(name, "mac%c", 'a' + instance);
|
||||
mac = prom_getenv(name);
|
||||
if (!mac && instance) {
|
||||
sprintf(name, "mac%c", 'a');
|
||||
mac = prom_getenv(name);
|
||||
}
|
||||
|
||||
if (mac) {
|
||||
if (!mac_pton(mac, dev_addr)) {
|
||||
pr_warn("cannot parse mac address, using random address\n");
|
||||
eth_random_addr(dev_addr);
|
||||
}
|
||||
} else
|
||||
eth_random_addr(dev_addr);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* USB
|
||||
****************************************************************************/
|
||||
static struct resource usb_res[] = {
|
||||
{
|
||||
.name = "regs",
|
||||
.flags = IORESOURCE_MEM,
|
||||
.start = AR7_REGS_USB,
|
||||
.end = AR7_REGS_USB + 0xff,
|
||||
},
|
||||
{
|
||||
.name = "irq",
|
||||
.flags = IORESOURCE_IRQ,
|
||||
.start = 32,
|
||||
.end = 32,
|
||||
},
|
||||
{
|
||||
.name = "mem",
|
||||
.flags = IORESOURCE_MEM,
|
||||
.start = 0x03400000,
|
||||
.end = 0x03401fff,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device ar7_udc = {
|
||||
.name = "ar7_udc",
|
||||
.resource = usb_res,
|
||||
.num_resources = ARRAY_SIZE(usb_res),
|
||||
};
|
||||
|
||||
/*****************************************************************************
|
||||
* LEDs
|
||||
****************************************************************************/
|
||||
static const struct gpio_led default_leds[] = {
|
||||
{
|
||||
.name = "status",
|
||||
.gpio = 8,
|
||||
.active_low = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct gpio_led titan_leds[] = {
|
||||
{ .name = "status", .gpio = 8, .active_low = 1, },
|
||||
{ .name = "wifi", .gpio = 13, .active_low = 1, },
|
||||
};
|
||||
|
||||
static const struct gpio_led dsl502t_leds[] = {
|
||||
{
|
||||
.name = "status",
|
||||
.gpio = 9,
|
||||
.active_low = 1,
|
||||
},
|
||||
{
|
||||
.name = "ethernet",
|
||||
.gpio = 7,
|
||||
.active_low = 1,
|
||||
},
|
||||
{
|
||||
.name = "usb",
|
||||
.gpio = 12,
|
||||
.active_low = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct gpio_led dg834g_leds[] = {
|
||||
{
|
||||
.name = "ppp",
|
||||
.gpio = 6,
|
||||
.active_low = 1,
|
||||
},
|
||||
{
|
||||
.name = "status",
|
||||
.gpio = 7,
|
||||
.active_low = 1,
|
||||
},
|
||||
{
|
||||
.name = "adsl",
|
||||
.gpio = 8,
|
||||
.active_low = 1,
|
||||
},
|
||||
{
|
||||
.name = "wifi",
|
||||
.gpio = 12,
|
||||
.active_low = 1,
|
||||
},
|
||||
{
|
||||
.name = "power",
|
||||
.gpio = 14,
|
||||
.active_low = 1,
|
||||
.default_trigger = "default-on",
|
||||
},
|
||||
};
|
||||
|
||||
static const struct gpio_led fb_sl_leds[] = {
|
||||
{
|
||||
.name = "1",
|
||||
.gpio = 7,
|
||||
},
|
||||
{
|
||||
.name = "2",
|
||||
.gpio = 13,
|
||||
.active_low = 1,
|
||||
},
|
||||
{
|
||||
.name = "3",
|
||||
.gpio = 10,
|
||||
.active_low = 1,
|
||||
},
|
||||
{
|
||||
.name = "4",
|
||||
.gpio = 12,
|
||||
.active_low = 1,
|
||||
},
|
||||
{
|
||||
.name = "5",
|
||||
.gpio = 9,
|
||||
.active_low = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct gpio_led fb_fon_leds[] = {
|
||||
{
|
||||
.name = "1",
|
||||
.gpio = 8,
|
||||
},
|
||||
{
|
||||
.name = "2",
|
||||
.gpio = 3,
|
||||
.active_low = 1,
|
||||
},
|
||||
{
|
||||
.name = "3",
|
||||
.gpio = 5,
|
||||
},
|
||||
{
|
||||
.name = "4",
|
||||
.gpio = 4,
|
||||
.active_low = 1,
|
||||
},
|
||||
{
|
||||
.name = "5",
|
||||
.gpio = 11,
|
||||
.active_low = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct gpio_led gt701_leds[] = {
|
||||
{
|
||||
.name = "inet:green",
|
||||
.gpio = 13,
|
||||
.active_low = 1,
|
||||
},
|
||||
{
|
||||
.name = "usb",
|
||||
.gpio = 12,
|
||||
.active_low = 1,
|
||||
},
|
||||
{
|
||||
.name = "inet:red",
|
||||
.gpio = 9,
|
||||
.active_low = 1,
|
||||
},
|
||||
{
|
||||
.name = "power:red",
|
||||
.gpio = 7,
|
||||
.active_low = 1,
|
||||
},
|
||||
{
|
||||
.name = "power:green",
|
||||
.gpio = 8,
|
||||
.active_low = 1,
|
||||
.default_trigger = "default-on",
|
||||
},
|
||||
{
|
||||
.name = "ethernet",
|
||||
.gpio = 10,
|
||||
.active_low = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct gpio_led_platform_data ar7_led_data;
|
||||
|
||||
static struct platform_device ar7_gpio_leds = {
|
||||
.name = "leds-gpio",
|
||||
.dev = {
|
||||
.platform_data = &ar7_led_data,
|
||||
}
|
||||
};
|
||||
|
||||
static void __init detect_leds(void)
|
||||
{
|
||||
char *prid, *usb_prod;
|
||||
|
||||
/* Default LEDs */
|
||||
ar7_led_data.num_leds = ARRAY_SIZE(default_leds);
|
||||
ar7_led_data.leds = default_leds;
|
||||
|
||||
/* FIXME: the whole thing is unreliable */
|
||||
prid = prom_getenv("ProductID");
|
||||
usb_prod = prom_getenv("usb_prod");
|
||||
|
||||
/* If we can't get the product id from PROM, use the default LEDs */
|
||||
if (!prid)
|
||||
return;
|
||||
|
||||
if (strstr(prid, "Fritz_Box_FON")) {
|
||||
ar7_led_data.num_leds = ARRAY_SIZE(fb_fon_leds);
|
||||
ar7_led_data.leds = fb_fon_leds;
|
||||
} else if (strstr(prid, "Fritz_Box_")) {
|
||||
ar7_led_data.num_leds = ARRAY_SIZE(fb_sl_leds);
|
||||
ar7_led_data.leds = fb_sl_leds;
|
||||
} else if ((!strcmp(prid, "AR7RD") || !strcmp(prid, "AR7DB"))
|
||||
&& usb_prod != NULL && strstr(usb_prod, "DSL-502T")) {
|
||||
ar7_led_data.num_leds = ARRAY_SIZE(dsl502t_leds);
|
||||
ar7_led_data.leds = dsl502t_leds;
|
||||
} else if (strstr(prid, "DG834")) {
|
||||
ar7_led_data.num_leds = ARRAY_SIZE(dg834g_leds);
|
||||
ar7_led_data.leds = dg834g_leds;
|
||||
} else if (strstr(prid, "CYWM") || strstr(prid, "CYWL")) {
|
||||
ar7_led_data.num_leds = ARRAY_SIZE(titan_leds);
|
||||
ar7_led_data.leds = titan_leds;
|
||||
} else if (strstr(prid, "GT701")) {
|
||||
ar7_led_data.num_leds = ARRAY_SIZE(gt701_leds);
|
||||
ar7_led_data.leds = gt701_leds;
|
||||
}
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Watchdog
|
||||
****************************************************************************/
|
||||
static struct resource ar7_wdt_res = {
|
||||
.name = "regs",
|
||||
.flags = IORESOURCE_MEM,
|
||||
.start = -1, /* Filled at runtime */
|
||||
.end = -1, /* Filled at runtime */
|
||||
};
|
||||
|
||||
static struct platform_device ar7_wdt = {
|
||||
.name = "ar7_wdt",
|
||||
.resource = &ar7_wdt_res,
|
||||
.num_resources = 1,
|
||||
};
|
||||
|
||||
/*****************************************************************************
|
||||
* Init
|
||||
****************************************************************************/
|
||||
static int __init ar7_register_uarts(void)
|
||||
{
|
||||
#ifdef CONFIG_SERIAL_8250
|
||||
static struct uart_port uart_port __initdata;
|
||||
struct clk *bus_clk;
|
||||
int res;
|
||||
|
||||
memset(&uart_port, 0, sizeof(struct uart_port));
|
||||
|
||||
bus_clk = clk_get(NULL, "bus");
|
||||
if (IS_ERR(bus_clk))
|
||||
panic("unable to get bus clk");
|
||||
|
||||
uart_port.type = PORT_AR7;
|
||||
uart_port.uartclk = clk_get_rate(bus_clk) / 2;
|
||||
uart_port.iotype = UPIO_MEM32;
|
||||
uart_port.flags = UPF_FIXED_TYPE | UPF_BOOT_AUTOCONF;
|
||||
uart_port.regshift = 2;
|
||||
|
||||
uart_port.line = 0;
|
||||
uart_port.irq = AR7_IRQ_UART0;
|
||||
uart_port.mapbase = AR7_REGS_UART0;
|
||||
uart_port.membase = ioremap(uart_port.mapbase, 256);
|
||||
|
||||
res = early_serial_setup(&uart_port);
|
||||
if (res)
|
||||
return res;
|
||||
|
||||
/* Only TNETD73xx have a second serial port */
|
||||
if (ar7_has_second_uart()) {
|
||||
uart_port.line = 1;
|
||||
uart_port.irq = AR7_IRQ_UART1;
|
||||
uart_port.mapbase = UR8_REGS_UART1;
|
||||
uart_port.membase = ioremap(uart_port.mapbase, 256);
|
||||
|
||||
res = early_serial_setup(&uart_port);
|
||||
if (res)
|
||||
return res;
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __init titan_fixup_devices(void)
|
||||
{
|
||||
/* Set vlynq0 data */
|
||||
vlynq_low_data.reset_bit = 15;
|
||||
vlynq_low_data.gpio_bit = 14;
|
||||
|
||||
/* Set vlynq1 data */
|
||||
vlynq_high_data.reset_bit = 16;
|
||||
vlynq_high_data.gpio_bit = 7;
|
||||
|
||||
/* Set vlynq0 resources */
|
||||
vlynq_low_res[0].start = TITAN_REGS_VLYNQ0;
|
||||
vlynq_low_res[0].end = TITAN_REGS_VLYNQ0 + 0xff;
|
||||
vlynq_low_res[1].start = 33;
|
||||
vlynq_low_res[1].end = 33;
|
||||
vlynq_low_res[2].start = 0x0c000000;
|
||||
vlynq_low_res[2].end = 0x0fffffff;
|
||||
vlynq_low_res[3].start = 80;
|
||||
vlynq_low_res[3].end = 111;
|
||||
|
||||
/* Set vlynq1 resources */
|
||||
vlynq_high_res[0].start = TITAN_REGS_VLYNQ1;
|
||||
vlynq_high_res[0].end = TITAN_REGS_VLYNQ1 + 0xff;
|
||||
vlynq_high_res[1].start = 34;
|
||||
vlynq_high_res[1].end = 34;
|
||||
vlynq_high_res[2].start = 0x40000000;
|
||||
vlynq_high_res[2].end = 0x43ffffff;
|
||||
vlynq_high_res[3].start = 112;
|
||||
vlynq_high_res[3].end = 143;
|
||||
|
||||
/* Set cpmac0 data */
|
||||
cpmac_low_data.phy_mask = 0x40000000;
|
||||
|
||||
/* Set cpmac1 data */
|
||||
cpmac_high_data.phy_mask = 0x80000000;
|
||||
|
||||
/* Set cpmac0 resources */
|
||||
cpmac_low_res[0].start = TITAN_REGS_MAC0;
|
||||
cpmac_low_res[0].end = TITAN_REGS_MAC0 + 0x7ff;
|
||||
|
||||
/* Set cpmac1 resources */
|
||||
cpmac_high_res[0].start = TITAN_REGS_MAC1;
|
||||
cpmac_high_res[0].end = TITAN_REGS_MAC1 + 0x7ff;
|
||||
}
|
||||
|
||||
static int __init ar7_register_devices(void)
|
||||
{
|
||||
void __iomem *bootcr;
|
||||
u32 val;
|
||||
int res;
|
||||
|
||||
res = ar7_gpio_init();
|
||||
if (res)
|
||||
pr_warn("unable to register gpios: %d\n", res);
|
||||
|
||||
res = ar7_register_uarts();
|
||||
if (res)
|
||||
pr_err("unable to setup uart(s): %d\n", res);
|
||||
|
||||
res = platform_device_register(&physmap_flash);
|
||||
if (res)
|
||||
pr_warn("unable to register physmap-flash: %d\n", res);
|
||||
|
||||
if (ar7_is_titan())
|
||||
titan_fixup_devices();
|
||||
|
||||
ar7_device_disable(vlynq_low_data.reset_bit);
|
||||
res = platform_device_register(&vlynq_low);
|
||||
if (res)
|
||||
pr_warn("unable to register vlynq-low: %d\n", res);
|
||||
|
||||
if (ar7_has_high_vlynq()) {
|
||||
ar7_device_disable(vlynq_high_data.reset_bit);
|
||||
res = platform_device_register(&vlynq_high);
|
||||
if (res)
|
||||
pr_warn("unable to register vlynq-high: %d\n", res);
|
||||
}
|
||||
|
||||
if (ar7_has_high_cpmac()) {
|
||||
res = fixed_phy_add(PHY_POLL, cpmac_high.id,
|
||||
&fixed_phy_status);
|
||||
if (!res) {
|
||||
cpmac_get_mac(1, cpmac_high_data.dev_addr);
|
||||
|
||||
res = platform_device_register(&cpmac_high);
|
||||
if (res)
|
||||
pr_warn("unable to register cpmac-high: %d\n",
|
||||
res);
|
||||
} else
|
||||
pr_warn("unable to add cpmac-high phy: %d\n", res);
|
||||
} else
|
||||
cpmac_low_data.phy_mask = 0xffffffff;
|
||||
|
||||
res = fixed_phy_add(PHY_POLL, cpmac_low.id, &fixed_phy_status);
|
||||
if (!res) {
|
||||
cpmac_get_mac(0, cpmac_low_data.dev_addr);
|
||||
res = platform_device_register(&cpmac_low);
|
||||
if (res)
|
||||
pr_warn("unable to register cpmac-low: %d\n", res);
|
||||
} else
|
||||
pr_warn("unable to add cpmac-low phy: %d\n", res);
|
||||
|
||||
detect_leds();
|
||||
res = platform_device_register(&ar7_gpio_leds);
|
||||
if (res)
|
||||
pr_warn("unable to register leds: %d\n", res);
|
||||
|
||||
res = platform_device_register(&ar7_udc);
|
||||
if (res)
|
||||
pr_warn("unable to register usb slave: %d\n", res);
|
||||
|
||||
/* Register watchdog only if enabled in hardware */
|
||||
bootcr = ioremap(AR7_REGS_DCL, 4);
|
||||
val = readl(bootcr);
|
||||
iounmap(bootcr);
|
||||
if (val & AR7_WDT_HW_ENA) {
|
||||
if (ar7_has_high_vlynq())
|
||||
ar7_wdt_res.start = UR8_REGS_WDT;
|
||||
else
|
||||
ar7_wdt_res.start = AR7_REGS_WDT;
|
||||
|
||||
ar7_wdt_res.end = ar7_wdt_res.start + 0x20;
|
||||
res = platform_device_register(&ar7_wdt);
|
||||
if (res)
|
||||
pr_warn("unable to register watchdog: %d\n", res);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
device_initcall(ar7_register_devices);
|
||||
@ -1,256 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Carsten Langgaard, carstenl@mips.com
|
||||
* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
|
||||
*
|
||||
* Putting things on the screen/serial line using YAMONs facilities.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/serial_reg.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/export.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/io.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/setup.h>
|
||||
|
||||
#include <asm/mach-ar7/ar7.h>
|
||||
#include <asm/mach-ar7/prom.h>
|
||||
|
||||
#define MAX_ENTRY 80
|
||||
|
||||
struct env_var {
|
||||
char *name;
|
||||
char *value;
|
||||
};
|
||||
|
||||
static struct env_var adam2_env[MAX_ENTRY];
|
||||
|
||||
char *prom_getenv(const char *name)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; (i < MAX_ENTRY) && adam2_env[i].name; i++)
|
||||
if (!strcmp(name, adam2_env[i].name))
|
||||
return adam2_env[i].value;
|
||||
|
||||
return NULL;
|
||||
}
|
||||
EXPORT_SYMBOL(prom_getenv);
|
||||
|
||||
static void __init ar7_init_cmdline(int argc, char *argv[])
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 1; i < argc; i++) {
|
||||
strlcat(arcs_cmdline, argv[i], COMMAND_LINE_SIZE);
|
||||
if (i < (argc - 1))
|
||||
strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE);
|
||||
}
|
||||
}
|
||||
|
||||
struct psbl_rec {
|
||||
u32 psbl_size;
|
||||
u32 env_base;
|
||||
u32 env_size;
|
||||
u32 ffs_base;
|
||||
u32 ffs_size;
|
||||
};
|
||||
|
||||
static const char psp_env_version[] __initconst = "TIENV0.8";
|
||||
|
||||
struct psp_env_chunk {
|
||||
u8 num;
|
||||
u8 ctrl;
|
||||
u16 csum;
|
||||
u8 len;
|
||||
char data[11];
|
||||
} __packed;
|
||||
|
||||
struct psp_var_map_entry {
|
||||
u8 num;
|
||||
char *value;
|
||||
};
|
||||
|
||||
static const struct psp_var_map_entry psp_var_map[] = {
|
||||
{ 1, "cpufrequency" },
|
||||
{ 2, "memsize" },
|
||||
{ 3, "flashsize" },
|
||||
{ 4, "modetty0" },
|
||||
{ 5, "modetty1" },
|
||||
{ 8, "maca" },
|
||||
{ 9, "macb" },
|
||||
{ 28, "sysfrequency" },
|
||||
{ 38, "mipsfrequency" },
|
||||
};
|
||||
|
||||
/*
|
||||
|
||||
Well-known variable (num is looked up in table above for matching variable name)
|
||||
Example: cpufrequency=211968000
|
||||
+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+---
|
||||
| 01 |CTRL|CHECKSUM | 01 | _2 | _1 | _1 | _9 | _6 | _8 | _0 | _0 | _0 | \0 | FF
|
||||
+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+---
|
||||
|
||||
Name=Value pair in a single chunk
|
||||
Example: NAME=VALUE
|
||||
+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+---
|
||||
| 00 |CTRL|CHECKSUM | 01 | _N | _A | _M | _E | _0 | _V | _A | _L | _U | _E | \0
|
||||
+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+---
|
||||
|
||||
Name=Value pair in 2 chunks (len is the number of chunks)
|
||||
Example: bootloaderVersion=1.3.7.15
|
||||
+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+---
|
||||
| 00 |CTRL|CHECKSUM | 02 | _b | _o | _o | _t | _l | _o | _a | _d | _e | _r | _V
|
||||
+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+---
|
||||
| _e | _r | _s | _i | _o | _n | \0 | _1 | _. | _3 | _. | _7 | _. | _1 | _5 | \0
|
||||
+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+---
|
||||
|
||||
Data is padded with 0xFF
|
||||
|
||||
*/
|
||||
|
||||
#define PSP_ENV_SIZE 4096
|
||||
|
||||
static char psp_env_data[PSP_ENV_SIZE] = { 0, };
|
||||
|
||||
static char * __init lookup_psp_var_map(u8 num)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(psp_var_map); i++)
|
||||
if (psp_var_map[i].num == num)
|
||||
return psp_var_map[i].value;
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void __init add_adam2_var(char *name, char *value)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < MAX_ENTRY; i++) {
|
||||
if (!adam2_env[i].name) {
|
||||
adam2_env[i].name = name;
|
||||
adam2_env[i].value = value;
|
||||
return;
|
||||
} else if (!strcmp(adam2_env[i].name, name)) {
|
||||
adam2_env[i].value = value;
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static int __init parse_psp_env(void *psp_env_base)
|
||||
{
|
||||
int i, n;
|
||||
char *name, *value;
|
||||
struct psp_env_chunk *chunks = (struct psp_env_chunk *)psp_env_data;
|
||||
|
||||
memcpy_fromio(chunks, psp_env_base, PSP_ENV_SIZE);
|
||||
|
||||
i = 1;
|
||||
n = PSP_ENV_SIZE / sizeof(struct psp_env_chunk);
|
||||
while (i < n) {
|
||||
if ((chunks[i].num == 0xff) || ((i + chunks[i].len) > n))
|
||||
break;
|
||||
value = chunks[i].data;
|
||||
if (chunks[i].num) {
|
||||
name = lookup_psp_var_map(chunks[i].num);
|
||||
} else {
|
||||
name = value;
|
||||
value += strlen(name) + 1;
|
||||
}
|
||||
if (name)
|
||||
add_adam2_var(name, value);
|
||||
i += chunks[i].len;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __init ar7_init_env(struct env_var *env)
|
||||
{
|
||||
int i;
|
||||
struct psbl_rec *psbl = (struct psbl_rec *)(KSEG1ADDR(0x14000300));
|
||||
void *psp_env = (void *)KSEG1ADDR(psbl->env_base);
|
||||
|
||||
if (strcmp(psp_env, psp_env_version) == 0) {
|
||||
parse_psp_env(psp_env);
|
||||
} else {
|
||||
for (i = 0; i < MAX_ENTRY; i++, env++)
|
||||
if (env->name)
|
||||
add_adam2_var(env->name, env->value);
|
||||
}
|
||||
}
|
||||
|
||||
static void __init console_config(void)
|
||||
{
|
||||
#ifdef CONFIG_SERIAL_8250_CONSOLE
|
||||
char console_string[40];
|
||||
int baud = 0;
|
||||
char parity = '\0', bits = '\0', flow = '\0';
|
||||
char *s, *p;
|
||||
|
||||
if (strstr(arcs_cmdline, "console="))
|
||||
return;
|
||||
|
||||
s = prom_getenv("modetty0");
|
||||
if (s) {
|
||||
baud = simple_strtoul(s, &p, 10);
|
||||
s = p;
|
||||
if (*s == ',')
|
||||
s++;
|
||||
if (*s)
|
||||
parity = *s++;
|
||||
if (*s == ',')
|
||||
s++;
|
||||
if (*s)
|
||||
bits = *s++;
|
||||
if (*s == ',')
|
||||
s++;
|
||||
if (*s == 'h')
|
||||
flow = 'r';
|
||||
}
|
||||
|
||||
if (baud == 0)
|
||||
baud = 38400;
|
||||
if (parity != 'n' && parity != 'o' && parity != 'e')
|
||||
parity = 'n';
|
||||
if (bits != '7' && bits != '8')
|
||||
bits = '8';
|
||||
|
||||
if (flow == 'r')
|
||||
sprintf(console_string, " console=ttyS0,%d%c%c%c", baud,
|
||||
parity, bits, flow);
|
||||
else
|
||||
sprintf(console_string, " console=ttyS0,%d%c%c", baud, parity,
|
||||
bits);
|
||||
strlcat(arcs_cmdline, console_string, COMMAND_LINE_SIZE);
|
||||
#endif
|
||||
}
|
||||
|
||||
void __init prom_init(void)
|
||||
{
|
||||
ar7_init_cmdline(fw_arg0, (char **)fw_arg1);
|
||||
ar7_init_env((struct env_var *)fw_arg2);
|
||||
console_config();
|
||||
}
|
||||
|
||||
#define PORT(offset) (KSEG1ADDR(AR7_REGS_UART0 + (offset * 4)))
|
||||
static inline unsigned int serial_in(int offset)
|
||||
{
|
||||
return readl((void *)PORT(offset));
|
||||
}
|
||||
|
||||
static inline void serial_out(int offset, int value)
|
||||
{
|
||||
writel(value, (void *)PORT(offset));
|
||||
}
|
||||
|
||||
void prom_putchar(char c)
|
||||
{
|
||||
while ((serial_in(UART_LSR) & UART_LSR_TEMT) == 0)
|
||||
;
|
||||
serial_out(UART_TX, c);
|
||||
}
|
||||
@ -1,93 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Carsten Langgaard, carstenl@mips.com
|
||||
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/pm.h>
|
||||
#include <linux/time.h>
|
||||
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/mach-ar7/ar7.h>
|
||||
#include <asm/mach-ar7/prom.h>
|
||||
|
||||
static void ar7_machine_restart(char *command)
|
||||
{
|
||||
u32 *softres_reg = ioremap(AR7_REGS_RESET + AR7_RESET_SOFTWARE, 1);
|
||||
|
||||
writel(1, softres_reg);
|
||||
}
|
||||
|
||||
static void ar7_machine_halt(void)
|
||||
{
|
||||
while (1)
|
||||
;
|
||||
}
|
||||
|
||||
static void ar7_machine_power_off(void)
|
||||
{
|
||||
u32 *power_reg = (u32 *)ioremap(AR7_REGS_POWER, 1);
|
||||
u32 power_state = readl(power_reg) | (3 << 30);
|
||||
|
||||
writel(power_state, power_reg);
|
||||
ar7_machine_halt();
|
||||
}
|
||||
|
||||
const char *get_system_type(void)
|
||||
{
|
||||
u16 chip_id = ar7_chip_id();
|
||||
u16 titan_variant_id = titan_chip_id();
|
||||
|
||||
switch (chip_id) {
|
||||
case AR7_CHIP_7100:
|
||||
return "TI AR7 (TNETD7100)";
|
||||
case AR7_CHIP_7200:
|
||||
return "TI AR7 (TNETD7200)";
|
||||
case AR7_CHIP_7300:
|
||||
return "TI AR7 (TNETD7300)";
|
||||
case AR7_CHIP_TITAN:
|
||||
switch (titan_variant_id) {
|
||||
case TITAN_CHIP_1050:
|
||||
return "TI AR7 (TNETV1050)";
|
||||
case TITAN_CHIP_1055:
|
||||
return "TI AR7 (TNETV1055)";
|
||||
case TITAN_CHIP_1056:
|
||||
return "TI AR7 (TNETV1056)";
|
||||
case TITAN_CHIP_1060:
|
||||
return "TI AR7 (TNETV1060)";
|
||||
}
|
||||
fallthrough;
|
||||
default:
|
||||
return "TI AR7 (unknown)";
|
||||
}
|
||||
}
|
||||
|
||||
static int __init ar7_init_console(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
console_initcall(ar7_init_console);
|
||||
|
||||
/*
|
||||
* Initializes basic routines and structures pointers, memory size (as
|
||||
* given by the bios and saves the command line.
|
||||
*/
|
||||
void __init plat_mem_setup(void)
|
||||
{
|
||||
unsigned long io_base;
|
||||
|
||||
_machine_restart = ar7_machine_restart;
|
||||
_machine_halt = ar7_machine_halt;
|
||||
pm_power_off = ar7_machine_power_off;
|
||||
|
||||
io_base = (unsigned long)ioremap(AR7_REGS_BASE, 0x10000);
|
||||
if (!io_base)
|
||||
panic("Can't remap IO base!");
|
||||
set_io_port_base(io_base);
|
||||
|
||||
prom_meminit();
|
||||
|
||||
printk(KERN_INFO "%s, ID: 0x%04x, Revision: 0x%02x\n",
|
||||
get_system_type(), ar7_chip_id(), ar7_chip_rev());
|
||||
}
|
||||
@ -1,31 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Carsten Langgaard, carstenl@mips.com
|
||||
* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
|
||||
*
|
||||
* Setting up the clock on the MIPS boards.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/time.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/clk.h>
|
||||
|
||||
#include <asm/time.h>
|
||||
#include <asm/mach-ar7/ar7.h>
|
||||
|
||||
void __init plat_time_init(void)
|
||||
{
|
||||
struct clk *cpu_clk;
|
||||
|
||||
/* Initialize ar7 clocks so the CPU clock frequency is correct */
|
||||
ar7_init_clocks();
|
||||
|
||||
cpu_clk = clk_get(NULL, "cpu");
|
||||
if (IS_ERR(cpu_clk)) {
|
||||
printk(KERN_ERR "unable to get cpu clock\n");
|
||||
return;
|
||||
}
|
||||
|
||||
mips_hpt_frequency = clk_get_rate(cpu_clk) / 2;
|
||||
}
|
||||
@ -13,11 +13,6 @@
|
||||
#define PORT(offset) (CKSEG1ADDR(UART_BASE) + (offset))
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_AR7
|
||||
#include <ar7.h>
|
||||
#define PORT(offset) (CKSEG1ADDR(AR7_REGS_UART0) + (4 * offset))
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_INGENIC
|
||||
#define INGENIC_UART_BASE_ADDR (0x10030000 + 0x1000 * CONFIG_ZBOOT_INGENIC_UART)
|
||||
#define PORT(offset) (CKSEG1ADDR(INGENIC_UART_BASE_ADDR) + (4 * offset))
|
||||
|
||||
@ -1,119 +0,0 @@
|
||||
# CONFIG_LOCALVERSION_AUTO is not set
|
||||
CONFIG_KERNEL_LZMA=y
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_BSD_PROCESS_ACCT=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_RELAY=y
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_EXPERT=y
|
||||
# CONFIG_ELF_CORE is not set
|
||||
# CONFIG_KALLSYMS is not set
|
||||
# CONFIG_VM_EVENT_COUNTERS is not set
|
||||
# CONFIG_COMPAT_BRK is not set
|
||||
CONFIG_AR7=y
|
||||
CONFIG_HZ_100=y
|
||||
CONFIG_KEXEC=y
|
||||
# CONFIG_SECCOMP is not set
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_BSD_DISKLABEL=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_MULTICAST=y
|
||||
CONFIG_IP_ADVANCED_ROUTER=y
|
||||
CONFIG_IP_MULTIPLE_TABLES=y
|
||||
CONFIG_IP_ROUTE_MULTIPATH=y
|
||||
CONFIG_IP_ROUTE_VERBOSE=y
|
||||
CONFIG_IP_MROUTE=y
|
||||
CONFIG_SYN_COOKIES=y
|
||||
# CONFIG_INET_DIAG is not set
|
||||
CONFIG_TCP_CONG_ADVANCED=y
|
||||
# CONFIG_TCP_CONG_BIC is not set
|
||||
# CONFIG_TCP_CONG_CUBIC is not set
|
||||
CONFIG_TCP_CONG_WESTWOOD=y
|
||||
# CONFIG_TCP_CONG_HTCP is not set
|
||||
# CONFIG_IPV6 is not set
|
||||
CONFIG_NETFILTER=y
|
||||
# CONFIG_BRIDGE_NETFILTER is not set
|
||||
CONFIG_NF_CONNTRACK=m
|
||||
CONFIG_NF_CONNTRACK_MARK=y
|
||||
CONFIG_NF_CONNTRACK_FTP=m
|
||||
CONFIG_NF_CONNTRACK_IRC=m
|
||||
CONFIG_NF_CONNTRACK_TFTP=m
|
||||
CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
|
||||
CONFIG_NETFILTER_XT_MATCH_LIMIT=m
|
||||
CONFIG_NETFILTER_XT_MATCH_MAC=m
|
||||
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
|
||||
CONFIG_NETFILTER_XT_MATCH_STATE=m
|
||||
CONFIG_IP_NF_IPTABLES=m
|
||||
CONFIG_IP_NF_FILTER=m
|
||||
CONFIG_IP_NF_TARGET_REJECT=m
|
||||
CONFIG_IP_NF_MANGLE=m
|
||||
CONFIG_IP_NF_RAW=m
|
||||
CONFIG_ATM=m
|
||||
CONFIG_ATM_BR2684=m
|
||||
CONFIG_ATM_BR2684_IPFILTER=y
|
||||
CONFIG_BRIDGE=y
|
||||
CONFIG_VLAN_8021Q=y
|
||||
CONFIG_NET_SCHED=y
|
||||
CONFIG_NET_CLS_ACT=y
|
||||
CONFIG_NET_ACT_POLICE=y
|
||||
CONFIG_HAMRADIO=y
|
||||
CONFIG_CFG80211=m
|
||||
CONFIG_MAC80211=m
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_CFI=y
|
||||
CONFIG_MTD_CFI_INTELEXT=y
|
||||
CONFIG_MTD_CFI_AMDSTD=y
|
||||
CONFIG_MTD_CFI_STAA=y
|
||||
CONFIG_MTD_COMPLEX_MAPPINGS=y
|
||||
CONFIG_MTD_PHYSMAP=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_CPMAC=y
|
||||
CONFIG_FIXED_PHY=y
|
||||
CONFIG_PPP=m
|
||||
CONFIG_PPP_FILTER=y
|
||||
CONFIG_PPP_MULTILINK=y
|
||||
CONFIG_PPPOATM=m
|
||||
CONFIG_PPPOE=m
|
||||
CONFIG_PPP_ASYNC=m
|
||||
# CONFIG_INPUT is not set
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_VT is not set
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_8250_NR_UARTS=2
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_WATCHDOG=y
|
||||
CONFIG_AR7_WDT=y
|
||||
# CONFIG_USB_SUPPORT is not set
|
||||
CONFIG_NEW_LEDS=y
|
||||
CONFIG_LEDS_CLASS=y
|
||||
CONFIG_LEDS_GPIO=y
|
||||
CONFIG_LEDS_TRIGGERS=y
|
||||
CONFIG_LEDS_TRIGGER_TIMER=y
|
||||
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
|
||||
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
|
||||
# CONFIG_DNOTIFY is not set
|
||||
CONFIG_PROC_KCORE=y
|
||||
# CONFIG_PROC_PAGE_MONITOR is not set
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_JFFS2_FS=y
|
||||
CONFIG_JFFS2_SUMMARY=y
|
||||
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
|
||||
CONFIG_SQUASHFS=y
|
||||
# CONFIG_CRYPTO_HW is not set
|
||||
CONFIG_STRIP_ASM_SYMS=y
|
||||
CONFIG_DEBUG_FS=y
|
||||
CONFIG_CMDLINE_BOOL=y
|
||||
CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
|
||||
@ -1,191 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org>
|
||||
* Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org>
|
||||
*/
|
||||
|
||||
#ifndef __AR7_H__
|
||||
#define __AR7_H__
|
||||
|
||||
#include <linux/delay.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/errno.h>
|
||||
|
||||
#include <asm/addrspace.h>
|
||||
|
||||
#define AR7_SDRAM_BASE 0x14000000
|
||||
|
||||
#define AR7_REGS_BASE 0x08610000
|
||||
|
||||
#define AR7_REGS_MAC0 (AR7_REGS_BASE + 0x0000)
|
||||
#define AR7_REGS_GPIO (AR7_REGS_BASE + 0x0900)
|
||||
/* 0x08610A00 - 0x08610BFF (512 bytes, 128 bytes / clock) */
|
||||
#define AR7_REGS_POWER (AR7_REGS_BASE + 0x0a00)
|
||||
#define AR7_REGS_CLOCKS (AR7_REGS_POWER + 0x80)
|
||||
#define UR8_REGS_CLOCKS (AR7_REGS_POWER + 0x20)
|
||||
#define AR7_REGS_UART0 (AR7_REGS_BASE + 0x0e00)
|
||||
#define AR7_REGS_USB (AR7_REGS_BASE + 0x1200)
|
||||
#define AR7_REGS_RESET (AR7_REGS_BASE + 0x1600)
|
||||
#define AR7_REGS_PINSEL (AR7_REGS_BASE + 0x160C)
|
||||
#define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800)
|
||||
#define AR7_REGS_DCL (AR7_REGS_BASE + 0x1a00)
|
||||
#define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1c00)
|
||||
#define AR7_REGS_MDIO (AR7_REGS_BASE + 0x1e00)
|
||||
#define AR7_REGS_IRQ (AR7_REGS_BASE + 0x2400)
|
||||
#define AR7_REGS_MAC1 (AR7_REGS_BASE + 0x2800)
|
||||
|
||||
#define AR7_REGS_WDT (AR7_REGS_BASE + 0x1f00)
|
||||
#define UR8_REGS_WDT (AR7_REGS_BASE + 0x0b00)
|
||||
#define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00)
|
||||
|
||||
/* Titan registers */
|
||||
#define TITAN_REGS_ESWITCH_BASE (0x08640000)
|
||||
#define TITAN_REGS_MAC0 (TITAN_REGS_ESWITCH_BASE)
|
||||
#define TITAN_REGS_MAC1 (TITAN_REGS_ESWITCH_BASE + 0x0800)
|
||||
#define TITAN_REGS_MDIO (TITAN_REGS_ESWITCH_BASE + 0x02000)
|
||||
#define TITAN_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1c00)
|
||||
#define TITAN_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1300)
|
||||
|
||||
#define AR7_RESET_PERIPHERAL 0x0
|
||||
#define AR7_RESET_SOFTWARE 0x4
|
||||
#define AR7_RESET_STATUS 0x8
|
||||
|
||||
#define AR7_RESET_BIT_CPMAC_LO 17
|
||||
#define AR7_RESET_BIT_CPMAC_HI 21
|
||||
#define AR7_RESET_BIT_MDIO 22
|
||||
#define AR7_RESET_BIT_EPHY 26
|
||||
|
||||
#define TITAN_RESET_BIT_EPHY1 28
|
||||
|
||||
/* GPIO control registers */
|
||||
#define AR7_GPIO_INPUT 0x0
|
||||
#define AR7_GPIO_OUTPUT 0x4
|
||||
#define AR7_GPIO_DIR 0x8
|
||||
#define AR7_GPIO_ENABLE 0xc
|
||||
#define TITAN_GPIO_INPUT_0 0x0
|
||||
#define TITAN_GPIO_INPUT_1 0x4
|
||||
#define TITAN_GPIO_OUTPUT_0 0x8
|
||||
#define TITAN_GPIO_OUTPUT_1 0xc
|
||||
#define TITAN_GPIO_DIR_0 0x10
|
||||
#define TITAN_GPIO_DIR_1 0x14
|
||||
#define TITAN_GPIO_ENBL_0 0x18
|
||||
#define TITAN_GPIO_ENBL_1 0x1c
|
||||
|
||||
#define AR7_CHIP_7100 0x18
|
||||
#define AR7_CHIP_7200 0x2b
|
||||
#define AR7_CHIP_7300 0x05
|
||||
#define AR7_CHIP_TITAN 0x07
|
||||
#define TITAN_CHIP_1050 0x0f
|
||||
#define TITAN_CHIP_1055 0x0e
|
||||
#define TITAN_CHIP_1056 0x0d
|
||||
#define TITAN_CHIP_1060 0x07
|
||||
|
||||
/* Interrupts */
|
||||
#define AR7_IRQ_UART0 15
|
||||
#define AR7_IRQ_UART1 16
|
||||
|
||||
/* Clocks */
|
||||
#define AR7_AFE_CLOCK 35328000
|
||||
#define AR7_REF_CLOCK 25000000
|
||||
#define AR7_XTAL_CLOCK 24000000
|
||||
|
||||
/* DCL */
|
||||
#define AR7_WDT_HW_ENA 0x10
|
||||
|
||||
struct plat_cpmac_data {
|
||||
int reset_bit;
|
||||
int power_bit;
|
||||
u32 phy_mask;
|
||||
char dev_addr[6];
|
||||
};
|
||||
|
||||
struct plat_dsl_data {
|
||||
int reset_bit_dsl;
|
||||
int reset_bit_sar;
|
||||
};
|
||||
|
||||
static inline int ar7_is_titan(void)
|
||||
{
|
||||
return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x24)) & 0xffff) ==
|
||||
AR7_CHIP_TITAN;
|
||||
}
|
||||
|
||||
static inline u16 ar7_chip_id(void)
|
||||
{
|
||||
return ar7_is_titan() ? AR7_CHIP_TITAN : (readl((void *)
|
||||
KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff);
|
||||
}
|
||||
|
||||
static inline u16 titan_chip_id(void)
|
||||
{
|
||||
unsigned int val = readl((void *)KSEG1ADDR(AR7_REGS_GPIO +
|
||||
TITAN_GPIO_INPUT_1));
|
||||
return ((val >> 12) & 0x0f);
|
||||
}
|
||||
|
||||
static inline u8 ar7_chip_rev(void)
|
||||
{
|
||||
return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + (ar7_is_titan() ? 0x24 :
|
||||
0x14))) >> 16) & 0xff;
|
||||
}
|
||||
|
||||
static inline int ar7_has_high_cpmac(void)
|
||||
{
|
||||
u16 chip_id = ar7_chip_id();
|
||||
switch (chip_id) {
|
||||
case AR7_CHIP_7100:
|
||||
case AR7_CHIP_7200:
|
||||
return 0;
|
||||
case AR7_CHIP_7300:
|
||||
return 1;
|
||||
default:
|
||||
return -ENXIO;
|
||||
}
|
||||
}
|
||||
#define ar7_has_high_vlynq ar7_has_high_cpmac
|
||||
#define ar7_has_second_uart ar7_has_high_cpmac
|
||||
|
||||
static inline void ar7_device_enable(u32 bit)
|
||||
{
|
||||
void *reset_reg =
|
||||
(void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PERIPHERAL);
|
||||
writel(readl(reset_reg) | (1 << bit), reset_reg);
|
||||
msleep(20);
|
||||
}
|
||||
|
||||
static inline void ar7_device_disable(u32 bit)
|
||||
{
|
||||
void *reset_reg =
|
||||
(void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PERIPHERAL);
|
||||
writel(readl(reset_reg) & ~(1 << bit), reset_reg);
|
||||
msleep(20);
|
||||
}
|
||||
|
||||
static inline void ar7_device_reset(u32 bit)
|
||||
{
|
||||
ar7_device_disable(bit);
|
||||
ar7_device_enable(bit);
|
||||
}
|
||||
|
||||
static inline void ar7_device_on(u32 bit)
|
||||
{
|
||||
void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
|
||||
writel(readl(power_reg) | (1 << bit), power_reg);
|
||||
msleep(20);
|
||||
}
|
||||
|
||||
static inline void ar7_device_off(u32 bit)
|
||||
{
|
||||
void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
|
||||
writel(readl(power_reg) & ~(1 << bit), power_reg);
|
||||
msleep(20);
|
||||
}
|
||||
|
||||
int __init ar7_gpio_init(void);
|
||||
void __init ar7_init_clocks(void);
|
||||
|
||||
/* Board specific GPIO functions */
|
||||
int ar7_gpio_enable(unsigned gpio);
|
||||
int ar7_gpio_disable(unsigned gpio);
|
||||
|
||||
#endif /* __AR7_H__ */
|
||||
@ -1,16 +0,0 @@
|
||||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Shamelessly copied from asm-mips/mach-emma2rh/
|
||||
* Copyright (C) 2003 by Ralf Baechle
|
||||
*/
|
||||
#ifndef __ASM_AR7_IRQ_H
|
||||
#define __ASM_AR7_IRQ_H
|
||||
|
||||
#define NR_IRQS 256
|
||||
|
||||
#include <asm/mach-generic/irq.h>
|
||||
|
||||
#endif /* __ASM_AR7_IRQ_H */
|
||||
@ -1,12 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* Copyright (C) 2006, 2007 Florian Fainelli <florian@openwrt.org>
|
||||
*/
|
||||
|
||||
#ifndef __PROM_H__
|
||||
#define __PROM_H__
|
||||
|
||||
extern char *prom_getenv(const char *name);
|
||||
extern void prom_meminit(void);
|
||||
|
||||
#endif /* __PROM_H__ */
|
||||
@ -1,22 +0,0 @@
|
||||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle
|
||||
* Copyright (C) 2000, 2002 Maciej W. Rozycki
|
||||
* Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
|
||||
*/
|
||||
#ifndef _ASM_AR7_SPACES_H
|
||||
#define _ASM_AR7_SPACES_H
|
||||
|
||||
/*
|
||||
* This handles the memory map.
|
||||
* We handle pages at KSEG0 for kernels with 32 bit address space.
|
||||
*/
|
||||
#define PAGE_OFFSET _AC(0x94000000, UL)
|
||||
#define PHYS_OFFSET _AC(0x14000000, UL)
|
||||
|
||||
#include <asm/mach-generic/spaces.h>
|
||||
|
||||
#endif /* __ASM_AR7_SPACES_H */
|
||||
Loading…
Reference in New Issue
Block a user