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drm/i915: fix TLB invalidation for Gen12.50 video and compute engines

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In case of Gen12.50 video and compute engines, TLB_INV registers are
masked - to modify one bit, corresponding bit in upper half of the register
must be enabled, otherwise nothing happens.

Fixes: 77fa9efc16 ("drm/i915/xehp: Create separate reg definitions for new MCR registers")
Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221214075439.402485-1-andrzej.hajda@intel.com
This commit is contained in:
Andrzej Hajda 2022-12-14 08:54:39 +01:00 committed by Andi Shyti
parent 95df9cc24b
commit 4d5cf7b168
1 changed files with 7 additions and 1 deletions
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8
drivers/gpu/drm/i915/gt/intel_gt.c
View File

@ -1099,9 +1099,15 @@ static void mmio_invalidate_full(struct intel_gt *gt)
continue; continue;
if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
u32 val = BIT(engine->instance);
if (engine->class == VIDEO_DECODE_CLASS ||
engine->class == VIDEO_ENHANCEMENT_CLASS ||
engine->class == COMPUTE_CLASS)
val = _MASKED_BIT_ENABLE(val);
intel_gt_mcr_multicast_write_fw(gt, intel_gt_mcr_multicast_write_fw(gt,
xehp_regs[engine->class], xehp_regs[engine->class],
BIT(engine->instance)); val);
} else { } else {
rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num); rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num);
if (!i915_mmio_reg_offset(rb.reg)) if (!i915_mmio_reg_offset(rb.reg))