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Merge branch 'pci/misc'
- Check pcie_find_root_port() return in x86 fixups to avoid NULL pointer dereferences (Samasth Norway Ananda) - Make pci_bus_type constant (Kunwu Chan) - Remove unused declarations of __pci_pme_wakeup() and pci_vpd_release() (Yue Haibing) - Remove any leftover .*.cmd files with make clean (zhang jiao) * pci/misc: PCI: Fix typos PCI/VPD: Remove pci_vpd_release() unused declarations PCI/PM: Remove __pci_pme_wakeup() unused declarations PCI: Make pci_bus_type constant x86/PCI: Check pcie_find_root_port() return for NULL
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5dc07a20ac
@ -980,7 +980,7 @@ static void amd_rp_pme_suspend(struct pci_dev *dev)
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return;
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rp = pcie_find_root_port(dev);
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if (!rp->pm_cap)
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if (!rp || !rp->pm_cap)
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return;
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rp->pme_support &= ~((PCI_PM_CAP_PME_D3hot|PCI_PM_CAP_PME_D3cold) >>
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@ -994,7 +994,7 @@ static void amd_rp_pme_resume(struct pci_dev *dev)
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u16 pmc;
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rp = pcie_find_root_port(dev);
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if (!rp->pm_cap)
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if (!rp || !rp->pm_cap)
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return;
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pci_read_config_word(rp, rp->pm_cap + PCI_PM_PMC, &pmc);
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@ -455,8 +455,8 @@ void pci_restore_pasid_state(struct pci_dev *pdev)
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* pci_pasid_features - Check which PASID features are supported
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* @pdev: PCI device structure
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*
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* Returns a negative value when no PASI capability is present.
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* Otherwise is returns a bitmask with supported features. Current
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* Return a negative value when no PASID capability is present.
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* Otherwise return a bitmask with supported features. Current
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* features reported are:
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* PCI_PASID_CAP_EXEC - Execute permission supported
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* PCI_PASID_CAP_PRIV - Privileged mode supported
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@ -38,7 +38,7 @@ config PCIE_CADENCE_PLAT_EP
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select PCIE_CADENCE_EP
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select PCIE_CADENCE_PLAT
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help
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Say Y here if you want to support the Cadence PCIe platform controller in
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Say Y here if you want to support the Cadence PCIe platform controller in
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endpoint mode. This PCIe controller may be embedded into many
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different vendors SoCs.
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@ -328,7 +328,7 @@ get_slot_mapping(struct pci_bus *bus, u8 bus_num, u8 dev_num, u8 *slot)
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} else {
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/* Did not get a match on the target PCI device. Check
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* if the current IRQ table entry is a PCI-to-PCI
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* bridge device. If so, and it's secondary bus
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* bridge device. If so, and its secondary bus
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* matches the bus number for the target device, I need
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* to save the bridge's slot number. If I can not find
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* an entry for the target device, I will have to
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@ -112,7 +112,7 @@ static int get_power_status(struct hotplug_slot *hotplug_slot, u8 *value)
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static int get_adapter_status(struct hotplug_slot *hotplug_slot, u8 *value)
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{
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/* if the slot exits it always contains a function */
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/* if the slot exists it always contains a function */
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*value = 1;
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return 0;
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}
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@ -156,7 +156,7 @@ EXPORT_SYMBOL_GPL(pci_iomap_wc);
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* the different IOMAP ranges.
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*
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* But if the architecture does not use the generic iomap code, and if
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* it has _not_ defined it's own private pci_iounmap function, we define
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* it has _not_ defined its own private pci_iounmap function, we define
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* it here.
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*
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* NOTE! This default implementation assumes that if the architecture
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@ -1670,7 +1670,7 @@ static void pci_dma_cleanup(struct device *dev)
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iommu_device_unuse_default_domain(dev);
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}
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struct bus_type pci_bus_type = {
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const struct bus_type pci_bus_type = {
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.name = "pci",
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.match = pci_bus_match,
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.uevent = pci_uevent,
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@ -139,7 +139,6 @@ void pcie_clear_device_status(struct pci_dev *dev);
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void pcie_clear_root_pme_status(struct pci_dev *dev);
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bool pci_check_pme_status(struct pci_dev *dev);
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void pci_pme_wakeup_bus(struct pci_bus *bus);
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int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
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void pci_pme_restore(struct pci_dev *dev);
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bool pci_dev_need_resume(struct pci_dev *dev);
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void pci_dev_adjust_pme(struct pci_dev *dev);
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@ -189,7 +188,6 @@ static inline bool pcie_downstream_port(const struct pci_dev *dev)
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}
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void pci_vpd_init(struct pci_dev *dev);
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void pci_vpd_release(struct pci_dev *dev);
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extern const struct attribute_group pci_dev_vpd_attr_group;
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/* PCI Virtual Channel */
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@ -1102,7 +1102,7 @@ enum pcie_bus_config_types {
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extern enum pcie_bus_config_types pcie_bus_config;
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extern struct bus_type pci_bus_type;
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extern const struct bus_type pci_bus_type;
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/* Do NOT directly access these two variables, unless you are arch-specific PCI
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* code, or PCI core code. */
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