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clk: starfive: Add StarFive JH7110 PLL clock driver
Add driver for the StarFive JH7110 PLL clock controller and they work by reading and setting syscon registers. Co-developed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
Xingyu Wu
Conor Dooley
parent
a097a5ec14
commit
616bc1dea1
@ -20271,6 +20271,12 @@ S: Supported
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F: Documentation/devicetree/bindings/mmc/starfive*
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F: drivers/mmc/host/dw_mmc-starfive.c
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STARFIVE JH7110 PLL CLOCK DRIVER
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M: Xingyu Wu <xingyu.wu@starfivetech.com>
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S: Supported
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F: Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml
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F: drivers/clk/starfive/clk-starfive-jh7110-pll.c
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STARFIVE JH7110 SYSCON
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M: William Qiu <william.qiu@starfivetech.com>
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M: Xingyu Wu <xingyu.wu@starfivetech.com>
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@ -21,6 +21,14 @@ config CLK_STARFIVE_JH7100_AUDIO
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Say Y or M here to support the audio clocks on the StarFive JH7100
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SoC.
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config CLK_STARFIVE_JH7110_PLL
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bool "StarFive JH7110 PLL clock support"
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depends on ARCH_STARFIVE || COMPILE_TEST
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default ARCH_STARFIVE
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help
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Say yes here to support the PLL clock controller on the
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StarFive JH7110 SoC.
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config CLK_STARFIVE_JH7110_SYS
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bool "StarFive JH7110 system clock support"
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depends on ARCH_STARFIVE || COMPILE_TEST
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@ -4,5 +4,6 @@ obj-$(CONFIG_CLK_STARFIVE_JH71X0) += clk-starfive-jh71x0.o
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obj-$(CONFIG_CLK_STARFIVE_JH7100) += clk-starfive-jh7100.o
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obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) += clk-starfive-jh7100-audio.o
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obj-$(CONFIG_CLK_STARFIVE_JH7110_PLL) += clk-starfive-jh7110-pll.o
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obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS) += clk-starfive-jh7110-sys.o
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obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o
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507
drivers/clk/starfive/clk-starfive-jh7110-pll.c
Normal file
507
drivers/clk/starfive/clk-starfive-jh7110-pll.c
Normal file
@ -0,0 +1,507 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* StarFive JH7110 PLL Clock Generator Driver
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*
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* Copyright (C) 2023 StarFive Technology Co., Ltd.
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* Copyright (C) 2023 Emil Renner Berthing <emil.renner.berthing@canonical.com>
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*
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* This driver is about to register JH7110 PLL clock generator and support ops.
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* The JH7110 have three PLL clock, PLL0, PLL1 and PLL2.
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* Each PLL clocks work in integer mode or fraction mode by some dividers,
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* and the configuration registers and dividers are set in several syscon registers.
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* The formula for calculating frequency is:
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* Fvco = Fref * (NI + NF) / M / Q1
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* Fref: OSC source clock rate
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* NI: integer frequency dividing ratio of feedback divider, set by fbdiv[11:0].
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* NF: fractional frequency dividing ratio, set by frac[23:0]. NF = frac[23:0] / 2^24 = 0 ~ 0.999.
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* M: frequency dividing ratio of pre-divider, set by prediv[5:0].
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* Q1: frequency dividing ratio of post divider, set by 2^postdiv1[1:0], eg. 1, 2, 4 or 8.
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*/
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#include <linux/bits.h>
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#include <linux/clk-provider.h>
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#include <linux/debugfs.h>
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/starfive,jh7110-crg.h>
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/* this driver expects a 24MHz input frequency from the oscillator */
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#define JH7110_PLL_OSC_RATE 24000000UL
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#define JH7110_PLL0_PD_OFFSET 0x18
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#define JH7110_PLL0_DACPD_SHIFT 24
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#define JH7110_PLL0_DACPD_MASK BIT(24)
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#define JH7110_PLL0_DSMPD_SHIFT 25
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#define JH7110_PLL0_DSMPD_MASK BIT(25)
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#define JH7110_PLL0_FBDIV_OFFSET 0x1c
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#define JH7110_PLL0_FBDIV_SHIFT 0
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#define JH7110_PLL0_FBDIV_MASK GENMASK(11, 0)
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#define JH7110_PLL0_FRAC_OFFSET 0x20
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#define JH7110_PLL0_PREDIV_OFFSET 0x24
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#define JH7110_PLL1_PD_OFFSET 0x24
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#define JH7110_PLL1_DACPD_SHIFT 15
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#define JH7110_PLL1_DACPD_MASK BIT(15)
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#define JH7110_PLL1_DSMPD_SHIFT 16
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#define JH7110_PLL1_DSMPD_MASK BIT(16)
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#define JH7110_PLL1_FBDIV_OFFSET 0x24
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#define JH7110_PLL1_FBDIV_SHIFT 17
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#define JH7110_PLL1_FBDIV_MASK GENMASK(28, 17)
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#define JH7110_PLL1_FRAC_OFFSET 0x28
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#define JH7110_PLL1_PREDIV_OFFSET 0x2c
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#define JH7110_PLL2_PD_OFFSET 0x2c
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#define JH7110_PLL2_DACPD_SHIFT 15
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#define JH7110_PLL2_DACPD_MASK BIT(15)
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#define JH7110_PLL2_DSMPD_SHIFT 16
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#define JH7110_PLL2_DSMPD_MASK BIT(16)
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#define JH7110_PLL2_FBDIV_OFFSET 0x2c
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#define JH7110_PLL2_FBDIV_SHIFT 17
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#define JH7110_PLL2_FBDIV_MASK GENMASK(28, 17)
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#define JH7110_PLL2_FRAC_OFFSET 0x30
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#define JH7110_PLL2_PREDIV_OFFSET 0x34
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#define JH7110_PLL_FRAC_SHIFT 0
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#define JH7110_PLL_FRAC_MASK GENMASK(23, 0)
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#define JH7110_PLL_POSTDIV1_SHIFT 28
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#define JH7110_PLL_POSTDIV1_MASK GENMASK(29, 28)
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#define JH7110_PLL_PREDIV_SHIFT 0
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#define JH7110_PLL_PREDIV_MASK GENMASK(5, 0)
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enum jh7110_pll_mode {
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JH7110_PLL_MODE_FRACTION,
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JH7110_PLL_MODE_INTEGER,
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};
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struct jh7110_pll_preset {
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unsigned long freq;
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u32 frac; /* frac value should be decimals multiplied by 2^24 */
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unsigned fbdiv : 12; /* fbdiv value should be 8 to 4095 */
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unsigned prediv : 6;
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unsigned postdiv1 : 2;
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unsigned mode : 1;
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};
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struct jh7110_pll_info {
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char *name;
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const struct jh7110_pll_preset *presets;
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unsigned int npresets;
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struct {
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unsigned int pd;
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unsigned int fbdiv;
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unsigned int frac;
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unsigned int prediv;
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} offsets;
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struct {
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u32 dacpd;
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u32 dsmpd;
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u32 fbdiv;
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} masks;
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struct {
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char dacpd;
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char dsmpd;
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char fbdiv;
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} shifts;
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};
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#define _JH7110_PLL(_idx, _name, _presets) \
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[_idx] = { \
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.name = _name, \
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.presets = _presets, \
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.npresets = ARRAY_SIZE(_presets), \
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.offsets = { \
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.pd = JH7110_PLL##_idx##_PD_OFFSET, \
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.fbdiv = JH7110_PLL##_idx##_FBDIV_OFFSET, \
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.frac = JH7110_PLL##_idx##_FRAC_OFFSET, \
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.prediv = JH7110_PLL##_idx##_PREDIV_OFFSET, \
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}, \
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.masks = { \
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.dacpd = JH7110_PLL##_idx##_DACPD_MASK, \
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.dsmpd = JH7110_PLL##_idx##_DSMPD_MASK, \
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.fbdiv = JH7110_PLL##_idx##_FBDIV_MASK, \
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}, \
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.shifts = { \
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.dacpd = JH7110_PLL##_idx##_DACPD_SHIFT, \
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.dsmpd = JH7110_PLL##_idx##_DSMPD_SHIFT, \
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.fbdiv = JH7110_PLL##_idx##_FBDIV_SHIFT, \
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}, \
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}
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#define JH7110_PLL(idx, name, presets) _JH7110_PLL(idx, name, presets)
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struct jh7110_pll_data {
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struct clk_hw hw;
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unsigned int idx;
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};
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struct jh7110_pll_priv {
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struct device *dev;
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struct regmap *regmap;
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struct jh7110_pll_data pll[JH7110_PLLCLK_END];
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};
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struct jh7110_pll_regvals {
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u32 dacpd;
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u32 dsmpd;
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u32 fbdiv;
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u32 frac;
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u32 postdiv1;
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u32 prediv;
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};
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/*
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* Because the pll frequency is relatively fixed,
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* it cannot be set arbitrarily, so it needs a specific configuration.
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* PLL0 frequency should be multiple of 125MHz (USB frequency).
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*/
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static const struct jh7110_pll_preset jh7110_pll0_presets[] = {
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{
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.freq = 375000000,
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.fbdiv = 125,
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.prediv = 8,
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.postdiv1 = 0,
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.mode = JH7110_PLL_MODE_INTEGER,
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}, {
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.freq = 500000000,
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.fbdiv = 125,
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.prediv = 6,
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.postdiv1 = 0,
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.mode = JH7110_PLL_MODE_INTEGER,
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}, {
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.freq = 625000000,
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.fbdiv = 625,
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.prediv = 24,
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.postdiv1 = 0,
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.mode = JH7110_PLL_MODE_INTEGER,
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}, {
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.freq = 750000000,
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.fbdiv = 125,
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.prediv = 4,
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.postdiv1 = 0,
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.mode = JH7110_PLL_MODE_INTEGER,
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}, {
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.freq = 875000000,
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.fbdiv = 875,
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.prediv = 24,
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.postdiv1 = 0,
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.mode = JH7110_PLL_MODE_INTEGER,
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}, {
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.freq = 1000000000,
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.fbdiv = 125,
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.prediv = 3,
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.postdiv1 = 0,
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.mode = JH7110_PLL_MODE_INTEGER,
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}, {
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.freq = 1250000000,
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.fbdiv = 625,
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.prediv = 12,
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.postdiv1 = 0,
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.mode = JH7110_PLL_MODE_INTEGER,
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}, {
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.freq = 1375000000,
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.fbdiv = 1375,
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.prediv = 24,
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.postdiv1 = 0,
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.mode = JH7110_PLL_MODE_INTEGER,
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}, {
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.freq = 1500000000,
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.fbdiv = 125,
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.prediv = 2,
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.postdiv1 = 0,
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.mode = JH7110_PLL_MODE_INTEGER,
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},
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};
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static const struct jh7110_pll_preset jh7110_pll1_presets[] = {
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{
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.freq = 1066000000,
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.fbdiv = 533,
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.prediv = 12,
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.postdiv1 = 0,
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.mode = JH7110_PLL_MODE_INTEGER,
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}, {
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.freq = 1200000000,
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.fbdiv = 50,
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.prediv = 1,
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.postdiv1 = 0,
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.mode = JH7110_PLL_MODE_INTEGER,
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}, {
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.freq = 1400000000,
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.fbdiv = 350,
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.prediv = 6,
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.postdiv1 = 0,
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.mode = JH7110_PLL_MODE_INTEGER,
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}, {
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.freq = 1600000000,
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.fbdiv = 200,
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.prediv = 3,
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.postdiv1 = 0,
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.mode = JH7110_PLL_MODE_INTEGER,
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},
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};
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static const struct jh7110_pll_preset jh7110_pll2_presets[] = {
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{
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.freq = 1188000000,
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.fbdiv = 99,
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.prediv = 2,
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.postdiv1 = 0,
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.mode = JH7110_PLL_MODE_INTEGER,
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}, {
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.freq = 1228800000,
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.fbdiv = 256,
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.prediv = 5,
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.postdiv1 = 0,
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.mode = JH7110_PLL_MODE_INTEGER,
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},
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};
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static const struct jh7110_pll_info jh7110_plls[JH7110_PLLCLK_END] = {
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JH7110_PLL(JH7110_PLLCLK_PLL0_OUT, "pll0_out", jh7110_pll0_presets),
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JH7110_PLL(JH7110_PLLCLK_PLL1_OUT, "pll1_out", jh7110_pll1_presets),
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JH7110_PLL(JH7110_PLLCLK_PLL2_OUT, "pll2_out", jh7110_pll2_presets),
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};
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static struct jh7110_pll_data *jh7110_pll_data_from(struct clk_hw *hw)
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{
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return container_of(hw, struct jh7110_pll_data, hw);
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}
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static struct jh7110_pll_priv *jh7110_pll_priv_from(struct jh7110_pll_data *pll)
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{
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return container_of(pll, struct jh7110_pll_priv, pll[pll->idx]);
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}
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static void jh7110_pll_regvals_get(struct regmap *regmap,
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const struct jh7110_pll_info *info,
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struct jh7110_pll_regvals *ret)
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{
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u32 val;
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regmap_read(regmap, info->offsets.pd, &val);
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ret->dacpd = (val & info->masks.dacpd) >> info->shifts.dacpd;
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ret->dsmpd = (val & info->masks.dsmpd) >> info->shifts.dsmpd;
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regmap_read(regmap, info->offsets.fbdiv, &val);
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ret->fbdiv = (val & info->masks.fbdiv) >> info->shifts.fbdiv;
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regmap_read(regmap, info->offsets.frac, &val);
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ret->frac = (val & JH7110_PLL_FRAC_MASK) >> JH7110_PLL_FRAC_SHIFT;
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ret->postdiv1 = (val & JH7110_PLL_POSTDIV1_MASK) >> JH7110_PLL_POSTDIV1_SHIFT;
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regmap_read(regmap, info->offsets.prediv, &val);
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ret->prediv = (val & JH7110_PLL_PREDIV_MASK) >> JH7110_PLL_PREDIV_SHIFT;
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}
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static unsigned long jh7110_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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{
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struct jh7110_pll_data *pll = jh7110_pll_data_from(hw);
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struct jh7110_pll_priv *priv = jh7110_pll_priv_from(pll);
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struct jh7110_pll_regvals val;
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unsigned long rate;
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jh7110_pll_regvals_get(priv->regmap, &jh7110_plls[pll->idx], &val);
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/*
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* dacpd = dsmpd = 0: fraction mode
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* dacpd = dsmpd = 1: integer mode, frac value ignored
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*
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* rate = parent * (fbdiv + frac/2^24) / prediv / 2^postdiv1
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* = (parent * fbdiv + parent * frac / 2^24) / (prediv * 2^postdiv1)
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*/
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if (val.dacpd == 0 && val.dsmpd == 0)
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rate = parent_rate * val.frac / (1UL << 24);
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else if (val.dacpd == 1 && val.dsmpd == 1)
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rate = 0;
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else
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return 0;
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rate += parent_rate * val.fbdiv;
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rate /= val.prediv << val.postdiv1;
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return rate;
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}
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static int jh7110_pll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
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{
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struct jh7110_pll_data *pll = jh7110_pll_data_from(hw);
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const struct jh7110_pll_info *info = &jh7110_plls[pll->idx];
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const struct jh7110_pll_preset *selected = &info->presets[0];
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unsigned int idx;
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/* if the parent rate doesn't match our expectations the presets won't work */
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if (req->best_parent_rate != JH7110_PLL_OSC_RATE) {
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req->rate = jh7110_pll_recalc_rate(hw, req->best_parent_rate);
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return 0;
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}
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/* find highest rate lower or equal to the requested rate */
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for (idx = 1; idx < info->npresets; idx++) {
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const struct jh7110_pll_preset *val = &info->presets[idx];
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if (req->rate < val->freq)
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break;
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selected = val;
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}
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req->rate = selected->freq;
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return 0;
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}
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static int jh7110_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct jh7110_pll_data *pll = jh7110_pll_data_from(hw);
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struct jh7110_pll_priv *priv = jh7110_pll_priv_from(pll);
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const struct jh7110_pll_info *info = &jh7110_plls[pll->idx];
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const struct jh7110_pll_preset *val;
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unsigned int idx;
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/* if the parent rate doesn't match our expectations the presets won't work */
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if (parent_rate != JH7110_PLL_OSC_RATE)
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return -EINVAL;
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for (idx = 0, val = &info->presets[0]; idx < info->npresets; idx++, val++) {
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||||
if (val->freq == rate)
|
||||
goto found;
|
||||
}
|
||||
return -EINVAL;
|
||||
|
||||
found:
|
||||
if (val->mode == JH7110_PLL_MODE_FRACTION)
|
||||
regmap_update_bits(priv->regmap, info->offsets.frac, JH7110_PLL_FRAC_MASK,
|
||||
val->frac << JH7110_PLL_FRAC_SHIFT);
|
||||
|
||||
regmap_update_bits(priv->regmap, info->offsets.pd, info->masks.dacpd,
|
||||
(u32)val->mode << info->shifts.dacpd);
|
||||
regmap_update_bits(priv->regmap, info->offsets.pd, info->masks.dsmpd,
|
||||
(u32)val->mode << info->shifts.dsmpd);
|
||||
regmap_update_bits(priv->regmap, info->offsets.prediv, JH7110_PLL_PREDIV_MASK,
|
||||
(u32)val->prediv << JH7110_PLL_PREDIV_SHIFT);
|
||||
regmap_update_bits(priv->regmap, info->offsets.fbdiv, info->masks.fbdiv,
|
||||
val->fbdiv << info->shifts.fbdiv);
|
||||
regmap_update_bits(priv->regmap, info->offsets.frac, JH7110_PLL_POSTDIV1_MASK,
|
||||
(u32)val->postdiv1 << JH7110_PLL_POSTDIV1_SHIFT);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
static int jh7110_pll_registers_read(struct seq_file *s, void *unused)
|
||||
{
|
||||
struct jh7110_pll_data *pll = s->private;
|
||||
struct jh7110_pll_priv *priv = jh7110_pll_priv_from(pll);
|
||||
struct jh7110_pll_regvals val;
|
||||
|
||||
jh7110_pll_regvals_get(priv->regmap, &jh7110_plls[pll->idx], &val);
|
||||
|
||||
seq_printf(s, "fbdiv=%u\n"
|
||||
"frac=%u\n"
|
||||
"prediv=%u\n"
|
||||
"postdiv1=%u\n"
|
||||
"dacpd=%u\n"
|
||||
"dsmpd=%u\n",
|
||||
val.fbdiv, val.frac, val.prediv, val.postdiv1,
|
||||
val.dacpd, val.dsmpd);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int jh7110_pll_registers_open(struct inode *inode, struct file *f)
|
||||
{
|
||||
return single_open(f, jh7110_pll_registers_read, inode->i_private);
|
||||
}
|
||||
|
||||
static const struct file_operations jh7110_pll_registers_ops = {
|
||||
.owner = THIS_MODULE,
|
||||
.open = jh7110_pll_registers_open,
|
||||
.release = single_release,
|
||||
.read = seq_read,
|
||||
.llseek = seq_lseek
|
||||
};
|
||||
|
||||
static void jh7110_pll_debug_init(struct clk_hw *hw, struct dentry *dentry)
|
||||
{
|
||||
struct jh7110_pll_data *pll = jh7110_pll_data_from(hw);
|
||||
|
||||
debugfs_create_file("registers", 0400, dentry, pll,
|
||||
&jh7110_pll_registers_ops);
|
||||
}
|
||||
#else
|
||||
#define jh7110_pll_debug_init NULL
|
||||
#endif
|
||||
|
||||
static const struct clk_ops jh7110_pll_ops = {
|
||||
.recalc_rate = jh7110_pll_recalc_rate,
|
||||
.determine_rate = jh7110_pll_determine_rate,
|
||||
.set_rate = jh7110_pll_set_rate,
|
||||
.debug_init = jh7110_pll_debug_init,
|
||||
};
|
||||
|
||||
static struct clk_hw *jh7110_pll_get(struct of_phandle_args *clkspec, void *data)
|
||||
{
|
||||
struct jh7110_pll_priv *priv = data;
|
||||
unsigned int idx = clkspec->args[0];
|
||||
|
||||
if (idx < JH7110_PLLCLK_END)
|
||||
return &priv->pll[idx].hw;
|
||||
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
static int jh7110_pll_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct jh7110_pll_priv *priv;
|
||||
unsigned int idx;
|
||||
int ret;
|
||||
|
||||
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
priv->dev = &pdev->dev;
|
||||
priv->regmap = syscon_node_to_regmap(priv->dev->of_node->parent);
|
||||
if (IS_ERR(priv->regmap))
|
||||
return PTR_ERR(priv->regmap);
|
||||
|
||||
for (idx = 0; idx < JH7110_PLLCLK_END; idx++) {
|
||||
struct clk_parent_data parents = {
|
||||
.index = 0,
|
||||
};
|
||||
struct clk_init_data init = {
|
||||
.name = jh7110_plls[idx].name,
|
||||
.ops = &jh7110_pll_ops,
|
||||
.parent_data = &parents,
|
||||
.num_parents = 1,
|
||||
.flags = 0,
|
||||
};
|
||||
struct jh7110_pll_data *pll = &priv->pll[idx];
|
||||
|
||||
pll->hw.init = &init;
|
||||
pll->idx = idx;
|
||||
|
||||
ret = devm_clk_hw_register(&pdev->dev, &pll->hw);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return devm_of_clk_add_hw_provider(&pdev->dev, jh7110_pll_get, priv);
|
||||
}
|
||||
|
||||
static const struct of_device_id jh7110_pll_match[] = {
|
||||
{ .compatible = "starfive,jh7110-pll" },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, jh7110_pll_match);
|
||||
|
||||
static struct platform_driver jh7110_pll_driver = {
|
||||
.driver = {
|
||||
.name = "clk-starfive-jh7110-pll",
|
||||
.of_match_table = jh7110_pll_match,
|
||||
},
|
||||
};
|
||||
builtin_platform_driver_probe(jh7110_pll_driver, jh7110_pll_probe);
|
||||
Loading…
Reference in New Issue
Block a user