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ARM: smp: remove arch-provided "pen_release"

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Consolidating the "pen_release" stuff amongst the various SoC
implementations gives credence to having a CPU holding pen for
secondary CPUs.  However, this is far from the truth.

Many SoC implementations cargo-cult copied various bits of the pen
release implementation from the initial Realview/Versatile Express
implementation without understanding what it was or why it existed.
The reason it existed is because these are _development_ platforms,
and some board firmware is unable to individually control the
startup of secondary CPUs.  Moreover, they do not have a way to
power down or reset secondary CPUs for hot-unplug.  Hence, the
pen_release implementation was designed for ARM Ltd's development
platforms to provide a working implementation, even though it is
very far from what is required.

It was decided a while back to reduce the duplication by consolidating
the "pen_release" variable, but this only made the situation worse -
we have ended up with several implementations that read this variable
but do not write it - again, showing the cargo-cult mentality at work,
lack of proper review of new code, and in some cases a lack of testing.

While it would be preferable to remove pen_release entirely from the
kernel, this is not possible without help from the SoC maintainers,
which seems to be lacking.  However, I want to remove pen_release from
arch code to remove the credence that having it gives.

This patch removes pen_release from the arch code entirely, adding
private per-SoC definitions for it instead, and explicitly stating
that write_pen_release() is cargo-cult copied and should not be
copied any further.  Rename write_pen_release() in a similar fashion
as well.

Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
This commit is contained in:
Russell King 2018-12-13 14:02:48 +00:00
parent 70678554c4
commit 6213f70e7c
12 changed files with 56 additions and 43 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/include/asm/smp.h
View File

@ -67,7 +67,6 @@ struct secondary_data {
void *stack;
};
extern struct secondary_data secondary_data;
extern volatile int pen_release;
extern void secondary_startup(void);
extern void secondary_startup_arm(void);

6
arch/arm/kernel/smp.c
View File

@ -62,12 +62,6 @@
*/
struct secondary_data secondary_data;
/*
* control for which core is the next to come out of the secondary
* boot "holding pen"
*/
volatile int pen_release = -1;
enum ipi_msg_type {
IPI_WAKEUP,
IPI_TIMER,

2
arch/arm/mach-exynos/headsmp.S
View File

@ -36,4 +36,4 @@ ENDPROC(exynos4_secondary_startup)
.align 2
1: .long .
.long pen_release
.long exynos_pen_release

31
arch/arm/mach-exynos/platsmp.c
View File

@ -28,6 +28,9 @@
extern void exynos4_secondary_startup(void);
/* XXX exynos_pen_release is cargo culted code - DO NOT COPY XXX */
volatile int exynos_pen_release = -1;
#ifdef CONFIG_HOTPLUG_CPU
static inline void cpu_leave_lowpower(u32 core_id)
{
@ -57,7 +60,7 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
wfi();
if (pen_release == core_id) {
if (exynos_pen_release == core_id) {
/*
* OK, proper wakeup, we're done
*/
@ -228,15 +231,17 @@ void exynos_core_restart(u32 core_id)
}
/*
* Write pen_release in a way that is guaranteed to be visible to all
* observers, irrespective of whether they're taking part in coherency
* XXX CARGO CULTED CODE - DO NOT COPY XXX
*
* Write exynos_pen_release in a way that is guaranteed to be visible to
* all observers, irrespective of whether they're taking part in coherency
* or not. This is necessary for the hotplug code to work reliably.
*/
static void write_pen_release(int val)
static void exynos_write_pen_release(int val)
{
pen_release = val;
exynos_pen_release = val;
smp_wmb();
sync_cache_w(&pen_release);
sync_cache_w(&exynos_pen_release);
}
static DEFINE_SPINLOCK(boot_lock);
@ -247,7 +252,7 @@ static void exynos_secondary_init(unsigned int cpu)
* let the primary processor know we're out of the
* pen, then head off into the C entry point
*/
write_pen_release(-1);
exynos_write_pen_release(-1);
/*
* Synchronise with the boot thread.
@ -322,12 +327,12 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
/*
* The secondary processor is waiting to be released from
* the holding pen - release it, then wait for it to flag
* that it has been released by resetting pen_release.
* that it has been released by resetting exynos_pen_release.
*
* Note that "pen_release" is the hardware CPU core ID, whereas
* Note that "exynos_pen_release" is the hardware CPU core ID, whereas
* "cpu" is Linux's internal ID.
*/
write_pen_release(core_id);
exynos_write_pen_release(core_id);
if (!exynos_cpu_power_state(core_id)) {
exynos_cpu_power_up(core_id);
@ -376,13 +381,13 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
else
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
if (pen_release == -1)
if (exynos_pen_release == -1)
break;
udelay(10);
}
if (pen_release != -1)
if (exynos_pen_release != -1)
ret = -ETIMEDOUT;
/*
@ -392,7 +397,7 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
fail:
spin_unlock(&boot_lock);
return pen_release != -1 ? ret : 0;
return exynos_pen_release != -1 ? ret : 0;
}
static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)

2
arch/arm/mach-prima2/common.h
View File

@ -15,6 +15,8 @@
#include <asm/mach/time.h>
#include <asm/exception.h>
extern volatile int prima2_pen_release;
extern const struct smp_operations sirfsoc_smp_ops;
extern void sirfsoc_secondary_startup(void);
extern void sirfsoc_cpu_die(unsigned int cpu);

2
arch/arm/mach-prima2/headsmp.S
View File

@ -34,4 +34,4 @@ ENDPROC(sirfsoc_secondary_startup)
.align
1: .long .
.long pen_release
.long prima2_pen_release

3
arch/arm/mach-prima2/hotplug.c
View File

@ -11,6 +11,7 @@
#include <linux/smp.h>
#include <asm/smp_plat.h>
#include "common.h"
static inline void platform_do_lowpower(unsigned int cpu)
{
@ -18,7 +19,7 @@ static inline void platform_do_lowpower(unsigned int cpu)
for (;;) {
__asm__ __volatile__("dsb\n\t" "wfi\n\t"
: : : "memory");
if (pen_release == cpu_logical_map(cpu)) {
if (prima2_pen_release == cpu_logical_map(cpu)) {
/*
* OK, proper wakeup, we're done
*/

17
arch/arm/mach-prima2/platsmp.c
View File

@ -24,13 +24,16 @@ static void __iomem *clk_base;
static DEFINE_SPINLOCK(boot_lock);
/* XXX prima2_pen_release is cargo culted code - DO NOT COPY XXX */
volatile int prima2_pen_release = -1;
static void sirfsoc_secondary_init(unsigned int cpu)
{
/*
* let the primary processor know we're out of the
* pen, then head off into the C entry point
*/
pen_release = -1;
prima2_pen_release = -1;
smp_wmb();
/*
@ -80,13 +83,13 @@ static int sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle)
/*
* The secondary processor is waiting to be released from
* the holding pen - release it, then wait for it to flag
* that it has been released by resetting pen_release.
* that it has been released by resetting prima2_pen_release.
*
* Note that "pen_release" is the hardware CPU ID, whereas
* Note that "prima2_pen_release" is the hardware CPU ID, whereas
* "cpu" is Linux's internal ID.
*/
pen_release = cpu_logical_map(cpu);
sync_cache_w(&pen_release);
prima2_pen_release = cpu_logical_map(cpu);
sync_cache_w(&prima2_pen_release);
/*
* Send the secondary CPU SEV, thereby causing the boot monitor to read
@ -97,7 +100,7 @@ static int sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle)
timeout = jiffies + (1 * HZ);
while (time_before(jiffies, timeout)) {
smp_rmb();
if (pen_release == -1)
if (prima2_pen_release == -1)
break;
udelay(10);
@ -109,7 +112,7 @@ static int sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle)
*/
spin_unlock(&boot_lock);
return pen_release != -1 ? -ENOSYS : 0;
return prima2_pen_release != -1 ? -ENOSYS : 0;
}
const struct smp_operations sirfsoc_smp_ops __initconst = {

2
arch/arm/mach-spear/generic.h
View File

@ -20,6 +20,8 @@
#include <asm/mach/time.h>
extern volatile int spear_pen_release;
extern void spear13xx_timer_init(void);
extern void spear3xx_timer_init(void);
extern struct pl022_ssp_controller pl022_plat_data;

2
arch/arm/mach-spear/headsmp.S
View File

@ -43,5 +43,5 @@ pen: ldr r7, [r6]
.align
1: .long .
.long pen_release
.long spear_pen_release
ENDPROC(spear13xx_secondary_startup)

4
arch/arm/mach-spear/hotplug.c
View File

@ -16,6 +16,8 @@
#include <asm/cp15.h>
#include <asm/smp_plat.h>
#include "generic.h"
static inline void cpu_enter_lowpower(void)
{
unsigned int v;
@ -57,7 +59,7 @@ static inline void spear13xx_do_lowpower(unsigned int cpu, int *spurious)
for (;;) {
wfi();
if (pen_release == cpu) {
if (spear_pen_release == cpu) {
/*
* OK, proper wakeup, we're done
*/

27
arch/arm/mach-spear/platsmp.c
View File

@ -20,16 +20,21 @@
#include <mach/spear.h>
#include "generic.h"
/* XXX spear_pen_release is cargo culted code - DO NOT COPY XXX */
volatile int spear_pen_release = -1;
/*
* Write pen_release in a way that is guaranteed to be visible to all
* observers, irrespective of whether they're taking part in coherency
* XXX CARGO CULTED CODE - DO NOT COPY XXX
*
* Write spear_pen_release in a way that is guaranteed to be visible to
* all observers, irrespective of whether they're taking part in coherency
* or not. This is necessary for the hotplug code to work reliably.
*/
static void write_pen_release(int val)
static void spear_write_pen_release(int val)
{
pen_release = val;
spear_pen_release = val;
smp_wmb();
sync_cache_w(&pen_release);
sync_cache_w(&spear_pen_release);
}
static DEFINE_SPINLOCK(boot_lock);
@ -42,7 +47,7 @@ static void spear13xx_secondary_init(unsigned int cpu)
* let the primary processor know we're out of the
* pen, then head off into the C entry point
*/
write_pen_release(-1);
spear_write_pen_release(-1);
/*
* Synchronise with the boot thread.
@ -64,17 +69,17 @@ static int spear13xx_boot_secondary(unsigned int cpu, struct task_struct *idle)
/*
* The secondary processor is waiting to be released from
* the holding pen - release it, then wait for it to flag
* that it has been released by resetting pen_release.
* that it has been released by resetting spear_pen_release.
*
* Note that "pen_release" is the hardware CPU ID, whereas
* Note that "spear_pen_release" is the hardware CPU ID, whereas
* "cpu" is Linux's internal ID.
*/
write_pen_release(cpu);
spear_write_pen_release(cpu);
timeout = jiffies + (1 * HZ);
while (time_before(jiffies, timeout)) {
smp_rmb();
if (pen_release == -1)
if (spear_pen_release == -1)
break;
udelay(10);
@ -86,7 +91,7 @@ static int spear13xx_boot_secondary(unsigned int cpu, struct task_struct *idle)
*/
spin_unlock(&boot_lock);
return pen_release != -1 ? -ENOSYS : 0;
return spear_pen_release != -1 ? -ENOSYS : 0;
}
/*