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coresight: etm4x: Fix accesses to TRCPROCSELR

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TRCPROCSELR is not implemented if the TRCIDR3.NUMPROC == 0. Skip
accessing the register in such cases.

Cc: stable@vger.kernel.org
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20201127175256.1092685-7-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Suzuki K Poulose 2020-11-27 10:52:47 -07:00 committed by Greg Kroah-Hartman
parent 4e2187274f
commit 6288b4ceca
1 changed files with 6 additions and 4 deletions
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10
drivers/hwtracing/coresight/coresight-etm4x-core.c
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@ -124,8 +124,8 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1))
dev_err(etm_dev, dev_err(etm_dev,
"timeout while waiting for Idle Trace Status\n"); "timeout while waiting for Idle Trace Status\n");
if (drvdata->nr_pe)
writel_relaxed(config->pe_sel, drvdata->base + TRCPROCSELR); writel_relaxed(config->pe_sel, drvdata->base + TRCPROCSELR);
writel_relaxed(config->cfg, drvdata->base + TRCCONFIGR); writel_relaxed(config->cfg, drvdata->base + TRCCONFIGR);
/* nothing specific implemented */ /* nothing specific implemented */
writel_relaxed(0x0, drvdata->base + TRCAUXCTLR); writel_relaxed(0x0, drvdata->base + TRCAUXCTLR);
@ -1185,7 +1185,8 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
state = drvdata->save_state; state = drvdata->save_state;
state->trcprgctlr = readl(drvdata->base + TRCPRGCTLR); state->trcprgctlr = readl(drvdata->base + TRCPRGCTLR);
state->trcprocselr = readl(drvdata->base + TRCPROCSELR); if (drvdata->nr_pe)
state->trcprocselr = readl(drvdata->base + TRCPROCSELR);
state->trcconfigr = readl(drvdata->base + TRCCONFIGR); state->trcconfigr = readl(drvdata->base + TRCCONFIGR);
state->trcauxctlr = readl(drvdata->base + TRCAUXCTLR); state->trcauxctlr = readl(drvdata->base + TRCAUXCTLR);
state->trceventctl0r = readl(drvdata->base + TRCEVENTCTL0R); state->trceventctl0r = readl(drvdata->base + TRCEVENTCTL0R);
@ -1292,7 +1293,8 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
writel_relaxed(state->trcclaimset, drvdata->base + TRCCLAIMSET); writel_relaxed(state->trcclaimset, drvdata->base + TRCCLAIMSET);
writel_relaxed(state->trcprgctlr, drvdata->base + TRCPRGCTLR); writel_relaxed(state->trcprgctlr, drvdata->base + TRCPRGCTLR);
writel_relaxed(state->trcprocselr, drvdata->base + TRCPROCSELR); if (drvdata->nr_pe)
writel_relaxed(state->trcprocselr, drvdata->base + TRCPROCSELR);
writel_relaxed(state->trcconfigr, drvdata->base + TRCCONFIGR); writel_relaxed(state->trcconfigr, drvdata->base + TRCCONFIGR);
writel_relaxed(state->trcauxctlr, drvdata->base + TRCAUXCTLR); writel_relaxed(state->trcauxctlr, drvdata->base + TRCAUXCTLR);
writel_relaxed(state->trceventctl0r, drvdata->base + TRCEVENTCTL0R); writel_relaxed(state->trceventctl0r, drvdata->base + TRCEVENTCTL0R);