mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
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- fix for loongson64 device tree
- add SPI nand to realtek device tree - change clock tree for mobileye -----BEGIN PGP SIGNATURE----- iQJOBAABCAA4FiEEbt46xwy6kEcDOXoUeZbBVTGwZHAFAmdJe7oaHHRzYm9nZW5k QGFscGhhLmZyYW5rZW4uZGUACgkQeZbBVTGwZHDtFA/9HizYQrLv1qoK+e/7OTkE XT0S1jcV534x+yQlMops+aGHIif8ghrf4nHq3i2JNPI0hzasS8ao4jO8qFTONeoa b9yh7EchGSPptR5Qc3d4OxXQ9rWdeAXe4ByVavW+odgzRRoIuH6oFrUs/KXIo5Zn 3d1bpcNLultZKfLVryrT9Q74cQ4TNwlpwfjuGLsUO2xSzQ0PBlZSY2bokrxdUg9t xH0IR3Nd9v0e6P5zUdpRcHI1Hu2GXzz0bTnkxDsmETlDYU/VI51BYWHmNGUscYAz iUqrI4FZD/ncTmrqgZOI1SG3jTKh8dx9HZDU+nN2P35OPClMgKQYLBpMg0/Kffgf hX/qet0aPwSOYPfzb0Ao1CQO3FNbZ7oipo3DkuM3dwihJA0pbPHDuTmKpS11Agec 5XSYPmNJg253TC0cPBKty/TgzVlxNi9+ss7MreO3uRY6HGo2f+kX7fO4+7iDkCF0 nrTJ/PLdH4WTn+pykk4f8uA32hGmjiJN0/rxAkbIZ78noVnPStGBXNCbbqPzUShV FmNgyo+ob5H6iZF8o+8u1CRk8aAIEwsNIysJmHNNEVp3ox8GGb5LnXWv9bosxwOs 72HLQOxAiaiWirfxcXpIjKUT6nGxivOdRkmptfTMAi6u2EwlynHyj4z+Cs5mGBfa tNc9Px3EPsatzG0MUji7f00= =f5du -----END PGP SIGNATURE----- Merge tag 'mips_6.13_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux Pull MIPS updates from Thomas Bogendoerfer: - fix for loongson64 device tree - add SPI nand to realtek device tree - change clock tree for mobileye * tag 'mips_6.13_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: MIPS: Loongson64: DTS: Really fix PCIe port nodes for ls7a mips: dts: realtek: Add SPI NAND controller MIPS: mobileye: eyeq6h: add OLB nodes OLB and remove fixed clocks MIPS: mobileye: eyeq5: use OLB as provider for fixed factor clocks
This commit is contained in:
Linus Torvalds
commit
63c81af15c
@ -70,7 +70,6 @@ pci@1a000000 {
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <2>;
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msi-parent = <&msi>;
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reg = <0 0x1a000000 0 0x02000000>,
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@ -234,7 +233,7 @@ phy1: ethernet-phy@1 {
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};
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};
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pci_bridge@9,0 {
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pcie@9,0 {
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compatible = "pci0014,7a19.1",
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"pci0014,7a19",
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"pciclass060400",
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@ -244,12 +243,16 @@ pci_bridge@9,0 {
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interrupts = <32 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&pic>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &pic 32 IRQ_TYPE_LEVEL_HIGH>;
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ranges;
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};
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pci_bridge@a,0 {
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pcie@a,0 {
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compatible = "pci0014,7a09.1",
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"pci0014,7a09",
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"pciclass060400",
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@ -259,12 +262,16 @@ pci_bridge@a,0 {
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interrupts = <33 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&pic>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &pic 33 IRQ_TYPE_LEVEL_HIGH>;
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ranges;
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};
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pci_bridge@b,0 {
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pcie@b,0 {
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compatible = "pci0014,7a09.1",
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"pci0014,7a09",
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"pciclass060400",
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@ -274,12 +281,16 @@ pci_bridge@b,0 {
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interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&pic>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &pic 34 IRQ_TYPE_LEVEL_HIGH>;
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ranges;
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};
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pci_bridge@c,0 {
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pcie@c,0 {
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compatible = "pci0014,7a09.1",
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"pci0014,7a09",
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"pciclass060400",
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@ -289,12 +300,16 @@ pci_bridge@c,0 {
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interrupts = <35 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&pic>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &pic 35 IRQ_TYPE_LEVEL_HIGH>;
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ranges;
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};
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pci_bridge@d,0 {
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pcie@d,0 {
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compatible = "pci0014,7a19.1",
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"pci0014,7a19",
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"pciclass060400",
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@ -304,12 +319,16 @@ pci_bridge@d,0 {
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interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&pic>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &pic 36 IRQ_TYPE_LEVEL_HIGH>;
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ranges;
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};
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pci_bridge@e,0 {
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pcie@e,0 {
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compatible = "pci0014,7a09.1",
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"pci0014,7a09",
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"pciclass060400",
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@ -319,12 +338,16 @@ pci_bridge@e,0 {
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interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&pic>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &pic 37 IRQ_TYPE_LEVEL_HIGH>;
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ranges;
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};
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pci_bridge@f,0 {
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pcie@f,0 {
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compatible = "pci0014,7a29.1",
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"pci0014,7a29",
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"pciclass060400",
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@ -334,12 +357,16 @@ pci_bridge@f,0 {
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interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&pic>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &pic 40 IRQ_TYPE_LEVEL_HIGH>;
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ranges;
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};
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pci_bridge@10,0 {
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pcie@10,0 {
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compatible = "pci0014,7a19.1",
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"pci0014,7a19",
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"pciclass060400",
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@ -349,12 +376,16 @@ pci_bridge@10,0 {
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interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&pic>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &pic 41 IRQ_TYPE_LEVEL_HIGH>;
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ranges;
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};
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pci_bridge@11,0 {
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pcie@11,0 {
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compatible = "pci0014,7a29.1",
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"pci0014,7a29",
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"pciclass060400",
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@ -364,12 +395,16 @@ pci_bridge@11,0 {
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interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&pic>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &pic 42 IRQ_TYPE_LEVEL_HIGH>;
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ranges;
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};
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pci_bridge@12,0 {
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pcie@12,0 {
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compatible = "pci0014,7a19.1",
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"pci0014,7a19",
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"pciclass060400",
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@ -379,12 +414,16 @@ pci_bridge@12,0 {
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interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&pic>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &pic 43 IRQ_TYPE_LEVEL_HIGH>;
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ranges;
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};
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pci_bridge@13,0 {
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pcie@13,0 {
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compatible = "pci0014,7a29.1",
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"pci0014,7a29",
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"pciclass060400",
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@ -394,12 +433,16 @@ pci_bridge@13,0 {
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interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&pic>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &pic 38 IRQ_TYPE_LEVEL_HIGH>;
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ranges;
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};
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pci_bridge@14,0 {
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pcie@14,0 {
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compatible = "pci0014,7a19.1",
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"pci0014,7a19",
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"pciclass060400",
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@ -409,9 +452,13 @@ pci_bridge@14,0 {
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interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&pic>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &pic 39 IRQ_TYPE_LEVEL_HIGH>;
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ranges;
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};
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};
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@ -1,270 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Copyright 2023 Mobileye Vision Technologies Ltd.
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*/
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#include <dt-bindings/clock/mobileye,eyeq5-clk.h>
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/ {
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/* Fixed clock */
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xtal: xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <30000000>;
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};
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/* PLL_CPU derivatives */
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occ_cpu: occ-cpu {
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compatible = "fixed-factor-clock";
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clocks = <&olb EQ5C_PLL_CPU>;
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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};
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si_css0_ref_clk: si-css0-ref-clk { /* gate ClkRstGen_si_css0_ref */
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compatible = "fixed-factor-clock";
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clocks = <&occ_cpu>;
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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};
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cpc_clk: cpc-clk {
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compatible = "fixed-factor-clock";
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clocks = <&si_css0_ref_clk>;
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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};
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core0_clk: core0-clk {
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compatible = "fixed-factor-clock";
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clocks = <&si_css0_ref_clk>;
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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};
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core1_clk: core1-clk {
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compatible = "fixed-factor-clock";
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clocks = <&si_css0_ref_clk>;
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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};
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core2_clk: core2-clk {
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compatible = "fixed-factor-clock";
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clocks = <&si_css0_ref_clk>;
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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};
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core3_clk: core3-clk {
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compatible = "fixed-factor-clock";
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clocks = <&si_css0_ref_clk>;
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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};
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cm_clk: cm-clk {
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compatible = "fixed-factor-clock";
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clocks = <&si_css0_ref_clk>;
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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};
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mem_clk: mem-clk {
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compatible = "fixed-factor-clock";
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clocks = <&si_css0_ref_clk>;
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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};
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occ_isram: occ-isram {
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compatible = "fixed-factor-clock";
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clocks = <&olb EQ5C_PLL_CPU>;
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#clock-cells = <0>;
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clock-div = <2>;
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clock-mult = <1>;
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};
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isram_clk: isram-clk { /* gate ClkRstGen_isram */
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compatible = "fixed-factor-clock";
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clocks = <&occ_isram>;
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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};
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occ_dbu: occ-dbu {
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compatible = "fixed-factor-clock";
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clocks = <&olb EQ5C_PLL_CPU>;
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#clock-cells = <0>;
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clock-div = <10>;
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clock-mult = <1>;
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};
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si_dbu_tp_pclk: si-dbu-tp-pclk { /* gate ClkRstGen_dbu */
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compatible = "fixed-factor-clock";
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clocks = <&occ_dbu>;
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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};
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/* PLL_VDI derivatives */
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occ_vdi: occ-vdi {
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compatible = "fixed-factor-clock";
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clocks = <&olb EQ5C_PLL_VDI>;
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#clock-cells = <0>;
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clock-div = <2>;
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clock-mult = <1>;
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};
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vdi_clk: vdi-clk { /* gate ClkRstGen_vdi */
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compatible = "fixed-factor-clock";
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clocks = <&occ_vdi>;
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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};
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occ_can_ser: occ-can-ser {
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compatible = "fixed-factor-clock";
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clocks = <&olb EQ5C_PLL_VDI>;
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#clock-cells = <0>;
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clock-div = <16>;
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clock-mult = <1>;
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};
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can_ser_clk: can-ser-clk { /* gate ClkRstGen_can_ser */
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compatible = "fixed-factor-clock";
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clocks = <&occ_can_ser>;
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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};
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i2c_ser_clk: i2c-ser-clk {
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compatible = "fixed-factor-clock";
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clocks = <&olb EQ5C_PLL_VDI>;
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#clock-cells = <0>;
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clock-div = <20>;
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clock-mult = <1>;
|
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};
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/* PLL_PER derivatives */
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occ_periph: occ-periph {
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compatible = "fixed-factor-clock";
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clocks = <&olb EQ5C_PLL_PER>;
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#clock-cells = <0>;
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clock-div = <16>;
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clock-mult = <1>;
|
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};
|
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periph_clk: periph-clk {
|
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compatible = "fixed-factor-clock";
|
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clocks = <&occ_periph>;
|
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#clock-cells = <0>;
|
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clock-div = <1>;
|
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clock-mult = <1>;
|
||||
};
|
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can_clk: can-clk {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&occ_periph>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <1>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
spi_clk: spi-clk {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&occ_periph>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <1>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
uart_clk: uart-clk {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&occ_periph>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <1>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
i2c_clk: i2c-clk {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&occ_periph>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <1>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "i2c_clk";
|
||||
};
|
||||
timer_clk: timer-clk {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&occ_periph>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <1>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "timer_clk";
|
||||
};
|
||||
gpio_clk: gpio-clk {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&occ_periph>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <1>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "gpio_clk";
|
||||
};
|
||||
emmc_sys_clk: emmc-sys-clk {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&olb EQ5C_PLL_PER>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <10>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "emmc_sys_clk";
|
||||
};
|
||||
ccf_ctrl_clk: ccf-ctrl-clk {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&olb EQ5C_PLL_PER>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <4>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "ccf_ctrl_clk";
|
||||
};
|
||||
occ_mjpeg_core: occ-mjpeg-core {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&olb EQ5C_PLL_PER>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "occ_mjpeg_core";
|
||||
};
|
||||
hsm_clk: hsm-clk { /* gate ClkRstGen_hsm */
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&occ_mjpeg_core>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <1>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "hsm_clk";
|
||||
};
|
||||
mjpeg_core_clk: mjpeg-core-clk { /* gate ClkRstGen_mjpeg_gen */
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&occ_mjpeg_core>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <1>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "mjpeg_core_clk";
|
||||
};
|
||||
fcmu_a_clk: fcmu-a-clk {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&olb EQ5C_PLL_PER>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <20>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "fcmu_a_clk";
|
||||
};
|
||||
occ_pci_sys: occ-pci-sys {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&olb EQ5C_PLL_PER>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <8>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "occ_pci_sys";
|
||||
};
|
||||
pclk: pclk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <250000000>; /* 250MHz */
|
||||
};
|
||||
tsu_clk: tsu-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <125000000>; /* 125MHz */
|
||||
};
|
||||
};
|
||||
@ -5,7 +5,7 @@
|
||||
|
||||
#include <dt-bindings/interrupt-controller/mips-gic.h>
|
||||
|
||||
#include "eyeq5-clocks.dtsi"
|
||||
#include <dt-bindings/clock/mobileye,eyeq5-clk.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
@ -17,7 +17,7 @@ cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "img,i6500";
|
||||
reg = <0>;
|
||||
clocks = <&core0_clk>;
|
||||
clocks = <&olb EQ5C_CPU_CORE0>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -64,6 +64,24 @@ cpu_intc: interrupt-controller {
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
xtal: xtal {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <30000000>;
|
||||
};
|
||||
|
||||
pclk: pclk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <250000000>; /* 250MHz */
|
||||
};
|
||||
|
||||
tsu_clk: tsu-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <125000000>; /* 125MHz */
|
||||
};
|
||||
|
||||
soc: soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
@ -76,7 +94,7 @@ uart0: serial@800000 {
|
||||
reg-io-width = <4>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&uart_clk>, <&occ_periph>;
|
||||
clocks = <&olb EQ5C_PER_UART>, <&olb EQ5C_PER_OCC>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
resets = <&olb 0 10>;
|
||||
pinctrl-names = "default";
|
||||
@ -89,7 +107,7 @@ uart1: serial@900000 {
|
||||
reg-io-width = <4>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&uart_clk>, <&occ_periph>;
|
||||
clocks = <&olb EQ5C_PER_UART>, <&olb EQ5C_PER_OCC>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
resets = <&olb 0 11>;
|
||||
pinctrl-names = "default";
|
||||
@ -102,7 +120,7 @@ uart2: serial@a00000 {
|
||||
reg-io-width = <4>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&uart_clk>, <&occ_periph>;
|
||||
clocks = <&olb EQ5C_PER_UART>, <&olb EQ5C_PER_OCC>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
resets = <&olb 0 12>;
|
||||
pinctrl-names = "default";
|
||||
@ -135,7 +153,7 @@ gic: interrupt-controller@140000 {
|
||||
timer {
|
||||
compatible = "mti,gic-timer";
|
||||
interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
|
||||
clocks = <&core0_clk>;
|
||||
clocks = <&olb EQ5C_CPU_CORE0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -1,52 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
/*
|
||||
* Copyright 2023 Mobileye Vision Technologies Ltd.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/mobileye,eyeq5-clk.h>
|
||||
|
||||
/ {
|
||||
xtal: clock-30000000 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <30000000>;
|
||||
};
|
||||
|
||||
pll_west: clock-2000000000-west {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <2000000000>;
|
||||
};
|
||||
|
||||
pll_cpu: clock-2000000000-cpu {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <2000000000>;
|
||||
};
|
||||
|
||||
/* pll-cpu derivatives */
|
||||
occ_cpu: clock-2000000000-occ-cpu {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&pll_cpu>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <1>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
|
||||
/* pll-west derivatives */
|
||||
occ_periph_w: clock-200000000 {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&pll_west>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <10>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
uart_clk: clock-200000000-uart {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&occ_periph_w>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <1>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
|
||||
};
|
||||
@ -5,7 +5,7 @@
|
||||
|
||||
#include <dt-bindings/interrupt-controller/mips-gic.h>
|
||||
|
||||
#include "eyeq6h-fixed-clocks.dtsi"
|
||||
#include <dt-bindings/clock/mobileye,eyeq5-clk.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
@ -17,7 +17,7 @@ cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "img,i6500";
|
||||
reg = <0>;
|
||||
clocks = <&occ_cpu>;
|
||||
clocks = <&olb_central EQ6HC_CENTRAL_CPU_OCC>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -32,19 +32,42 @@ cpu_intc: interrupt-controller {
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
xtal: clock-30000000 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <30000000>;
|
||||
};
|
||||
|
||||
soc: soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
olb_acc: system-controller@d2003000 {
|
||||
compatible = "mobileye,eyeq6h-acc-olb", "syscon";
|
||||
reg = <0x0 0xd2003000 0x0 0x1000>;
|
||||
#reset-cells = <1>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&xtal>;
|
||||
clock-names = "ref";
|
||||
};
|
||||
|
||||
olb_central: system-controller@d3100000 {
|
||||
compatible = "mobileye,eyeq6h-central-olb", "syscon";
|
||||
reg = <0x0 0xd3100000 0x0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&xtal>;
|
||||
clock-names = "ref";
|
||||
};
|
||||
|
||||
uart0: serial@d3331000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0 0xd3331000 0x0 0x1000>;
|
||||
reg-io-width = <4>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SHARED 43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&occ_periph_w>, <&occ_periph_w>;
|
||||
clocks = <&olb_west EQ6HC_WEST_PER_UART>, <&olb_west EQ6HC_WEST_PER_OCC>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
@ -56,6 +79,15 @@ pinctrl_west: pinctrl@d3337000 {
|
||||
pinctrl-single,function-mask = <0xffff>;
|
||||
};
|
||||
|
||||
olb_west: system-controller@d3338000 {
|
||||
compatible = "mobileye,eyeq6h-west-olb", "syscon";
|
||||
reg = <0x0 0xd3338000 0x0 0x1000>;
|
||||
#reset-cells = <1>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&xtal>;
|
||||
clock-names = "ref";
|
||||
};
|
||||
|
||||
pinctrl_east: pinctrl@d3357000 {
|
||||
compatible = "pinctrl-single";
|
||||
reg = <0x0 0xd3357000 0x0 0xb0>;
|
||||
@ -64,6 +96,23 @@ pinctrl_east: pinctrl@d3357000 {
|
||||
pinctrl-single,function-mask = <0xffff>;
|
||||
};
|
||||
|
||||
olb_east: system-controller@d3358000 {
|
||||
compatible = "mobileye,eyeq6h-east-olb", "syscon";
|
||||
reg = <0x0 0xd3358000 0x0 0x1000>;
|
||||
#reset-cells = <1>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&xtal>;
|
||||
clock-names = "ref";
|
||||
};
|
||||
|
||||
olb_south: system-controller@d8013000 {
|
||||
compatible = "mobileye,eyeq6h-south-olb", "syscon";
|
||||
reg = <0x0 0xd8013000 0x0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&xtal>;
|
||||
clock-names = "ref";
|
||||
};
|
||||
|
||||
pinctrl_south: pinctrl@d8014000 {
|
||||
compatible = "pinctrl-single";
|
||||
reg = <0x0 0xd8014000 0x0 0xf8>;
|
||||
@ -72,6 +121,22 @@ pinctrl_south: pinctrl@d8014000 {
|
||||
pinctrl-single,function-mask = <0xffff>;
|
||||
};
|
||||
|
||||
olb_ddr0: system-controller@e4080000 {
|
||||
compatible = "mobileye,eyeq6h-ddr0-olb", "syscon";
|
||||
reg = <0x0 0xe4080000 0x0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&xtal>;
|
||||
clock-names = "ref";
|
||||
};
|
||||
|
||||
olb_ddr1: system-controller@e4081000 {
|
||||
compatible = "mobileye,eyeq6h-ddr1-olb", "syscon";
|
||||
reg = <0x0 0xe4081000 0x0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&xtal>;
|
||||
clock-names = "ref";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@f0920000 {
|
||||
compatible = "mti,gic";
|
||||
reg = <0x0 0xf0920000 0x0 0x20000>;
|
||||
@ -89,7 +154,7 @@ gic: interrupt-controller@f0920000 {
|
||||
timer {
|
||||
compatible = "mti,gic-timer";
|
||||
interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
|
||||
clocks = <&occ_cpu>;
|
||||
clocks = <&olb_central EQ6HC_CENTRAL_CPU_OCC>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -61,6 +61,8 @@ i2c1: i2c@388 {
|
||||
};
|
||||
|
||||
&soc {
|
||||
ranges = <0x0 0x18000000 0x20000>;
|
||||
|
||||
intc: interrupt-controller@3000 {
|
||||
compatible = "realtek,rtl9300-intc", "realtek,rtl-intc";
|
||||
reg = <0x3000 0x18>, <0x3018 0x18>;
|
||||
@ -88,6 +90,17 @@ timer0: timer@3200 {
|
||||
interrupts = <7>, <8>, <9>, <10>, <11>;
|
||||
clocks = <&lx_clk>;
|
||||
};
|
||||
|
||||
snand: spi@1a400 {
|
||||
compatible = "realtek,rtl9301-snand";
|
||||
reg = <0x1a400 0x44>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <19>;
|
||||
clocks = <&lx_clk>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user