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- removed AR7 platform support

Browse Source 
- cleanups and fixes
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Merge tag 'mips_6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

Pull MIPS updates from Thomas Bogendoerfer:

 - removed AR7 platform support

 - cleanups and fixes

* tag 'mips_6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux:
  MIPS: AR7: remove platform
  watchdog: ar7_wdt: remove driver to prepare for platform removal
  vlynq: remove bus driver
  mtd: parsers: ar7: remove support
  serial: 8250: remove AR7 support
  arch: mips: remove ReiserFS from defconfig
  MIPS: lantiq: Remove unnecessary include of <linux/of_irq.h>
  MIPS: lantiq: Fix pcibios_plat_dev_init() "no previous prototype" warning
  MIPS: KVM: Fix a build warning about variable set but not used
  MIPS: Remove dead code in relocate_new_kernel
  mips: dts: ralink: mt7621: rename to GnuBee GB-PC1 and GnuBee GB-PC2
  mips: dts: ralink: mt7621: define each reset as an item
  mips: dts: ingenic: Remove unneeded probe-type properties
  MIPS: loongson32: Remove dma.h and nand.h
This commit is contained in:
Linus Torvalds 2023-11-10 09:19:46 -08:00
commit 656d88c3b6
52 changed files with 5 additions and 4033 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
MAINTAINERS
View File

@ -23198,13 +23198,6 @@ W: https://linuxtv.org
T: git git://linuxtv.org/media_tree.git
F: drivers/media/test-drivers/vivid/*
VLYNQ BUS
M: Florian Fainelli <f.fainelli@gmail.com>
L: openwrt-devel@lists.openwrt.org (subscribers-only)
S: Maintained
F: drivers/vlynq/vlynq.c
F: include/linux/vlynq.h
VM SOCKETS (AF_VSOCK)
M: Stefano Garzarella <sgarzare@redhat.com>
L: virtualization@lists.linux.dev

1
arch/arm/configs/pxa_defconfig
View File

@ -100,7 +100,6 @@ CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_CONNECTOR=y
CONFIG_MTD=y
CONFIG_MTD_AR7_PARTS=m
CONFIG_MTD_CMDLINE_PARTS=m
CONFIG_MTD_OF_PARTS=m
CONFIG_MTD_AFS_PARTS=m

1
arch/mips/Kbuild.platforms
View File

@ -2,7 +2,6 @@
# All platforms listed in alphabetic order
platform-$(CONFIG_MIPS_ALCHEMY) += alchemy/
platform-$(CONFIG_AR7) += ar7/
platform-$(CONFIG_ATH25) += ath25/
platform-$(CONFIG_ATH79) += ath79/
platform-$(CONFIG_BCM47XX) += bcm47xx/

22
arch/mips/Kconfig
View File

@ -202,28 +202,6 @@ config MIPS_ALCHEMY
select SYS_SUPPORTS_ZBOOT
select COMMON_CLK
config AR7
bool "Texas Instruments AR7"
select BOOT_ELF32
select COMMON_CLK
select DMA_NONCOHERENT
select CEVT_R4K
select CSRC_R4K
select IRQ_MIPS_CPU
select NO_EXCEPT_FILL
select SWAP_IO_SPACE
select SYS_HAS_CPU_MIPS32_R1
select SYS_HAS_EARLY_PRINTK
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_MIPS16
select SYS_SUPPORTS_ZBOOT_UART16550
select GPIOLIB
select VLYNQ
help
Support for the Texas Instruments AR7 System-on-a-Chip
family: TNETD7100, 7200 and 7300.
config ATH25
bool "Atheros AR231x/AR531x SoC support"
select CEVT_R4K

11
arch/mips/ar7/Makefile
View File

@ -1,11 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
obj-y := \
prom.o \
setup.o \
memory.o \
irq.o \
time.o \
platform.o \
gpio.o \
clock.o

5
arch/mips/ar7/Platform
View File

@ -1,5 +0,0 @@
#
# Texas Instruments AR7
#
cflags-$(CONFIG_AR7) += -I$(srctree)/arch/mips/include/asm/mach-ar7
load-$(CONFIG_AR7) += 0xffffffff94100000

439
arch/mips/ar7/clock.c
View File

@ -1,439 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
* Copyright (C) 2007 Eugene Konev <ejka@openwrt.org>
* Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/export.h>
#include <linux/delay.h>
#include <linux/gcd.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/clkdev.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <asm/addrspace.h>
#include <asm/mach-ar7/ar7.h>
#define BOOT_PLL_SOURCE_MASK 0x3
#define CPU_PLL_SOURCE_SHIFT 16
#define BUS_PLL_SOURCE_SHIFT 14
#define USB_PLL_SOURCE_SHIFT 18
#define DSP_PLL_SOURCE_SHIFT 22
#define BOOT_PLL_SOURCE_AFE 0
#define BOOT_PLL_SOURCE_BUS 0
#define BOOT_PLL_SOURCE_REF 1
#define BOOT_PLL_SOURCE_XTAL 2
#define BOOT_PLL_SOURCE_CPU 3
#define BOOT_PLL_BYPASS 0x00000020
#define BOOT_PLL_ASYNC_MODE 0x02000000
#define BOOT_PLL_2TO1_MODE 0x00008000
#define TNETD7200_CLOCK_ID_CPU 0
#define TNETD7200_CLOCK_ID_DSP 1
#define TNETD7200_CLOCK_ID_USB 2
#define TNETD7200_DEF_CPU_CLK 211000000
#define TNETD7200_DEF_DSP_CLK 125000000
#define TNETD7200_DEF_USB_CLK 48000000
struct tnetd7300_clock {
u32 ctrl;
#define PREDIV_MASK 0x001f0000
#define PREDIV_SHIFT 16
#define POSTDIV_MASK 0x0000001f
u32 unused1[3];
u32 pll;
#define MUL_MASK 0x0000f000
#define MUL_SHIFT 12
#define PLL_MODE_MASK 0x00000001
#define PLL_NDIV 0x00000800
#define PLL_DIV 0x00000002
#define PLL_STATUS 0x00000001
u32 unused2[3];
};
struct tnetd7300_clocks {
struct tnetd7300_clock bus;
struct tnetd7300_clock cpu;
struct tnetd7300_clock usb;
struct tnetd7300_clock dsp;
};
struct tnetd7200_clock {
u32 ctrl;
u32 unused1[3];
#define DIVISOR_ENABLE_MASK 0x00008000
u32 mul;
u32 prediv;
u32 postdiv;
u32 postdiv2;
u32 unused2[6];
u32 cmd;
u32 status;
u32 cmden;
u32 padding[15];
};
struct tnetd7200_clocks {
struct tnetd7200_clock cpu;
struct tnetd7200_clock dsp;
struct tnetd7200_clock usb;
};
struct clk_rate {
u32 rate;
};
static struct clk_rate bus_clk = {
.rate = 125000000,
};
static struct clk_rate cpu_clk = {
.rate = 150000000,
};
static void approximate(int base, int target, int *prediv,
int *postdiv, int *mul)
{
int i, j, k, freq, res = target;
for (i = 1; i <= 16; i++)
for (j = 1; j <= 32; j++)
for (k = 1; k <= 32; k++) {
freq = abs(base / j * i / k - target);
if (freq < res) {
res = freq;
*mul = i;
*prediv = j;
*postdiv = k;
}
}
}
static void calculate(int base, int target, int *prediv, int *postdiv,
int *mul)
{
int tmp_gcd, tmp_base, tmp_freq;
for (*prediv = 1; *prediv <= 32; (*prediv)++) {
tmp_base = base / *prediv;
tmp_gcd = gcd(target, tmp_base);
*mul = target / tmp_gcd;
*postdiv = tmp_base / tmp_gcd;
if ((*mul < 1) || (*mul >= 16))
continue;
if ((*postdiv > 0) & (*postdiv <= 32))
break;
}
if (base / *prediv * *mul / *postdiv != target) {
approximate(base, target, prediv, postdiv, mul);
tmp_freq = base / *prediv * *mul / *postdiv;
printk(KERN_WARNING
"Adjusted requested frequency %d to %d\n",
target, tmp_freq);
}
printk(KERN_DEBUG "Clocks: prediv: %d, postdiv: %d, mul: %d\n",
*prediv, *postdiv, *mul);
}
static int tnetd7300_dsp_clock(void)
{
u32 didr1, didr2;
u8 rev = ar7_chip_rev();
didr1 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x18));
didr2 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x1c));
if (didr2 & (1 << 23))
return 0;
if ((rev >= 0x23) && (rev != 0x57))
return 250000000;
if ((((didr2 & 0x1fff) << 10) | ((didr1 & 0xffc00000) >> 22))
> 4208000)
return 250000000;
return 0;
}
static int tnetd7300_get_clock(u32 shift, struct tnetd7300_clock *clock,
u32 *bootcr, u32 bus_clock)
{
int product;
int base_clock = AR7_REF_CLOCK;
u32 ctrl = readl(&clock->ctrl);
u32 pll = readl(&clock->pll);
int prediv = ((ctrl & PREDIV_MASK) >> PREDIV_SHIFT) + 1;
int postdiv = (ctrl & POSTDIV_MASK) + 1;
int divisor = prediv * postdiv;
int mul = ((pll & MUL_MASK) >> MUL_SHIFT) + 1;
switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
case BOOT_PLL_SOURCE_BUS:
base_clock = bus_clock;
break;
case BOOT_PLL_SOURCE_REF:
base_clock = AR7_REF_CLOCK;
break;
case BOOT_PLL_SOURCE_XTAL:
base_clock = AR7_XTAL_CLOCK;
break;
case BOOT_PLL_SOURCE_CPU:
base_clock = cpu_clk.rate;
break;
}
if (*bootcr & BOOT_PLL_BYPASS)
return base_clock / divisor;
if ((pll & PLL_MODE_MASK) == 0)
return (base_clock >> (mul / 16 + 1)) / divisor;
if ((pll & (PLL_NDIV | PLL_DIV)) == (PLL_NDIV | PLL_DIV)) {
product = (mul & 1) ?
(base_clock * mul) >> 1 :
(base_clock * (mul - 1)) >> 2;
return product / divisor;
}
if (mul == 16)
return base_clock / divisor;
return base_clock * mul / divisor;
}
static void tnetd7300_set_clock(u32 shift, struct tnetd7300_clock *clock,
u32 *bootcr, u32 frequency)
{
int prediv, postdiv, mul;
int base_clock = bus_clk.rate;
switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
case BOOT_PLL_SOURCE_BUS:
base_clock = bus_clk.rate;
break;
case BOOT_PLL_SOURCE_REF:
base_clock = AR7_REF_CLOCK;
break;
case BOOT_PLL_SOURCE_XTAL:
base_clock = AR7_XTAL_CLOCK;
break;
case BOOT_PLL_SOURCE_CPU:
base_clock = cpu_clk.rate;
break;
}
calculate(base_clock, frequency, &prediv, &postdiv, &mul);
writel(((prediv - 1) << PREDIV_SHIFT) | (postdiv - 1), &clock->ctrl);
mdelay(1);
writel(4, &clock->pll);
while (readl(&clock->pll) & PLL_STATUS)
;
writel(((mul - 1) << MUL_SHIFT) | (0xff << 3) | 0x0e, &clock->pll);
mdelay(75);
}
static void __init tnetd7300_init_clocks(void)
{
u32 *bootcr = (u32 *)ioremap(AR7_REGS_DCL, 4);
struct tnetd7300_clocks *clocks =
ioremap(UR8_REGS_CLOCKS,
sizeof(struct tnetd7300_clocks));
u32 dsp_clk;
struct clk *clk;
bus_clk.rate = tnetd7300_get_clock(BUS_PLL_SOURCE_SHIFT,
&clocks->bus, bootcr, AR7_AFE_CLOCK);
if (*bootcr & BOOT_PLL_ASYNC_MODE)
cpu_clk.rate = tnetd7300_get_clock(CPU_PLL_SOURCE_SHIFT,
&clocks->cpu, bootcr, AR7_AFE_CLOCK);
else
cpu_clk.rate = bus_clk.rate;
dsp_clk = tnetd7300_dsp_clock();
if (dsp_clk == 250000000)
tnetd7300_set_clock(DSP_PLL_SOURCE_SHIFT, &clocks->dsp,
bootcr, dsp_clk);
iounmap(clocks);
iounmap(bootcr);
clk = clk_register_fixed_rate(NULL, "cpu", NULL, 0, cpu_clk.rate);
clkdev_create(clk, "cpu", NULL);
clk = clk_register_fixed_rate(NULL, "dsp", NULL, 0, dsp_clk);
clkdev_create(clk, "dsp", NULL);
}
static void tnetd7200_set_clock(int base, struct tnetd7200_clock *clock,
int prediv, int postdiv, int postdiv2, int mul, u32 frequency)
{
printk(KERN_INFO
"Clocks: base = %d, frequency = %u, prediv = %d, "
"postdiv = %d, postdiv2 = %d, mul = %d\n",
base, frequency, prediv, postdiv, postdiv2, mul);
writel(0, &clock->ctrl);
writel(DIVISOR_ENABLE_MASK | ((prediv - 1) & 0x1F), &clock->prediv);
writel((mul - 1) & 0xF, &clock->mul);
while (readl(&clock->status) & 0x1)
; /* nop */
writel(DIVISOR_ENABLE_MASK | ((postdiv - 1) & 0x1F), &clock->postdiv);
writel(readl(&clock->cmden) | 1, &clock->cmden);
writel(readl(&clock->cmd) | 1, &clock->cmd);
while (readl(&clock->status) & 0x1)
; /* nop */
writel(DIVISOR_ENABLE_MASK | ((postdiv2 - 1) & 0x1F), &clock->postdiv2);
writel(readl(&clock->cmden) | 1, &clock->cmden);
writel(readl(&clock->cmd) | 1, &clock->cmd);
while (readl(&clock->status) & 0x1)
; /* nop */
writel(readl(&clock->ctrl) | 1, &clock->ctrl);
}
static int tnetd7200_get_clock_base(int clock_id, u32 *bootcr)
{
if (*bootcr & BOOT_PLL_ASYNC_MODE)
/* Async */
switch (clock_id) {
case TNETD7200_CLOCK_ID_DSP:
return AR7_REF_CLOCK;
default:
return AR7_AFE_CLOCK;
}
else
/* Sync */
if (*bootcr & BOOT_PLL_2TO1_MODE)
/* 2:1 */
switch (clock_id) {
case TNETD7200_CLOCK_ID_DSP:
return AR7_REF_CLOCK;
default:
return AR7_AFE_CLOCK;
}
else
/* 1:1 */
return AR7_REF_CLOCK;
}
static void __init tnetd7200_init_clocks(void)
{
u32 *bootcr = (u32 *)ioremap(AR7_REGS_DCL, 4);
struct tnetd7200_clocks *clocks =
ioremap(AR7_REGS_CLOCKS,
sizeof(struct tnetd7200_clocks));
int cpu_base, cpu_mul, cpu_prediv, cpu_postdiv;
int dsp_base, dsp_mul, dsp_prediv, dsp_postdiv;
int usb_base, usb_mul, usb_prediv, usb_postdiv;
struct clk *clk;
cpu_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_CPU, bootcr);
dsp_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_DSP, bootcr);
if (*bootcr & BOOT_PLL_ASYNC_MODE) {
printk(KERN_INFO "Clocks: Async mode\n");
printk(KERN_INFO "Clocks: Setting DSP clock\n");
calculate(dsp_base, TNETD7200_DEF_DSP_CLK,
&dsp_prediv, &dsp_postdiv, &dsp_mul);
bus_clk.rate =
((dsp_base / dsp_prediv) * dsp_mul) / dsp_postdiv;
tnetd7200_set_clock(dsp_base, &clocks->dsp,
dsp_prediv, dsp_postdiv * 2, dsp_postdiv, dsp_mul * 2,
bus_clk.rate);
printk(KERN_INFO "Clocks: Setting CPU clock\n");
calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv,
&cpu_postdiv, &cpu_mul);
cpu_clk.rate =
((cpu_base / cpu_prediv) * cpu_mul) / cpu_postdiv;
tnetd7200_set_clock(cpu_base, &clocks->cpu,
cpu_prediv, cpu_postdiv, -1, cpu_mul,
cpu_clk.rate);
} else
if (*bootcr & BOOT_PLL_2TO1_MODE) {
printk(KERN_INFO "Clocks: Sync 2:1 mode\n");
printk(KERN_INFO "Clocks: Setting CPU clock\n");
calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv,
&cpu_postdiv, &cpu_mul);
cpu_clk.rate = ((cpu_base / cpu_prediv) * cpu_mul)
/ cpu_postdiv;
tnetd7200_set_clock(cpu_base, &clocks->cpu,
cpu_prediv, cpu_postdiv, -1, cpu_mul,
cpu_clk.rate);
printk(KERN_INFO "Clocks: Setting DSP clock\n");
calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv,
&dsp_postdiv, &dsp_mul);
bus_clk.rate = cpu_clk.rate / 2;
tnetd7200_set_clock(dsp_base, &clocks->dsp,
dsp_prediv, dsp_postdiv * 2, dsp_postdiv,
dsp_mul * 2, bus_clk.rate);
} else {
printk(KERN_INFO "Clocks: Sync 1:1 mode\n");
printk(KERN_INFO "Clocks: Setting DSP clock\n");
calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv,
&dsp_postdiv, &dsp_mul);
bus_clk.rate = ((dsp_base / dsp_prediv) * dsp_mul)
/ dsp_postdiv;
tnetd7200_set_clock(dsp_base, &clocks->dsp,
dsp_prediv, dsp_postdiv * 2, dsp_postdiv,
dsp_mul * 2, bus_clk.rate);
cpu_clk.rate = bus_clk.rate;
}
printk(KERN_INFO "Clocks: Setting USB clock\n");
usb_base = bus_clk.rate;
calculate(usb_base, TNETD7200_DEF_USB_CLK, &usb_prediv,
&usb_postdiv, &usb_mul);
tnetd7200_set_clock(usb_base, &clocks->usb,
usb_prediv, usb_postdiv, -1, usb_mul,
TNETD7200_DEF_USB_CLK);
iounmap(clocks);
iounmap(bootcr);
clk = clk_register_fixed_rate(NULL, "cpu", NULL, 0, cpu_clk.rate);
clkdev_create(clk, "cpu", NULL);
clkdev_create(clk, "dsp", NULL);
}
void __init ar7_init_clocks(void)
{
struct clk *clk;
switch (ar7_chip_id()) {
case AR7_CHIP_7100:
case AR7_CHIP_7200:
tnetd7200_init_clocks();
break;
case AR7_CHIP_7300:
tnetd7300_init_clocks();
break;
default:
break;
}
clk = clk_register_fixed_rate(NULL, "bus", NULL, 0, bus_clk.rate);
clkdev_create(clk, "bus", NULL);
/* adjust vbus clock rate */
clk = clk_register_fixed_factor(NULL, "vbus", "bus", 0, 1, 2);
clkdev_create(clk, "vbus", NULL);
clkdev_create(clk, "cpmac", "cpmac.1");
clkdev_create(clk, "cpmac", "cpmac.1");
}

332
arch/mips/ar7/gpio.c
View File

@ -1,332 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
* Copyright (C) 2007 Eugene Konev <ejka@openwrt.org>
* Copyright (C) 2009-2010 Florian Fainelli <florian@openwrt.org>
*/
#include <linux/init.h>
#include <linux/export.h>
#include <linux/gpio/driver.h>
#include <asm/mach-ar7/ar7.h>
#define AR7_GPIO_MAX 32
#define TITAN_GPIO_MAX 51
struct ar7_gpio_chip {
void __iomem *regs;
struct gpio_chip chip;
};
static int ar7_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
{
struct ar7_gpio_chip *gpch = gpiochip_get_data(chip);
void __iomem *gpio_in = gpch->regs + AR7_GPIO_INPUT;
return !!(readl(gpio_in) & (1 << gpio));
}
static int titan_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
{
struct ar7_gpio_chip *gpch = gpiochip_get_data(chip);
void __iomem *gpio_in0 = gpch->regs + TITAN_GPIO_INPUT_0;
void __iomem *gpio_in1 = gpch->regs + TITAN_GPIO_INPUT_1;
return readl(gpio >> 5 ? gpio_in1 : gpio_in0) & (1 << (gpio & 0x1f));
}
static void ar7_gpio_set_value(struct gpio_chip *chip,
unsigned gpio, int value)
{
struct ar7_gpio_chip *gpch = gpiochip_get_data(chip);
void __iomem *gpio_out = gpch->regs + AR7_GPIO_OUTPUT;
unsigned tmp;
tmp = readl(gpio_out) & ~(1 << gpio);
if (value)
tmp |= 1 << gpio;
writel(tmp, gpio_out);
}
static void titan_gpio_set_value(struct gpio_chip *chip,
unsigned gpio, int value)
{
struct ar7_gpio_chip *gpch = gpiochip_get_data(chip);
void __iomem *gpio_out0 = gpch->regs + TITAN_GPIO_OUTPUT_0;
void __iomem *gpio_out1 = gpch->regs + TITAN_GPIO_OUTPUT_1;
unsigned tmp;
tmp = readl(gpio >> 5 ? gpio_out1 : gpio_out0) & ~(1 << (gpio & 0x1f));
if (value)
tmp |= 1 << (gpio & 0x1f);
writel(tmp, gpio >> 5 ? gpio_out1 : gpio_out0);
}
static int ar7_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
{
struct ar7_gpio_chip *gpch = gpiochip_get_data(chip);
void __iomem *gpio_dir = gpch->regs + AR7_GPIO_DIR;
writel(readl(gpio_dir) | (1 << gpio), gpio_dir);
return 0;
}
static int titan_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
{
struct ar7_gpio_chip *gpch = gpiochip_get_data(chip);
void __iomem *gpio_dir0 = gpch->regs + TITAN_GPIO_DIR_0;
void __iomem *gpio_dir1 = gpch->regs + TITAN_GPIO_DIR_1;
if (gpio >= TITAN_GPIO_MAX)
return -EINVAL;
writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) | (1 << (gpio & 0x1f)),
gpio >> 5 ? gpio_dir1 : gpio_dir0);
return 0;
}
static int ar7_gpio_direction_output(struct gpio_chip *chip,
unsigned gpio, int value)
{
struct ar7_gpio_chip *gpch = gpiochip_get_data(chip);
void __iomem *gpio_dir = gpch->regs + AR7_GPIO_DIR;
ar7_gpio_set_value(chip, gpio, value);
writel(readl(gpio_dir) & ~(1 << gpio), gpio_dir);
return 0;
}
static int titan_gpio_direction_output(struct gpio_chip *chip,
unsigned gpio, int value)
{
struct ar7_gpio_chip *gpch = gpiochip_get_data(chip);
void __iomem *gpio_dir0 = gpch->regs + TITAN_GPIO_DIR_0;
void __iomem *gpio_dir1 = gpch->regs + TITAN_GPIO_DIR_1;
if (gpio >= TITAN_GPIO_MAX)
return -EINVAL;
titan_gpio_set_value(chip, gpio, value);
writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) & ~(1 <<
(gpio & 0x1f)), gpio >> 5 ? gpio_dir1 : gpio_dir0);
return 0;
}
static struct ar7_gpio_chip ar7_gpio_chip = {
.chip = {
.label = "ar7-gpio",
.direction_input = ar7_gpio_direction_input,
.direction_output = ar7_gpio_direction_output,
.set = ar7_gpio_set_value,
.get = ar7_gpio_get_value,
.base = 0,
.ngpio = AR7_GPIO_MAX,
}
};
static struct ar7_gpio_chip titan_gpio_chip = {
.chip = {
.label = "titan-gpio",
.direction_input = titan_gpio_direction_input,
.direction_output = titan_gpio_direction_output,
.set = titan_gpio_set_value,
.get = titan_gpio_get_value,
.base = 0,
.ngpio = TITAN_GPIO_MAX,
}
};
static inline int ar7_gpio_enable_ar7(unsigned gpio)
{
void __iomem *gpio_en = ar7_gpio_chip.regs + AR7_GPIO_ENABLE;
writel(readl(gpio_en) | (1 << gpio), gpio_en);
return 0;
}
static inline int ar7_gpio_enable_titan(unsigned gpio)
{
void __iomem *gpio_en0 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_0;
void __iomem *gpio_en1 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_1;
writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) | (1 << (gpio & 0x1f)),
gpio >> 5 ? gpio_en1 : gpio_en0);
return 0;
}
int ar7_gpio_enable(unsigned gpio)
{
return ar7_is_titan() ? ar7_gpio_enable_titan(gpio) :
ar7_gpio_enable_ar7(gpio);
}
EXPORT_SYMBOL(ar7_gpio_enable);
static inline int ar7_gpio_disable_ar7(unsigned gpio)
{
void __iomem *gpio_en = ar7_gpio_chip.regs + AR7_GPIO_ENABLE;
writel(readl(gpio_en) & ~(1 << gpio), gpio_en);
return 0;
}
static inline int ar7_gpio_disable_titan(unsigned gpio)
{
void __iomem *gpio_en0 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_0;
void __iomem *gpio_en1 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_1;
writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) & ~(1 << (gpio & 0x1f)),
gpio >> 5 ? gpio_en1 : gpio_en0);
return 0;
}
int ar7_gpio_disable(unsigned gpio)
{
return ar7_is_titan() ? ar7_gpio_disable_titan(gpio) :
ar7_gpio_disable_ar7(gpio);
}
EXPORT_SYMBOL(ar7_gpio_disable);
struct titan_gpio_cfg {
u32 reg;
u32 shift;
u32 func;
};
static const struct titan_gpio_cfg titan_gpio_table[] = {
/* reg, start bit, mux value */
{4, 24, 1},
{4, 26, 1},
{4, 28, 1},
{4, 30, 1},
{5, 6, 1},
{5, 8, 1},
{5, 10, 1},
{5, 12, 1},
{7, 14, 3},
{7, 16, 3},
{7, 18, 3},
{7, 20, 3},
{7, 22, 3},
{7, 26, 3},
{7, 28, 3},
{7, 30, 3},
{8, 0, 3},
{8, 2, 3},
{8, 4, 3},
{8, 10, 3},
{8, 14, 3},
{8, 16, 3},
{8, 18, 3},
{8, 20, 3},
{9, 8, 3},
{9, 10, 3},
{9, 12, 3},
{9, 14, 3},
{9, 18, 3},
{9, 20, 3},
{9, 24, 3},
{9, 26, 3},
{9, 28, 3},
{9, 30, 3},
{10, 0, 3},
{10, 2, 3},
{10, 8, 3},
{10, 10, 3},
{10, 12, 3},
{10, 14, 3},
{13, 12, 3},
{13, 14, 3},
{13, 16, 3},
{13, 18, 3},
{13, 24, 3},
{13, 26, 3},
{13, 28, 3},
{13, 30, 3},
{14, 2, 3},
{14, 6, 3},
{14, 8, 3},
{14, 12, 3}
};
static int titan_gpio_pinsel(unsigned gpio)
{
struct titan_gpio_cfg gpio_cfg;
u32 mux_status, pin_sel_reg, tmp;
void __iomem *pin_sel = (void __iomem *)KSEG1ADDR(AR7_REGS_PINSEL);
if (gpio >= ARRAY_SIZE(titan_gpio_table))
return -EINVAL;
gpio_cfg = titan_gpio_table[gpio];
pin_sel_reg = gpio_cfg.reg - 1;
mux_status = (readl(pin_sel + pin_sel_reg) >> gpio_cfg.shift) & 0x3;
/* Check the mux status */
if (!((mux_status == 0) || (mux_status == gpio_cfg.func)))
return 0;
/* Set the pin sel value */
tmp = readl(pin_sel + pin_sel_reg);
tmp |= ((gpio_cfg.func & 0x3) << gpio_cfg.shift);
writel(tmp, pin_sel + pin_sel_reg);
return 0;
}
/* Perform minimal Titan GPIO configuration */
static void titan_gpio_init(void)
{
unsigned i;
for (i = 44; i < 48; i++) {
titan_gpio_pinsel(i);
ar7_gpio_enable_titan(i);
titan_gpio_direction_input(&titan_gpio_chip.chip, i);
}
}
int __init ar7_gpio_init(void)
{
int ret;
struct ar7_gpio_chip *gpch;
unsigned size;
if (!ar7_is_titan()) {
gpch = &ar7_gpio_chip;
size = 0x10;
} else {
gpch = &titan_gpio_chip;
size = 0x1f;
}
gpch->regs = ioremap(AR7_REGS_GPIO, size);
if (!gpch->regs) {
printk(KERN_ERR "%s: failed to ioremap regs\n",
gpch->chip.label);
return -ENOMEM;
}
ret = gpiochip_add_data(&gpch->chip, gpch);
if (ret) {
printk(KERN_ERR "%s: failed to add gpiochip\n",
gpch->chip.label);
iounmap(gpch->regs);
return ret;
}
printk(KERN_INFO "%s: registered %d GPIOs\n",
gpch->chip.label, gpch->chip.ngpio);
if (ar7_is_titan())
titan_gpio_init();
return ret;
}

165
arch/mips/ar7/irq.c
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@ -1,165 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org>
* Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org>
*/
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
#include <asm/mach-ar7/ar7.h>
#define EXCEPT_OFFSET 0x80
#define PACE_OFFSET 0xA0
#define CHNLS_OFFSET 0x200
#define REG_OFFSET(irq, reg) ((irq) / 32 * 0x4 + reg * 0x10)
#define SEC_REG_OFFSET(reg) (EXCEPT_OFFSET + reg * 0x8)
#define SEC_SR_OFFSET (SEC_REG_OFFSET(0)) /* 0x80 */
#define CR_OFFSET(irq) (REG_OFFSET(irq, 1)) /* 0x10 */
#define SEC_CR_OFFSET (SEC_REG_OFFSET(1)) /* 0x88 */
#define ESR_OFFSET(irq) (REG_OFFSET(irq, 2)) /* 0x20 */
#define SEC_ESR_OFFSET (SEC_REG_OFFSET(2)) /* 0x90 */
#define ECR_OFFSET(irq) (REG_OFFSET(irq, 3)) /* 0x30 */
#define SEC_ECR_OFFSET (SEC_REG_OFFSET(3)) /* 0x98 */
#define PIR_OFFSET (0x40)
#define MSR_OFFSET (0x44)
#define PM_OFFSET(irq) (REG_OFFSET(irq, 5)) /* 0x50 */
#define TM_OFFSET(irq) (REG_OFFSET(irq, 6)) /* 0x60 */
#define REG(addr) ((u32 *)(KSEG1ADDR(AR7_REGS_IRQ) + addr))
#define CHNL_OFFSET(chnl) (CHNLS_OFFSET + (chnl * 4))
static int ar7_irq_base;
static void ar7_unmask_irq(struct irq_data *d)
{
writel(1 << ((d->irq - ar7_irq_base) % 32),
REG(ESR_OFFSET(d->irq - ar7_irq_base)));
}
static void ar7_mask_irq(struct irq_data *d)
{
writel(1 << ((d->irq - ar7_irq_base) % 32),
REG(ECR_OFFSET(d->irq - ar7_irq_base)));
}
static void ar7_ack_irq(struct irq_data *d)
{
writel(1 << ((d->irq - ar7_irq_base) % 32),
REG(CR_OFFSET(d->irq - ar7_irq_base)));
}
static void ar7_unmask_sec_irq(struct irq_data *d)
{
writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET));
}
static void ar7_mask_sec_irq(struct irq_data *d)
{
writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET));
}
static void ar7_ack_sec_irq(struct irq_data *d)
{
writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET));
}
static struct irq_chip ar7_irq_type = {
.name = "AR7",
.irq_unmask = ar7_unmask_irq,
.irq_mask = ar7_mask_irq,
.irq_ack = ar7_ack_irq
};
static struct irq_chip ar7_sec_irq_type = {
.name = "AR7",
.irq_unmask = ar7_unmask_sec_irq,
.irq_mask = ar7_mask_sec_irq,
.irq_ack = ar7_ack_sec_irq,
};
static void __init ar7_irq_init(int base)
{
int i;
/*
* Disable interrupts and clear pending
*/
writel(0xffffffff, REG(ECR_OFFSET(0)));
writel(0xff, REG(ECR_OFFSET(32)));
writel(0xffffffff, REG(SEC_ECR_OFFSET));
writel(0xffffffff, REG(CR_OFFSET(0)));
writel(0xff, REG(CR_OFFSET(32)));
writel(0xffffffff, REG(SEC_CR_OFFSET));
ar7_irq_base = base;
for (i = 0; i < 40; i++) {
writel(i, REG(CHNL_OFFSET(i)));
/* Primary IRQ's */
irq_set_chip_and_handler(base + i, &ar7_irq_type,
handle_level_irq);
/* Secondary IRQ's */
if (i < 32)
irq_set_chip_and_handler(base + i + 40,
&ar7_sec_irq_type,
handle_level_irq);
}
if (request_irq(2, no_action, IRQF_NO_THREAD, "AR7 cascade interrupt",
NULL))
pr_err("Failed to request irq 2 (AR7 cascade interrupt)\n");
if (request_irq(ar7_irq_base, no_action, IRQF_NO_THREAD,
"AR7 cascade interrupt", NULL)) {
pr_err("Failed to request irq %d (AR7 cascade interrupt)\n",
ar7_irq_base);
}
set_c0_status(IE_IRQ0);
}
void __init arch_init_irq(void)
{
mips_cpu_irq_init();
ar7_irq_init(8);
}
static void ar7_cascade(void)
{
u32 status;
int i, irq;
/* Primary IRQ's */
irq = readl(REG(PIR_OFFSET)) & 0x3f;
if (irq) {
do_IRQ(ar7_irq_base + irq);
return;
}
/* Secondary IRQ's are cascaded through primary '0' */
writel(1, REG(CR_OFFSET(irq)));
status = readl(REG(SEC_SR_OFFSET));
for (i = 0; i < 32; i++) {
if (status & 1) {
do_IRQ(ar7_irq_base + i + 40);
return;
}
status >>= 1;
}
spurious_interrupt();
}
asmlinkage void plat_irq_dispatch(void)
{
unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
if (pending & STATUSF_IP7) /* cpu timer */
do_IRQ(7);
else if (pending & STATUSF_IP2) /* int0 hardware line */
ar7_cascade();
else
spurious_interrupt();
}

51
arch/mips/ar7/memory.c
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@ -1,51 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
* Copyright (C) 2007 Eugene Konev <ejka@openwrt.org>
*/
#include <linux/memblock.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/pfn.h>
#include <linux/proc_fs.h>
#include <linux/string.h>
#include <linux/swap.h>
#include <asm/bootinfo.h>
#include <asm/page.h>
#include <asm/sections.h>
#include <asm/mach-ar7/ar7.h>
static int __init memsize(void)
{
u32 size = (64 << 20);
u32 *addr = (u32 *)KSEG1ADDR(AR7_SDRAM_BASE + size - 4);
u32 *kernel_end = (u32 *)KSEG1ADDR(CPHYSADDR((u32)&_end));
u32 *tmpaddr = addr;
while (tmpaddr > kernel_end) {
*tmpaddr = (u32)tmpaddr;
size >>= 1;
tmpaddr -= size >> 2;
}
do {
tmpaddr += size >> 2;
if (*tmpaddr != (u32)tmpaddr)
break;
size <<= 1;
} while (size < (64 << 20));
writel((u32)tmpaddr, &addr);
return size;
}
void __init prom_meminit(void)
{
unsigned long pages;
pages = memsize() >> PAGE_SHIFT;
memblock_add(PHYS_OFFSET, pages << PAGE_SHIFT);
}

722
arch/mips/ar7/platform.c
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@ -1,722 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org>
* Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org>
*/
#include <linux/init.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/serial.h>
#include <linux/serial_8250.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/vlynq.h>
#include <linux/leds.h>
#include <linux/string.h>
#include <linux/etherdevice.h>
#include <linux/phy.h>
#include <linux/phy_fixed.h>
#include <linux/gpio.h>
#include <linux/clk.h>
#include <asm/addrspace.h>
#include <asm/mach-ar7/ar7.h>
#include <asm/mach-ar7/prom.h>
/*****************************************************************************
* VLYNQ Bus
****************************************************************************/
struct plat_vlynq_data {
struct plat_vlynq_ops ops;
int gpio_bit;
int reset_bit;
};
static int vlynq_on(struct vlynq_device *dev)
{
int ret;
struct plat_vlynq_data *pdata = dev->dev.platform_data;
ret = gpio_request(pdata->gpio_bit, "vlynq");
if (ret)
goto out;
ar7_device_reset(pdata->reset_bit);
ret = ar7_gpio_disable(pdata->gpio_bit);
if (ret)
goto out_enabled;
ret = ar7_gpio_enable(pdata->gpio_bit);
if (ret)
goto out_enabled;
ret = gpio_direction_output(pdata->gpio_bit, 0);
if (ret)
goto out_gpio_enabled;
msleep(50);
gpio_set_value(pdata->gpio_bit, 1);
msleep(50);
return 0;
out_gpio_enabled:
ar7_gpio_disable(pdata->gpio_bit);
out_enabled:
ar7_device_disable(pdata->reset_bit);
gpio_free(pdata->gpio_bit);
out:
return ret;
}
static void vlynq_off(struct vlynq_device *dev)
{
struct plat_vlynq_data *pdata = dev->dev.platform_data;
ar7_gpio_disable(pdata->gpio_bit);
gpio_free(pdata->gpio_bit);
ar7_device_disable(pdata->reset_bit);
}
static struct resource vlynq_low_res[] = {
{
.name = "regs",
.flags = IORESOURCE_MEM,
.start = AR7_REGS_VLYNQ0,
.end = AR7_REGS_VLYNQ0 + 0xff,
},
{
.name = "irq",
.flags = IORESOURCE_IRQ,
.start = 29,
.end = 29,
},
{
.name = "mem",
.flags = IORESOURCE_MEM,
.start = 0x04000000,
.end = 0x04ffffff,
},
{
.name = "devirq",
.flags = IORESOURCE_IRQ,
.start = 80,
.end = 111,
},
};
static struct resource vlynq_high_res[] = {
{
.name = "regs",
.flags = IORESOURCE_MEM,
.start = AR7_REGS_VLYNQ1,
.end = AR7_REGS_VLYNQ1 + 0xff,
},
{
.name = "irq",
.flags = IORESOURCE_IRQ,
.start = 33,
.end = 33,
},
{
.name = "mem",
.flags = IORESOURCE_MEM,
.start = 0x0c000000,
.end = 0x0cffffff,
},
{
.name = "devirq",
.flags = IORESOURCE_IRQ,
.start = 112,
.end = 143,
},
};
static struct plat_vlynq_data vlynq_low_data = {
.ops = {
.on = vlynq_on,
.off = vlynq_off,
},
.reset_bit = 20,
.gpio_bit = 18,
};
static struct plat_vlynq_data vlynq_high_data = {
.ops = {
.on = vlynq_on,
.off = vlynq_off,
},
.reset_bit = 16,
.gpio_bit = 19,
};
static struct platform_device vlynq_low = {
.id = 0,
.name = "vlynq",
.dev = {
.platform_data = &vlynq_low_data,
},
.resource = vlynq_low_res,
.num_resources = ARRAY_SIZE(vlynq_low_res),
};
static struct platform_device vlynq_high = {
.id = 1,
.name = "vlynq",
.dev = {
.platform_data = &vlynq_high_data,
},
.resource = vlynq_high_res,
.num_resources = ARRAY_SIZE(vlynq_high_res),
};
/*****************************************************************************
* Flash
****************************************************************************/
static struct resource physmap_flash_resource = {
.name = "mem",
.flags = IORESOURCE_MEM,
.start = 0x10000000,
.end = 0x107fffff,
};
static const char *ar7_probe_types[] = { "ar7part", NULL };
static struct physmap_flash_data physmap_flash_data = {
.width = 2,
.part_probe_types = ar7_probe_types,
};
static struct platform_device physmap_flash = {
.name = "physmap-flash",
.dev = {
.platform_data = &physmap_flash_data,
},
.resource = &physmap_flash_resource,
.num_resources = 1,
};
/*****************************************************************************
* Ethernet
****************************************************************************/
static struct resource cpmac_low_res[] = {
{
.name = "regs",
.flags = IORESOURCE_MEM,
.start = AR7_REGS_MAC0,
.end = AR7_REGS_MAC0 + 0x7ff,
},
{
.name = "irq",
.flags = IORESOURCE_IRQ,
.start = 27,
.end = 27,
},
};
static struct resource cpmac_high_res[] = {
{
.name = "regs",
.flags = IORESOURCE_MEM,
.start = AR7_REGS_MAC1,
.end = AR7_REGS_MAC1 + 0x7ff,
},
{
.name = "irq",
.flags = IORESOURCE_IRQ,
.start = 41,
.end = 41,
},
};
static struct fixed_phy_status fixed_phy_status __initdata = {
.link = 1,
.speed = 100,
.duplex = 1,
};
static struct plat_cpmac_data cpmac_low_data = {
.reset_bit = 17,
.power_bit = 20,
.phy_mask = 0x80000000,
};
static struct plat_cpmac_data cpmac_high_data = {
.reset_bit = 21,
.power_bit = 22,
.phy_mask = 0x7fffffff,
};
static u64 cpmac_dma_mask = DMA_BIT_MASK(32);
static struct platform_device cpmac_low = {
.id = 0,
.name = "cpmac",
.dev = {
.dma_mask = &cpmac_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &cpmac_low_data,
},
.resource = cpmac_low_res,
.num_resources = ARRAY_SIZE(cpmac_low_res),
};
static struct platform_device cpmac_high = {
.id = 1,
.name = "cpmac",
.dev = {
.dma_mask = &cpmac_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &cpmac_high_data,
},
.resource = cpmac_high_res,
.num_resources = ARRAY_SIZE(cpmac_high_res),
};
static void __init cpmac_get_mac(int instance, unsigned char *dev_addr)
{
char name[5], *mac;
sprintf(name, "mac%c", 'a' + instance);
mac = prom_getenv(name);
if (!mac && instance) {
sprintf(name, "mac%c", 'a');
mac = prom_getenv(name);
}
if (mac) {
if (!mac_pton(mac, dev_addr)) {
pr_warn("cannot parse mac address, using random address\n");
eth_random_addr(dev_addr);
}
} else
eth_random_addr(dev_addr);
}
/*****************************************************************************
* USB
****************************************************************************/
static struct resource usb_res[] = {
{
.name = "regs",
.flags = IORESOURCE_MEM,
.start = AR7_REGS_USB,
.end = AR7_REGS_USB + 0xff,
},
{
.name = "irq",
.flags = IORESOURCE_IRQ,
.start = 32,
.end = 32,
},
{
.name = "mem",
.flags = IORESOURCE_MEM,
.start = 0x03400000,
.end = 0x03401fff,
},
};
static struct platform_device ar7_udc = {
.name = "ar7_udc",
.resource = usb_res,
.num_resources = ARRAY_SIZE(usb_res),
};
/*****************************************************************************
* LEDs
****************************************************************************/
static const struct gpio_led default_leds[] = {
{
.name = "status",
.gpio = 8,
.active_low = 1,
},
};
static const struct gpio_led titan_leds[] = {
{ .name = "status", .gpio = 8, .active_low = 1, },
{ .name = "wifi", .gpio = 13, .active_low = 1, },
};
static const struct gpio_led dsl502t_leds[] = {
{
.name = "status",
.gpio = 9,
.active_low = 1,
},
{
.name = "ethernet",
.gpio = 7,
.active_low = 1,
},
{
.name = "usb",
.gpio = 12,
.active_low = 1,
},
};
static const struct gpio_led dg834g_leds[] = {
{
.name = "ppp",
.gpio = 6,
.active_low = 1,
},
{
.name = "status",
.gpio = 7,
.active_low = 1,
},
{
.name = "adsl",
.gpio = 8,
.active_low = 1,
},
{
.name = "wifi",
.gpio = 12,
.active_low = 1,
},
{
.name = "power",
.gpio = 14,
.active_low = 1,
.default_trigger = "default-on",
},
};
static const struct gpio_led fb_sl_leds[] = {
{
.name = "1",
.gpio = 7,
},
{
.name = "2",
.gpio = 13,
.active_low = 1,
},
{
.name = "3",
.gpio = 10,
.active_low = 1,
},
{
.name = "4",
.gpio = 12,
.active_low = 1,
},
{
.name = "5",
.gpio = 9,
.active_low = 1,
},
};
static const struct gpio_led fb_fon_leds[] = {
{
.name = "1",
.gpio = 8,
},
{
.name = "2",
.gpio = 3,
.active_low = 1,
},
{
.name = "3",
.gpio = 5,
},
{
.name = "4",
.gpio = 4,
.active_low = 1,
},
{
.name = "5",
.gpio = 11,
.active_low = 1,
},
};
static const struct gpio_led gt701_leds[] = {
{
.name = "inet:green",
.gpio = 13,
.active_low = 1,
},
{
.name = "usb",
.gpio = 12,
.active_low = 1,
},
{
.name = "inet:red",
.gpio = 9,
.active_low = 1,
},
{
.name = "power:red",
.gpio = 7,
.active_low = 1,
},
{
.name = "power:green",
.gpio = 8,
.active_low = 1,
.default_trigger = "default-on",
},
{
.name = "ethernet",
.gpio = 10,
.active_low = 1,
},
};
static struct gpio_led_platform_data ar7_led_data;
static struct platform_device ar7_gpio_leds = {
.name = "leds-gpio",
.dev = {
.platform_data = &ar7_led_data,
}
};
static void __init detect_leds(void)
{
char *prid, *usb_prod;
/* Default LEDs */
ar7_led_data.num_leds = ARRAY_SIZE(default_leds);
ar7_led_data.leds = default_leds;
/* FIXME: the whole thing is unreliable */
prid = prom_getenv("ProductID");
usb_prod = prom_getenv("usb_prod");
/* If we can't get the product id from PROM, use the default LEDs */
if (!prid)
return;
if (strstr(prid, "Fritz_Box_FON")) {
ar7_led_data.num_leds = ARRAY_SIZE(fb_fon_leds);
ar7_led_data.leds = fb_fon_leds;
} else if (strstr(prid, "Fritz_Box_")) {
ar7_led_data.num_leds = ARRAY_SIZE(fb_sl_leds);
ar7_led_data.leds = fb_sl_leds;
} else if ((!strcmp(prid, "AR7RD") || !strcmp(prid, "AR7DB"))
&& usb_prod != NULL && strstr(usb_prod, "DSL-502T")) {
ar7_led_data.num_leds = ARRAY_SIZE(dsl502t_leds);
ar7_led_data.leds = dsl502t_leds;
} else if (strstr(prid, "DG834")) {
ar7_led_data.num_leds = ARRAY_SIZE(dg834g_leds);
ar7_led_data.leds = dg834g_leds;
} else if (strstr(prid, "CYWM") || strstr(prid, "CYWL")) {
ar7_led_data.num_leds = ARRAY_SIZE(titan_leds);
ar7_led_data.leds = titan_leds;
} else if (strstr(prid, "GT701")) {
ar7_led_data.num_leds = ARRAY_SIZE(gt701_leds);
ar7_led_data.leds = gt701_leds;
}
}
/*****************************************************************************
* Watchdog
****************************************************************************/
static struct resource ar7_wdt_res = {
.name = "regs",
.flags = IORESOURCE_MEM,
.start = -1, /* Filled at runtime */
.end = -1, /* Filled at runtime */
};
static struct platform_device ar7_wdt = {
.name = "ar7_wdt",
.resource = &ar7_wdt_res,
.num_resources = 1,
};
/*****************************************************************************
* Init
****************************************************************************/
static int __init ar7_register_uarts(void)
{
#ifdef CONFIG_SERIAL_8250
static struct uart_port uart_port __initdata;
struct clk *bus_clk;
int res;
memset(&uart_port, 0, sizeof(struct uart_port));
bus_clk = clk_get(NULL, "bus");
if (IS_ERR(bus_clk))
panic("unable to get bus clk");
uart_port.type = PORT_AR7;
uart_port.uartclk = clk_get_rate(bus_clk) / 2;
uart_port.iotype = UPIO_MEM32;
uart_port.flags = UPF_FIXED_TYPE | UPF_BOOT_AUTOCONF;
uart_port.regshift = 2;
uart_port.line = 0;
uart_port.irq = AR7_IRQ_UART0;
uart_port.mapbase = AR7_REGS_UART0;
uart_port.membase = ioremap(uart_port.mapbase, 256);
res = early_serial_setup(&uart_port);
if (res)
return res;
/* Only TNETD73xx have a second serial port */
if (ar7_has_second_uart()) {
uart_port.line = 1;
uart_port.irq = AR7_IRQ_UART1;
uart_port.mapbase = UR8_REGS_UART1;
uart_port.membase = ioremap(uart_port.mapbase, 256);
res = early_serial_setup(&uart_port);
if (res)
return res;
}
#endif
return 0;
}
static void __init titan_fixup_devices(void)
{
/* Set vlynq0 data */
vlynq_low_data.reset_bit = 15;
vlynq_low_data.gpio_bit = 14;
/* Set vlynq1 data */
vlynq_high_data.reset_bit = 16;
vlynq_high_data.gpio_bit = 7;
/* Set vlynq0 resources */
vlynq_low_res[0].start = TITAN_REGS_VLYNQ0;
vlynq_low_res[0].end = TITAN_REGS_VLYNQ0 + 0xff;
vlynq_low_res[1].start = 33;
vlynq_low_res[1].end = 33;
vlynq_low_res[2].start = 0x0c000000;
vlynq_low_res[2].end = 0x0fffffff;
vlynq_low_res[3].start = 80;
vlynq_low_res[3].end = 111;
/* Set vlynq1 resources */
vlynq_high_res[0].start = TITAN_REGS_VLYNQ1;
vlynq_high_res[0].end = TITAN_REGS_VLYNQ1 + 0xff;
vlynq_high_res[1].start = 34;
vlynq_high_res[1].end = 34;
vlynq_high_res[2].start = 0x40000000;
vlynq_high_res[2].end = 0x43ffffff;
vlynq_high_res[3].start = 112;
vlynq_high_res[3].end = 143;
/* Set cpmac0 data */
cpmac_low_data.phy_mask = 0x40000000;
/* Set cpmac1 data */
cpmac_high_data.phy_mask = 0x80000000;
/* Set cpmac0 resources */
cpmac_low_res[0].start = TITAN_REGS_MAC0;
cpmac_low_res[0].end = TITAN_REGS_MAC0 + 0x7ff;
/* Set cpmac1 resources */
cpmac_high_res[0].start = TITAN_REGS_MAC1;
cpmac_high_res[0].end = TITAN_REGS_MAC1 + 0x7ff;
}
static int __init ar7_register_devices(void)
{
void __iomem *bootcr;
u32 val;
int res;
res = ar7_gpio_init();
if (res)
pr_warn("unable to register gpios: %d\n", res);
res = ar7_register_uarts();
if (res)
pr_err("unable to setup uart(s): %d\n", res);
res = platform_device_register(&physmap_flash);
if (res)
pr_warn("unable to register physmap-flash: %d\n", res);
if (ar7_is_titan())
titan_fixup_devices();
ar7_device_disable(vlynq_low_data.reset_bit);
res = platform_device_register(&vlynq_low);
if (res)
pr_warn("unable to register vlynq-low: %d\n", res);
if (ar7_has_high_vlynq()) {
ar7_device_disable(vlynq_high_data.reset_bit);
res = platform_device_register(&vlynq_high);
if (res)
pr_warn("unable to register vlynq-high: %d\n", res);
}
if (ar7_has_high_cpmac()) {
res = fixed_phy_add(PHY_POLL, cpmac_high.id,
&fixed_phy_status);
if (!res) {
cpmac_get_mac(1, cpmac_high_data.dev_addr);
res = platform_device_register(&cpmac_high);
if (res)
pr_warn("unable to register cpmac-high: %d\n",
res);
} else
pr_warn("unable to add cpmac-high phy: %d\n", res);
} else
cpmac_low_data.phy_mask = 0xffffffff;
res = fixed_phy_add(PHY_POLL, cpmac_low.id, &fixed_phy_status);
if (!res) {
cpmac_get_mac(0, cpmac_low_data.dev_addr);
res = platform_device_register(&cpmac_low);
if (res)
pr_warn("unable to register cpmac-low: %d\n", res);
} else
pr_warn("unable to add cpmac-low phy: %d\n", res);
detect_leds();
res = platform_device_register(&ar7_gpio_leds);
if (res)
pr_warn("unable to register leds: %d\n", res);
res = platform_device_register(&ar7_udc);
if (res)
pr_warn("unable to register usb slave: %d\n", res);
/* Register watchdog only if enabled in hardware */
bootcr = ioremap(AR7_REGS_DCL, 4);
val = readl(bootcr);
iounmap(bootcr);
if (val & AR7_WDT_HW_ENA) {
if (ar7_has_high_vlynq())
ar7_wdt_res.start = UR8_REGS_WDT;
else
ar7_wdt_res.start = AR7_REGS_WDT;
ar7_wdt_res.end = ar7_wdt_res.start + 0x20;
res = platform_device_register(&ar7_wdt);
if (res)
pr_warn("unable to register watchdog: %d\n", res);
}
return 0;
}
device_initcall(ar7_register_devices);

256
arch/mips/ar7/prom.c
View File

@ -1,256 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
*
* Putting things on the screen/serial line using YAMONs facilities.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/serial_reg.h>
#include <linux/spinlock.h>
#include <linux/export.h>
#include <linux/string.h>
#include <linux/io.h>
#include <asm/bootinfo.h>
#include <asm/setup.h>
#include <asm/mach-ar7/ar7.h>
#include <asm/mach-ar7/prom.h>
#define MAX_ENTRY 80
struct env_var {
char *name;
char *value;
};
static struct env_var adam2_env[MAX_ENTRY];
char *prom_getenv(const char *name)
{
int i;
for (i = 0; (i < MAX_ENTRY) && adam2_env[i].name; i++)
if (!strcmp(name, adam2_env[i].name))
return adam2_env[i].value;
return NULL;
}
EXPORT_SYMBOL(prom_getenv);
static void __init ar7_init_cmdline(int argc, char *argv[])
{
int i;
for (i = 1; i < argc; i++) {
strlcat(arcs_cmdline, argv[i], COMMAND_LINE_SIZE);
if (i < (argc - 1))
strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE);
}
}
struct psbl_rec {
u32 psbl_size;
u32 env_base;
u32 env_size;
u32 ffs_base;
u32 ffs_size;
};
static const char psp_env_version[] __initconst = "TIENV0.8";
struct psp_env_chunk {
u8 num;
u8 ctrl;
u16 csum;
u8 len;
char data[11];
} __packed;
struct psp_var_map_entry {
u8 num;
char *value;
};
static const struct psp_var_map_entry psp_var_map[] = {
{ 1, "cpufrequency" },
{ 2, "memsize" },
{ 3, "flashsize" },
{ 4, "modetty0" },
{ 5, "modetty1" },
{ 8, "maca" },
{ 9, "macb" },
{ 28, "sysfrequency" },
{ 38, "mipsfrequency" },
};
/*
Well-known variable (num is looked up in table above for matching variable name)
Example: cpufrequency=211968000
+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+---
| 01 |CTRL|CHECKSUM | 01 | _2 | _1 | _1 | _9 | _6 | _8 | _0 | _0 | _0 | \0 | FF
+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+---
Name=Value pair in a single chunk
Example: NAME=VALUE
+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+---
| 00 |CTRL|CHECKSUM | 01 | _N | _A | _M | _E | _0 | _V | _A | _L | _U | _E | \0
+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+---
Name=Value pair in 2 chunks (len is the number of chunks)
Example: bootloaderVersion=1.3.7.15
+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+---
| 00 |CTRL|CHECKSUM | 02 | _b | _o | _o | _t | _l | _o | _a | _d | _e | _r | _V
+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+---
| _e | _r | _s | _i | _o | _n | \0 | _1 | _. | _3 | _. | _7 | _. | _1 | _5 | \0
+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+---
Data is padded with 0xFF
*/
#define PSP_ENV_SIZE 4096
static char psp_env_data[PSP_ENV_SIZE] = { 0, };
static char * __init lookup_psp_var_map(u8 num)
{
int i;
for (i = 0; i < ARRAY_SIZE(psp_var_map); i++)
if (psp_var_map[i].num == num)
return psp_var_map[i].value;
return NULL;
}
static void __init add_adam2_var(char *name, char *value)
{
int i;
for (i = 0; i < MAX_ENTRY; i++) {
if (!adam2_env[i].name) {
adam2_env[i].name = name;
adam2_env[i].value = value;
return;
} else if (!strcmp(adam2_env[i].name, name)) {
adam2_env[i].value = value;
return;
}
}
}
static int __init parse_psp_env(void *psp_env_base)
{
int i, n;
char *name, *value;
struct psp_env_chunk *chunks = (struct psp_env_chunk *)psp_env_data;
memcpy_fromio(chunks, psp_env_base, PSP_ENV_SIZE);
i = 1;
n = PSP_ENV_SIZE / sizeof(struct psp_env_chunk);
while (i < n) {
if ((chunks[i].num == 0xff) || ((i + chunks[i].len) > n))
break;
value = chunks[i].data;
if (chunks[i].num) {
name = lookup_psp_var_map(chunks[i].num);
} else {
name = value;
value += strlen(name) + 1;
}
if (name)
add_adam2_var(name, value);
i += chunks[i].len;
}
return 0;
}
static void __init ar7_init_env(struct env_var *env)
{
int i;
struct psbl_rec *psbl = (struct psbl_rec *)(KSEG1ADDR(0x14000300));
void *psp_env = (void *)KSEG1ADDR(psbl->env_base);
if (strcmp(psp_env, psp_env_version) == 0) {
parse_psp_env(psp_env);
} else {
for (i = 0; i < MAX_ENTRY; i++, env++)
if (env->name)
add_adam2_var(env->name, env->value);
}
}
static void __init console_config(void)
{
#ifdef CONFIG_SERIAL_8250_CONSOLE
char console_string[40];
int baud = 0;
char parity = '\0', bits = '\0', flow = '\0';
char *s, *p;
if (strstr(arcs_cmdline, "console="))
return;
s = prom_getenv("modetty0");
if (s) {
baud = simple_strtoul(s, &p, 10);
s = p;
if (*s == ',')
s++;
if (*s)
parity = *s++;
if (*s == ',')
s++;
if (*s)
bits = *s++;
if (*s == ',')
s++;
if (*s == 'h')
flow = 'r';
}
if (baud == 0)
baud = 38400;
if (parity != 'n' && parity != 'o' && parity != 'e')
parity = 'n';
if (bits != '7' && bits != '8')
bits = '8';
if (flow == 'r')
sprintf(console_string, " console=ttyS0,%d%c%c%c", baud,
parity, bits, flow);
else
sprintf(console_string, " console=ttyS0,%d%c%c", baud, parity,
bits);
strlcat(arcs_cmdline, console_string, COMMAND_LINE_SIZE);
#endif
}
void __init prom_init(void)
{
ar7_init_cmdline(fw_arg0, (char **)fw_arg1);
ar7_init_env((struct env_var *)fw_arg2);
console_config();
}
#define PORT(offset) (KSEG1ADDR(AR7_REGS_UART0 + (offset * 4)))
static inline unsigned int serial_in(int offset)
{
return readl((void *)PORT(offset));
}
static inline void serial_out(int offset, int value)
{
writel(value, (void *)PORT(offset));
}
void prom_putchar(char c)
{
while ((serial_in(UART_LSR) & UART_LSR_TEMT) == 0)
;
serial_out(UART_TX, c);
}

93
arch/mips/ar7/setup.c
View File

@ -1,93 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*/
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/pm.h>
#include <linux/time.h>
#include <asm/reboot.h>
#include <asm/mach-ar7/ar7.h>
#include <asm/mach-ar7/prom.h>
static void ar7_machine_restart(char *command)
{
u32 *softres_reg = ioremap(AR7_REGS_RESET + AR7_RESET_SOFTWARE, 1);
writel(1, softres_reg);
}
static void ar7_machine_halt(void)
{
while (1)
;
}
static void ar7_machine_power_off(void)
{
u32 *power_reg = (u32 *)ioremap(AR7_REGS_POWER, 1);
u32 power_state = readl(power_reg) | (3 << 30);
writel(power_state, power_reg);
ar7_machine_halt();
}
const char *get_system_type(void)
{
u16 chip_id = ar7_chip_id();
u16 titan_variant_id = titan_chip_id();
switch (chip_id) {
case AR7_CHIP_7100:
return "TI AR7 (TNETD7100)";
case AR7_CHIP_7200:
return "TI AR7 (TNETD7200)";
case AR7_CHIP_7300:
return "TI AR7 (TNETD7300)";
case AR7_CHIP_TITAN:
switch (titan_variant_id) {
case TITAN_CHIP_1050:
return "TI AR7 (TNETV1050)";
case TITAN_CHIP_1055:
return "TI AR7 (TNETV1055)";
case TITAN_CHIP_1056:
return "TI AR7 (TNETV1056)";
case TITAN_CHIP_1060:
return "TI AR7 (TNETV1060)";
}
fallthrough;
default:
return "TI AR7 (unknown)";
}
}
static int __init ar7_init_console(void)
{
return 0;
}
console_initcall(ar7_init_console);
/*
* Initializes basic routines and structures pointers, memory size (as
* given by the bios and saves the command line.
*/
void __init plat_mem_setup(void)
{
unsigned long io_base;
_machine_restart = ar7_machine_restart;
_machine_halt = ar7_machine_halt;
pm_power_off = ar7_machine_power_off;
io_base = (unsigned long)ioremap(AR7_REGS_BASE, 0x10000);
if (!io_base)
panic("Can't remap IO base!");
set_io_port_base(io_base);
prom_meminit();
printk(KERN_INFO "%s, ID: 0x%04x, Revision: 0x%02x\n",
get_system_type(), ar7_chip_id(), ar7_chip_rev());
}

31
arch/mips/ar7/time.c
View File

@ -1,31 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
*
* Setting up the clock on the MIPS boards.
*/
#include <linux/init.h>
#include <linux/time.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <asm/time.h>
#include <asm/mach-ar7/ar7.h>
void __init plat_time_init(void)
{
struct clk *cpu_clk;
/* Initialize ar7 clocks so the CPU clock frequency is correct */
ar7_init_clocks();
cpu_clk = clk_get(NULL, "cpu");
if (IS_ERR(cpu_clk)) {
printk(KERN_ERR "unable to get cpu clock\n");
return;
}
mips_hpt_frequency = clk_get_rate(cpu_clk) / 2;
}

5
arch/mips/boot/compressed/uart-16550.c
View File

@ -13,11 +13,6 @@
#define PORT(offset) (CKSEG1ADDR(UART_BASE) + (offset))
#endif
#ifdef CONFIG_AR7
#include <ar7.h>
#define PORT(offset) (CKSEG1ADDR(AR7_REGS_UART0) + (4 * offset))
#endif
#ifdef CONFIG_MACH_INGENIC
#define INGENIC_UART_BASE_ADDR (0x10030000 + 0x1000 * CONFIG_ZBOOT_INGENIC_UART)
#define PORT(offset) (CKSEG1ADDR(INGENIC_UART_BASE_ADDR) + (4 * offset))

1
arch/mips/boot/dts/ingenic/jz4725b.dtsi
View File

@ -366,7 +366,6 @@ bch: ecc-controller@130d0000 {
rom: memory@1fc00000 {
compatible = "mtd-rom";
probe-type = "map_rom";
reg = <0x1fc00000 0x2000>;
bank-width = <4>;

1
arch/mips/boot/dts/ingenic/jz4770.dtsi
View File

@ -461,7 +461,6 @@ usb_otg: usb@13440000 {
rom: memory@1fc00000 {
compatible = "mtd-rom";
probe-type = "map_rom";
reg = <0x1fc00000 0x2000>;
bank-width = <4>;

2
arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc1.dts
View File

@ -8,7 +8,7 @@
/ {
compatible = "gnubee,gb-pc1", "mediatek,mt7621-soc";
model = "GB-PC1";
model = "GnuBee GB-PC1";
memory@0 {
device_type = "memory";

2
arch/mips/boot/dts/ralink/mt7621-gnubee-gb-pc2.dts
View File

@ -8,7 +8,7 @@
/ {
compatible = "gnubee,gb-pc2", "mediatek,mt7621-soc";
model = "GB-PC2";
model = "GnuBee GB-PC2";
memory@0 {
device_type = "memory";

5
arch/mips/boot/dts/ralink/mt7621.dtsi
View File

@ -300,14 +300,13 @@ ethernet: ethernet@1e100000 {
compatible = "mediatek,mt7621-eth";
reg = <0x1e100000 0x10000>;
clocks = <&sysc MT7621_CLK_FE>,
<&sysc MT7621_CLK_ETH>;
clocks = <&sysc MT7621_CLK_FE>, <&sysc MT7621_CLK_ETH>;
clock-names = "fe", "ethif";
#address-cells = <1>;
#size-cells = <0>;
resets = <&sysc MT7621_RST_FE &sysc MT7621_RST_ETH>;
resets = <&sysc MT7621_RST_FE>, <&sysc MT7621_RST_ETH>;
reset-names = "fe", "eth";
interrupt-parent = <&gic>;

119
arch/mips/configs/ar7_defconfig
View File

@ -1,119 +0,0 @@
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_KERNEL_LZMA=y
CONFIG_SYSVIPC=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
# CONFIG_ELF_CORE is not set
# CONFIG_KALLSYMS is not set
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_AR7=y
CONFIG_HZ_100=y
CONFIG_KEXEC=y
# CONFIG_SECCOMP is not set
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_PARTITION_ADVANCED=y
CONFIG_BSD_DISKLABEL=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_MROUTE=y
CONFIG_SYN_COOKIES=y
# CONFIG_INET_DIAG is not set
CONFIG_TCP_CONG_ADVANCED=y
# CONFIG_TCP_CONG_BIC is not set
# CONFIG_TCP_CONG_CUBIC is not set
CONFIG_TCP_CONG_WESTWOOD=y
# CONFIG_TCP_CONG_HTCP is not set
# CONFIG_IPV6 is not set
CONFIG_NETFILTER=y
# CONFIG_BRIDGE_NETFILTER is not set
CONFIG_NF_CONNTRACK=m
CONFIG_NF_CONNTRACK_MARK=y
CONFIG_NF_CONNTRACK_FTP=m
CONFIG_NF_CONNTRACK_IRC=m
CONFIG_NF_CONNTRACK_TFTP=m
CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
CONFIG_NETFILTER_XT_MATCH_LIMIT=m
CONFIG_NETFILTER_XT_MATCH_MAC=m
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
CONFIG_NETFILTER_XT_MATCH_STATE=m
CONFIG_IP_NF_IPTABLES=m
CONFIG_IP_NF_FILTER=m
CONFIG_IP_NF_TARGET_REJECT=m
CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_RAW=m
CONFIG_ATM=m
CONFIG_ATM_BR2684=m
CONFIG_ATM_BR2684_IPFILTER=y
CONFIG_BRIDGE=y
CONFIG_VLAN_8021Q=y
CONFIG_NET_SCHED=y
CONFIG_NET_CLS_ACT=y
CONFIG_NET_ACT_POLICE=y
CONFIG_HAMRADIO=y
CONFIG_CFG80211=m
CONFIG_MAC80211=m
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_PHYSMAP=y
CONFIG_NETDEVICES=y
CONFIG_CPMAC=y
CONFIG_FIXED_PHY=y
CONFIG_PPP=m
CONFIG_PPP_FILTER=y
CONFIG_PPP_MULTILINK=y
CONFIG_PPPOATM=m
CONFIG_PPPOE=m
CONFIG_PPP_ASYNC=m
# CONFIG_INPUT is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=2
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
CONFIG_HW_RANDOM=y
CONFIG_GPIO_SYSFS=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_AR7_WDT=y
# CONFIG_USB_SUPPORT is not set
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
# CONFIG_DNOTIFY is not set
CONFIG_PROC_KCORE=y
# CONFIG_PROC_PAGE_MONITOR is not set
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_SUMMARY=y
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
CONFIG_SQUASHFS=y
# CONFIG_CRYPTO_HW is not set
CONFIG_STRIP_ASM_SYMS=y
CONFIG_DEBUG_FS=y
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="rootfstype=squashfs,jffs2"

1
arch/mips/configs/fuloong2e_defconfig
View File

@ -177,7 +177,6 @@ CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
CONFIG_REISERFS_FS=m
CONFIG_AUTOFS_FS=y
CONFIG_FUSE_FS=y
CONFIG_ISO9660_FS=m

4
arch/mips/configs/jazz_defconfig
View File

@ -70,10 +70,6 @@ CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_HWMON is not set
CONFIG_EXT2_FS=m
CONFIG_EXT3_FS=y
CONFIG_REISERFS_FS=m
CONFIG_REISERFS_FS_XATTR=y
CONFIG_REISERFS_FS_POSIX_ACL=y
CONFIG_REISERFS_FS_SECURITY=y
CONFIG_XFS_FS=m
CONFIG_XFS_QUOTA=y
CONFIG_AUTOFS_FS=m

3
arch/mips/configs/lemote2f_defconfig
View File

@ -229,9 +229,6 @@ CONFIG_EXT2_FS=m
CONFIG_EXT3_FS=y
CONFIG_EXT3_FS_POSIX_ACL=y
CONFIG_EXT3_FS_SECURITY=y
CONFIG_REISERFS_FS=m
CONFIG_REISERFS_PROC_INFO=y
CONFIG_REISERFS_FS_XATTR=y
CONFIG_JFS_FS=m
CONFIG_JFS_POSIX_ACL=y
CONFIG_XFS_FS=m

5
arch/mips/configs/malta_defconfig
View File

@ -317,11 +317,6 @@ CONFIG_UIO=m
CONFIG_UIO_CIF=m
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
CONFIG_REISERFS_FS=m
CONFIG_REISERFS_PROC_INFO=y
CONFIG_REISERFS_FS_XATTR=y
CONFIG_REISERFS_FS_POSIX_ACL=y
CONFIG_REISERFS_FS_SECURITY=y
CONFIG_JFS_FS=m
CONFIG_JFS_POSIX_ACL=y
CONFIG_JFS_SECURITY=y

5
arch/mips/configs/malta_kvm_defconfig
View File

@ -323,11 +323,6 @@ CONFIG_UIO=m
CONFIG_UIO_CIF=m
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
CONFIG_REISERFS_FS=m
CONFIG_REISERFS_PROC_INFO=y
CONFIG_REISERFS_FS_XATTR=y
CONFIG_REISERFS_FS_POSIX_ACL=y
CONFIG_REISERFS_FS_SECURITY=y
CONFIG_JFS_FS=m
CONFIG_JFS_POSIX_ACL=y
CONFIG_JFS_SECURITY=y

5
arch/mips/configs/maltaup_xpa_defconfig
View File

@ -323,11 +323,6 @@ CONFIG_UIO=m
CONFIG_UIO_CIF=m
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
CONFIG_REISERFS_FS=m
CONFIG_REISERFS_PROC_INFO=y
CONFIG_REISERFS_FS_XATTR=y
CONFIG_REISERFS_FS_POSIX_ACL=y
CONFIG_REISERFS_FS_SECURITY=y
CONFIG_JFS_FS=m
CONFIG_JFS_POSIX_ACL=y
CONFIG_JFS_SECURITY=y

4
arch/mips/configs/rm200_defconfig
View File

@ -310,10 +310,6 @@ CONFIG_USB_LD=m
CONFIG_USB_TEST=m
CONFIG_EXT2_FS=m
CONFIG_EXT3_FS=y
CONFIG_REISERFS_FS=m
CONFIG_REISERFS_FS_XATTR=y
CONFIG_REISERFS_FS_POSIX_ACL=y
CONFIG_REISERFS_FS_SECURITY=y
CONFIG_XFS_FS=m
CONFIG_XFS_QUOTA=y
CONFIG_AUTOFS_FS=m

191
arch/mips/include/asm/mach-ar7/ar7.h
View File

@ -1,191 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org>
* Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org>
*/
#ifndef __AR7_H__
#define __AR7_H__
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/errno.h>
#include <asm/addrspace.h>
#define AR7_SDRAM_BASE 0x14000000
#define AR7_REGS_BASE 0x08610000
#define AR7_REGS_MAC0 (AR7_REGS_BASE + 0x0000)
#define AR7_REGS_GPIO (AR7_REGS_BASE + 0x0900)
/* 0x08610A00 - 0x08610BFF (512 bytes, 128 bytes / clock) */
#define AR7_REGS_POWER (AR7_REGS_BASE + 0x0a00)
#define AR7_REGS_CLOCKS (AR7_REGS_POWER + 0x80)
#define UR8_REGS_CLOCKS (AR7_REGS_POWER + 0x20)
#define AR7_REGS_UART0 (AR7_REGS_BASE + 0x0e00)
#define AR7_REGS_USB (AR7_REGS_BASE + 0x1200)
#define AR7_REGS_RESET (AR7_REGS_BASE + 0x1600)
#define AR7_REGS_PINSEL (AR7_REGS_BASE + 0x160C)
#define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800)
#define AR7_REGS_DCL (AR7_REGS_BASE + 0x1a00)
#define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1c00)
#define AR7_REGS_MDIO (AR7_REGS_BASE + 0x1e00)
#define AR7_REGS_IRQ (AR7_REGS_BASE + 0x2400)
#define AR7_REGS_MAC1 (AR7_REGS_BASE + 0x2800)
#define AR7_REGS_WDT (AR7_REGS_BASE + 0x1f00)
#define UR8_REGS_WDT (AR7_REGS_BASE + 0x0b00)
#define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00)
/* Titan registers */
#define TITAN_REGS_ESWITCH_BASE (0x08640000)
#define TITAN_REGS_MAC0 (TITAN_REGS_ESWITCH_BASE)
#define TITAN_REGS_MAC1 (TITAN_REGS_ESWITCH_BASE + 0x0800)
#define TITAN_REGS_MDIO (TITAN_REGS_ESWITCH_BASE + 0x02000)
#define TITAN_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1c00)
#define TITAN_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1300)
#define AR7_RESET_PERIPHERAL 0x0
#define AR7_RESET_SOFTWARE 0x4
#define AR7_RESET_STATUS 0x8
#define AR7_RESET_BIT_CPMAC_LO 17
#define AR7_RESET_BIT_CPMAC_HI 21
#define AR7_RESET_BIT_MDIO 22
#define AR7_RESET_BIT_EPHY 26
#define TITAN_RESET_BIT_EPHY1 28
/* GPIO control registers */
#define AR7_GPIO_INPUT 0x0
#define AR7_GPIO_OUTPUT 0x4
#define AR7_GPIO_DIR 0x8
#define AR7_GPIO_ENABLE 0xc
#define TITAN_GPIO_INPUT_0 0x0
#define TITAN_GPIO_INPUT_1 0x4
#define TITAN_GPIO_OUTPUT_0 0x8
#define TITAN_GPIO_OUTPUT_1 0xc
#define TITAN_GPIO_DIR_0 0x10
#define TITAN_GPIO_DIR_1 0x14
#define TITAN_GPIO_ENBL_0 0x18
#define TITAN_GPIO_ENBL_1 0x1c
#define AR7_CHIP_7100 0x18
#define AR7_CHIP_7200 0x2b
#define AR7_CHIP_7300 0x05
#define AR7_CHIP_TITAN 0x07
#define TITAN_CHIP_1050 0x0f
#define TITAN_CHIP_1055 0x0e
#define TITAN_CHIP_1056 0x0d
#define TITAN_CHIP_1060 0x07
/* Interrupts */
#define AR7_IRQ_UART0 15
#define AR7_IRQ_UART1 16
/* Clocks */
#define AR7_AFE_CLOCK 35328000
#define AR7_REF_CLOCK 25000000
#define AR7_XTAL_CLOCK 24000000
/* DCL */
#define AR7_WDT_HW_ENA 0x10
struct plat_cpmac_data {
int reset_bit;
int power_bit;
u32 phy_mask;
char dev_addr[6];
};
struct plat_dsl_data {
int reset_bit_dsl;
int reset_bit_sar;
};
static inline int ar7_is_titan(void)
{
return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x24)) & 0xffff) ==
AR7_CHIP_TITAN;
}
static inline u16 ar7_chip_id(void)
{
return ar7_is_titan() ? AR7_CHIP_TITAN : (readl((void *)
KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff);
}
static inline u16 titan_chip_id(void)
{
unsigned int val = readl((void *)KSEG1ADDR(AR7_REGS_GPIO +
TITAN_GPIO_INPUT_1));
return ((val >> 12) & 0x0f);
}
static inline u8 ar7_chip_rev(void)
{
return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + (ar7_is_titan() ? 0x24 :
0x14))) >> 16) & 0xff;
}
static inline int ar7_has_high_cpmac(void)
{
u16 chip_id = ar7_chip_id();
switch (chip_id) {
case AR7_CHIP_7100:
case AR7_CHIP_7200:
return 0;
case AR7_CHIP_7300:
return 1;
default:
return -ENXIO;
}
}
#define ar7_has_high_vlynq ar7_has_high_cpmac
#define ar7_has_second_uart ar7_has_high_cpmac
static inline void ar7_device_enable(u32 bit)
{
void *reset_reg =
(void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PERIPHERAL);
writel(readl(reset_reg) | (1 << bit), reset_reg);
msleep(20);
}
static inline void ar7_device_disable(u32 bit)
{
void *reset_reg =
(void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PERIPHERAL);
writel(readl(reset_reg) & ~(1 << bit), reset_reg);
msleep(20);
}
static inline void ar7_device_reset(u32 bit)
{
ar7_device_disable(bit);
ar7_device_enable(bit);
}
static inline void ar7_device_on(u32 bit)
{
void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
writel(readl(power_reg) | (1 << bit), power_reg);
msleep(20);
}
static inline void ar7_device_off(u32 bit)
{
void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
writel(readl(power_reg) & ~(1 << bit), power_reg);
msleep(20);
}
int __init ar7_gpio_init(void);
void __init ar7_init_clocks(void);
/* Board specific GPIO functions */
int ar7_gpio_enable(unsigned gpio);
int ar7_gpio_disable(unsigned gpio);
#endif /* __AR7_H__ */

16
arch/mips/include/asm/mach-ar7/irq.h
View File

@ -1,16 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Shamelessly copied from asm-mips/mach-emma2rh/
* Copyright (C) 2003 by Ralf Baechle
*/
#ifndef __ASM_AR7_IRQ_H
#define __ASM_AR7_IRQ_H
#define NR_IRQS 256
#include <asm/mach-generic/irq.h>
#endif /* __ASM_AR7_IRQ_H */

12
arch/mips/include/asm/mach-ar7/prom.h
View File

@ -1,12 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2006, 2007 Florian Fainelli <florian@openwrt.org>
*/
#ifndef __PROM_H__
#define __PROM_H__
extern char *prom_getenv(const char *name);
extern void prom_meminit(void);
#endif /* __PROM_H__ */

22
arch/mips/include/asm/mach-ar7/spaces.h
View File

@ -1,22 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle
* Copyright (C) 2000, 2002 Maciej W. Rozycki
* Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
*/
#ifndef _ASM_AR7_SPACES_H
#define _ASM_AR7_SPACES_H
/*
* This handles the memory map.
* We handle pages at KSEG0 for kernels with 32 bit address space.
*/
#define PAGE_OFFSET _AC(0x94000000, UL)
#define PHYS_OFFSET _AC(0x14000000, UL)
#include <asm/mach-generic/spaces.h>
#endif /* __ASM_AR7_SPACES_H */

21
arch/mips/include/asm/mach-loongson32/dma.h
View File

@ -1,21 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2015 Zhang, Keguang <keguang.zhang@gmail.com>
*
* Loongson 1 NAND platform support.
*/
#ifndef __ASM_MACH_LOONGSON32_DMA_H
#define __ASM_MACH_LOONGSON32_DMA_H
#define LS1X_DMA_CHANNEL0 0
#define LS1X_DMA_CHANNEL1 1
#define LS1X_DMA_CHANNEL2 2
struct plat_ls1x_dma {
int nr_channels;
};
extern struct plat_ls1x_dma ls1b_dma_pdata;
#endif /* __ASM_MACH_LOONGSON32_DMA_H */

26
arch/mips/include/asm/mach-loongson32/nand.h
View File

@ -1,26 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2015 Zhang, Keguang <keguang.zhang@gmail.com>
*
* Loongson 1 NAND platform support.
*/
#ifndef __ASM_MACH_LOONGSON32_NAND_H
#define __ASM_MACH_LOONGSON32_NAND_H
#include <linux/dmaengine.h>
#include <linux/mtd/partitions.h>
struct plat_ls1x_nand {
struct mtd_partition *parts;
unsigned int nr_parts;
int hold_cycle;
int wait_cycle;
};
extern struct plat_ls1x_nand ls1b_nand_pdata;
bool ls1x_dma_filter_fn(struct dma_chan *chan, void *param);
#endif /* __ASM_MACH_LOONGSON32_NAND_H */

3
arch/mips/include/asm/mach-loongson32/platform.h
View File

@ -8,9 +8,6 @@
#include <linux/platform_device.h>
#include <dma.h>
#include <nand.h>
extern struct platform_device ls1x_uart_pdev;
extern struct platform_device ls1x_eth0_pdev;
extern struct platform_device ls1x_eth1_pdev;

1
arch/mips/kernel/relocate_kernel.S
View File

@ -66,7 +66,6 @@ copy_word:
LONG_ADDIU s6, s6, -1
beq s6, zero, process_entry
b copy_word
b process_entry
done:
#ifdef CONFIG_SMP

2
arch/mips/loongson32/common/platform.c
View File

@ -15,8 +15,6 @@
#include <platform.h>
#include <loongson1.h>
#include <dma.h>
#include <nand.h>
/* 8250/16550 compatible UART */
#define LS1X_UART(_id) \

2
arch/mips/loongson32/ls1b/board.c
View File

@ -8,8 +8,6 @@
#include <linux/sizes.h>
#include <loongson1.h>
#include <dma.h>
#include <nand.h>
#include <platform.h>
static const struct gpio_led ls1x_gpio_leds[] __initconst = {

2
arch/mips/pci/fixup-lantiq.c
View File

@ -4,8 +4,8 @@
* Copyright (C) 2012 John Crispin <john@phrozen.org>
*/
#include <linux/of_irq.h>
#include <linux/of_pci.h>
#include <linux/pci.h>
int (*ltq_pci_plat_arch_init)(struct pci_dev *dev) = NULL;
int (*ltq_pci_plat_dev_init)(struct pci_dev *dev) = NULL;

2
drivers/Kconfig
View File

@ -135,8 +135,6 @@ source "drivers/uio/Kconfig"
source "drivers/vfio/Kconfig"
source "drivers/vlynq/Kconfig"
source "drivers/virt/Kconfig"
source "drivers/virtio/Kconfig"

1
drivers/Makefile
View File

@ -151,7 +151,6 @@ obj-$(CONFIG_BCMA) += bcma/
obj-$(CONFIG_VHOST_RING) += vhost/
obj-$(CONFIG_VHOST_IOTLB) += vhost/
obj-$(CONFIG_VHOST) += vhost/
obj-$(CONFIG_VLYNQ) += vlynq/
obj-$(CONFIG_GREYBUS) += greybus/
obj-$(CONFIG_COMEDI) += comedi/
obj-$(CONFIG_STAGING) += staging/

5
drivers/mtd/parsers/Kconfig
View File

@ -1,9 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
config MTD_AR7_PARTS
tristate "TI AR7 partitioning parser"
help
TI AR7 partitioning parser support
config MTD_BCM47XX_PARTS
tristate "BCM47XX partitioning parser"
depends on BCM47XX || ARCH_BCM_5301X

1
drivers/mtd/parsers/Makefile
View File

@ -1,5 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o
obj-$(CONFIG_MTD_BCM47XX_PARTS) += bcm47xxpart.o
obj-$(CONFIG_MTD_BCM63XX_PARTS) += bcm63xxpart.o
obj-$(CONFIG_MTD_BRCM_U_BOOT) += brcm_u-boot.o

129
drivers/mtd/parsers/ar7part.c
View File

@ -1,129 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright © 2007 Eugene Konev <ejka@openwrt.org>
*
* TI AR7 flash partition table.
* Based on ar7 map by Felix Fietkau <nbd@openwrt.org>
*/
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/memblock.h>
#include <linux/module.h>
#include <uapi/linux/magic.h>
#define AR7_PARTS 4
#define ROOT_OFFSET 0xe0000
#define LOADER_MAGIC1 le32_to_cpu(0xfeedfa42)
#define LOADER_MAGIC2 le32_to_cpu(0xfeed1281)
struct ar7_bin_rec {
unsigned int checksum;
unsigned int length;
unsigned int address;
};
static int create_mtd_partitions(struct mtd_info *master,
const struct mtd_partition **pparts,
struct mtd_part_parser_data *data)
{
struct ar7_bin_rec header;
unsigned int offset;
size_t len;
unsigned int pre_size = master->erasesize, post_size = 0;
unsigned int root_offset = ROOT_OFFSET;
int retries = 10;
struct mtd_partition *ar7_parts;
ar7_parts = kcalloc(AR7_PARTS, sizeof(*ar7_parts), GFP_KERNEL);
if (!ar7_parts)
return -ENOMEM;
ar7_parts[0].name = "loader";
ar7_parts[0].offset = 0;
ar7_parts[0].size = master->erasesize;
ar7_parts[0].mask_flags = MTD_WRITEABLE;
ar7_parts[1].name = "config";
ar7_parts[1].offset = 0;
ar7_parts[1].size = master->erasesize;
ar7_parts[1].mask_flags = 0;
do { /* Try 10 blocks starting from master->erasesize */
offset = pre_size;
mtd_read(master, offset, sizeof(header), &len,
(uint8_t *)&header);
if (!strncmp((char *)&header, "TIENV0.8", 8))
ar7_parts[1].offset = pre_size;
if (header.checksum == LOADER_MAGIC1)
break;
if (header.checksum == LOADER_MAGIC2)
break;
pre_size += master->erasesize;
} while (retries--);
pre_size = offset;
if (!ar7_parts[1].offset) {
ar7_parts[1].offset = master->size - master->erasesize;
post_size = master->erasesize;
}
switch (header.checksum) {
case LOADER_MAGIC1:
while (header.length) {
offset += sizeof(header) + header.length;
mtd_read(master, offset, sizeof(header), &len,
(uint8_t *)&header);
}
root_offset = offset + sizeof(header) + 4;
break;
case LOADER_MAGIC2:
while (header.length) {
offset += sizeof(header) + header.length;
mtd_read(master, offset, sizeof(header), &len,
(uint8_t *)&header);
}
root_offset = offset + sizeof(header) + 4 + 0xff;
root_offset &= ~(uint32_t)0xff;
break;
default:
printk(KERN_WARNING "Unknown magic: %08x\n", header.checksum);
break;
}
mtd_read(master, root_offset, sizeof(header), &len, (u8 *)&header);
if (header.checksum != SQUASHFS_MAGIC) {
root_offset += master->erasesize - 1;
root_offset &= ~(master->erasesize - 1);
}
ar7_parts[2].name = "linux";
ar7_parts[2].offset = pre_size;
ar7_parts[2].size = master->size - pre_size - post_size;
ar7_parts[2].mask_flags = 0;
ar7_parts[3].name = "rootfs";
ar7_parts[3].offset = root_offset;
ar7_parts[3].size = master->size - root_offset - post_size;
ar7_parts[3].mask_flags = 0;
*pparts = ar7_parts;
return AR7_PARTS;
}
static struct mtd_part_parser ar7_parser = {
.parse_fn = create_mtd_partitions,
.name = "ar7part",
};
module_mtd_part_parser(ar7_parser);
MODULE_LICENSE("GPL");
MODULE_AUTHOR( "Felix Fietkau <nbd@openwrt.org>, "
"Eugene Konev <ejka@openwrt.org>");
MODULE_DESCRIPTION("MTD partitioning for TI AR7");

7
drivers/tty/serial/8250/8250_port.c
View File

@ -170,13 +170,6 @@ static const struct serial8250_config uart_config[] = {
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
.flags = UART_CAP_FIFO,
},
[PORT_AR7] = {
.name = "AR7",
.fifo_size = 16,
.tx_loadsz = 16,
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
.flags = UART_CAP_FIFO /* | UART_CAP_AFE */,
},
[PORT_U6_16550A] = {
.name = "U6_16550A",
.fifo_size = 64,

21
drivers/vlynq/Kconfig
View File

@ -1,21 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
menu "TI VLYNQ"
depends on AR7
config VLYNQ
bool "TI VLYNQ bus support"
help
Support for Texas Instruments(R) VLYNQ bus.
The VLYNQ bus is a high-speed, serial and packetized
data bus which allows external peripherals of a SoC
to appear into the system's main memory.
If unsure, say N
config VLYNQ_DEBUG
bool "VLYNQ bus debug"
depends on VLYNQ && DEBUG_KERNEL
help
Turn on VLYNQ bus debugging.
endmenu

6
drivers/vlynq/Makefile
View File

@ -1,6 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
#
# Makefile for kernel vlynq drivers
#
obj-$(CONFIG_VLYNQ) += vlynq.o

799
drivers/vlynq/vlynq.c
View File

@ -1,799 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2006, 2007 Eugene Konev <ejka@openwrt.org>
*
* Parts of the VLYNQ specification can be found here:
* http://www.ti.com/litv/pdf/sprue36a
*/
#include <linux/init.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/device.h>
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/irq.h>
#include <linux/vlynq.h>
#define VLYNQ_CTRL_PM_ENABLE 0x80000000
#define VLYNQ_CTRL_CLOCK_INT 0x00008000
#define VLYNQ_CTRL_CLOCK_DIV(x) (((x) & 7) << 16)
#define VLYNQ_CTRL_INT_LOCAL 0x00004000
#define VLYNQ_CTRL_INT_ENABLE 0x00002000
#define VLYNQ_CTRL_INT_VECTOR(x) (((x) & 0x1f) << 8)
#define VLYNQ_CTRL_INT2CFG 0x00000080
#define VLYNQ_CTRL_RESET 0x00000001
#define VLYNQ_CTRL_CLOCK_MASK (0x7 << 16)
#define VLYNQ_INT_OFFSET 0x00000014
#define VLYNQ_REMOTE_OFFSET 0x00000080
#define VLYNQ_STATUS_LINK 0x00000001
#define VLYNQ_STATUS_LERROR 0x00000080
#define VLYNQ_STATUS_RERROR 0x00000100
#define VINT_ENABLE 0x00000100
#define VINT_TYPE_EDGE 0x00000080
#define VINT_LEVEL_LOW 0x00000040
#define VINT_VECTOR(x) ((x) & 0x1f)
#define VINT_OFFSET(irq) (8 * ((irq) % 4))
#define VLYNQ_AUTONEGO_V2 0x00010000
struct vlynq_regs {
u32 revision;
u32 control;
u32 status;
u32 int_prio;
u32 int_status;
u32 int_pending;
u32 int_ptr;
u32 tx_offset;
struct vlynq_mapping rx_mapping[4];
u32 chip;
u32 autonego;
u32 unused[6];
u32 int_device[8];
};
#ifdef CONFIG_VLYNQ_DEBUG
static void vlynq_dump_regs(struct vlynq_device *dev)
{
int i;
printk(KERN_DEBUG "VLYNQ local=%p remote=%p\n",
dev->local, dev->remote);
for (i = 0; i < 32; i++) {
printk(KERN_DEBUG "VLYNQ: local %d: %08x\n",
i + 1, ((u32 *)dev->local)[i]);
printk(KERN_DEBUG "VLYNQ: remote %d: %08x\n",
i + 1, ((u32 *)dev->remote)[i]);
}
}
static void vlynq_dump_mem(u32 *base, int count)
{
int i;
for (i = 0; i < (count + 3) / 4; i++) {
if (i % 4 == 0)
printk(KERN_DEBUG "\nMEM[0x%04x]:", i * 4);
printk(KERN_DEBUG " 0x%08x", *(base + i));
}
printk(KERN_DEBUG "\n");
}
#endif
/* Check the VLYNQ link status with a given device */
static int vlynq_linked(struct vlynq_device *dev)
{
int i;
for (i = 0; i < 100; i++)
if (readl(&dev->local->status) & VLYNQ_STATUS_LINK)
return 1;
else
cpu_relax();
return 0;
}
static void vlynq_reset(struct vlynq_device *dev)
{
writel(readl(&dev->local->control) | VLYNQ_CTRL_RESET,
&dev->local->control);
/* Wait for the devices to finish resetting */
msleep(5);
/* Remove reset bit */
writel(readl(&dev->local->control) & ~VLYNQ_CTRL_RESET,
&dev->local->control);
/* Give some time for the devices to settle */
msleep(5);
}
static void vlynq_irq_unmask(struct irq_data *d)
{
struct vlynq_device *dev = irq_data_get_irq_chip_data(d);
int virq;
u32 val;
BUG_ON(!dev);
virq = d->irq - dev->irq_start;
val = readl(&dev->remote->int_device[virq >> 2]);
val |= (VINT_ENABLE | virq) << VINT_OFFSET(virq);
writel(val, &dev->remote->int_device[virq >> 2]);
}
static void vlynq_irq_mask(struct irq_data *d)
{
struct vlynq_device *dev = irq_data_get_irq_chip_data(d);
int virq;
u32 val;
BUG_ON(!dev);
virq = d->irq - dev->irq_start;
val = readl(&dev->remote->int_device[virq >> 2]);
val &= ~(VINT_ENABLE << VINT_OFFSET(virq));
writel(val, &dev->remote->int_device[virq >> 2]);
}
static int vlynq_irq_type(struct irq_data *d, unsigned int flow_type)
{
struct vlynq_device *dev = irq_data_get_irq_chip_data(d);
int virq;
u32 val;
BUG_ON(!dev);
virq = d->irq - dev->irq_start;
val = readl(&dev->remote->int_device[virq >> 2]);
switch (flow_type & IRQ_TYPE_SENSE_MASK) {
case IRQ_TYPE_EDGE_RISING:
case IRQ_TYPE_EDGE_FALLING:
case IRQ_TYPE_EDGE_BOTH:
val |= VINT_TYPE_EDGE << VINT_OFFSET(virq);
val &= ~(VINT_LEVEL_LOW << VINT_OFFSET(virq));
break;
case IRQ_TYPE_LEVEL_HIGH:
val &= ~(VINT_TYPE_EDGE << VINT_OFFSET(virq));
val &= ~(VINT_LEVEL_LOW << VINT_OFFSET(virq));
break;
case IRQ_TYPE_LEVEL_LOW:
val &= ~(VINT_TYPE_EDGE << VINT_OFFSET(virq));
val |= VINT_LEVEL_LOW << VINT_OFFSET(virq);
break;
default:
return -EINVAL;
}
writel(val, &dev->remote->int_device[virq >> 2]);
return 0;
}
static void vlynq_local_ack(struct irq_data *d)
{
struct vlynq_device *dev = irq_data_get_irq_chip_data(d);
u32 status = readl(&dev->local->status);
pr_debug("%s: local status: 0x%08x\n",
dev_name(&dev->dev), status);
writel(status, &dev->local->status);
}
static void vlynq_remote_ack(struct irq_data *d)
{
struct vlynq_device *dev = irq_data_get_irq_chip_data(d);
u32 status = readl(&dev->remote->status);
pr_debug("%s: remote status: 0x%08x\n",
dev_name(&dev->dev), status);
writel(status, &dev->remote->status);
}
static irqreturn_t vlynq_irq(int irq, void *dev_id)
{
struct vlynq_device *dev = dev_id;
u32 status;
int virq = 0;
status = readl(&dev->local->int_status);
writel(status, &dev->local->int_status);
if (unlikely(!status))
spurious_interrupt();
while (status) {
if (status & 1)
do_IRQ(dev->irq_start + virq);
status >>= 1;
virq++;
}
return IRQ_HANDLED;
}
static struct irq_chip vlynq_irq_chip = {
.name = "vlynq",
.irq_unmask = vlynq_irq_unmask,
.irq_mask = vlynq_irq_mask,
.irq_set_type = vlynq_irq_type,
};
static struct irq_chip vlynq_local_chip = {
.name = "vlynq local error",
.irq_unmask = vlynq_irq_unmask,
.irq_mask = vlynq_irq_mask,
.irq_ack = vlynq_local_ack,
};
static struct irq_chip vlynq_remote_chip = {
.name = "vlynq local error",
.irq_unmask = vlynq_irq_unmask,
.irq_mask = vlynq_irq_mask,
.irq_ack = vlynq_remote_ack,
};
static int vlynq_setup_irq(struct vlynq_device *dev)
{
u32 val;
int i, virq;
if (dev->local_irq == dev->remote_irq) {
printk(KERN_ERR
"%s: local vlynq irq should be different from remote\n",
dev_name(&dev->dev));
return -EINVAL;
}
/* Clear local and remote error bits */
writel(readl(&dev->local->status), &dev->local->status);
writel(readl(&dev->remote->status), &dev->remote->status);
/* Now setup interrupts */
val = VLYNQ_CTRL_INT_VECTOR(dev->local_irq);
val |= VLYNQ_CTRL_INT_ENABLE | VLYNQ_CTRL_INT_LOCAL |
VLYNQ_CTRL_INT2CFG;
val |= readl(&dev->local->control);
writel(VLYNQ_INT_OFFSET, &dev->local->int_ptr);
writel(val, &dev->local->control);
val = VLYNQ_CTRL_INT_VECTOR(dev->remote_irq);
val |= VLYNQ_CTRL_INT_ENABLE;
val |= readl(&dev->remote->control);
writel(VLYNQ_INT_OFFSET, &dev->remote->int_ptr);
writel(val, &dev->remote->int_ptr);
writel(val, &dev->remote->control);
for (i = dev->irq_start; i <= dev->irq_end; i++) {
virq = i - dev->irq_start;
if (virq == dev->local_irq) {
irq_set_chip_and_handler(i, &vlynq_local_chip,
handle_level_irq);
irq_set_chip_data(i, dev);
} else if (virq == dev->remote_irq) {
irq_set_chip_and_handler(i, &vlynq_remote_chip,
handle_level_irq);
irq_set_chip_data(i, dev);
} else {
irq_set_chip_and_handler(i, &vlynq_irq_chip,
handle_simple_irq);
irq_set_chip_data(i, dev);
writel(0, &dev->remote->int_device[virq >> 2]);
}
}
if (request_irq(dev->irq, vlynq_irq, IRQF_SHARED, "vlynq", dev)) {
printk(KERN_ERR "%s: request_irq failed\n",
dev_name(&dev->dev));
return -EAGAIN;
}
return 0;
}
static void vlynq_device_release(struct device *dev)
{
struct vlynq_device *vdev = to_vlynq_device(dev);
kfree(vdev);
}
static int vlynq_device_match(struct device *dev,
struct device_driver *drv)
{
struct vlynq_device *vdev = to_vlynq_device(dev);
struct vlynq_driver *vdrv = to_vlynq_driver(drv);
struct vlynq_device_id *ids = vdrv->id_table;
while (ids->id) {
if (ids->id == vdev->dev_id) {
vdev->divisor = ids->divisor;
vlynq_set_drvdata(vdev, ids);
printk(KERN_INFO "Driver found for VLYNQ "
"device: %08x\n", vdev->dev_id);
return 1;
}
printk(KERN_DEBUG "Not using the %08x VLYNQ device's driver"
" for VLYNQ device: %08x\n", ids->id, vdev->dev_id);
ids++;
}
return 0;
}
static int vlynq_device_probe(struct device *dev)
{
struct vlynq_device *vdev = to_vlynq_device(dev);
struct vlynq_driver *drv = to_vlynq_driver(dev->driver);
struct vlynq_device_id *id = vlynq_get_drvdata(vdev);
int result = -ENODEV;
if (drv->probe)
result = drv->probe(vdev, id);
if (result)
put_device(dev);
return result;
}
static void vlynq_device_remove(struct device *dev)
{
struct vlynq_driver *drv = to_vlynq_driver(dev->driver);
if (drv->remove)
drv->remove(to_vlynq_device(dev));
}
int __vlynq_register_driver(struct vlynq_driver *driver, struct module *owner)
{
driver->driver.name = driver->name;
driver->driver.bus = &vlynq_bus_type;
return driver_register(&driver->driver);
}
EXPORT_SYMBOL(__vlynq_register_driver);
void vlynq_unregister_driver(struct vlynq_driver *driver)
{
driver_unregister(&driver->driver);
}
EXPORT_SYMBOL(vlynq_unregister_driver);
/*
* A VLYNQ remote device can clock the VLYNQ bus master
* using a dedicated clock line. In that case, both the
* remove device and the bus master should have the same
* serial clock dividers configured. Iterate through the
* 8 possible dividers until we actually link with the
* device.
*/
static int __vlynq_try_remote(struct vlynq_device *dev)
{
int i;
vlynq_reset(dev);
for (i = dev->dev_id ? vlynq_rdiv2 : vlynq_rdiv8; dev->dev_id ?
i <= vlynq_rdiv8 : i >= vlynq_rdiv2;
dev->dev_id ? i++ : i--) {
if (!vlynq_linked(dev))
break;
writel((readl(&dev->remote->control) &
~VLYNQ_CTRL_CLOCK_MASK) |
VLYNQ_CTRL_CLOCK_INT |
VLYNQ_CTRL_CLOCK_DIV(i - vlynq_rdiv1),
&dev->remote->control);
writel((readl(&dev->local->control)
& ~(VLYNQ_CTRL_CLOCK_INT |
VLYNQ_CTRL_CLOCK_MASK)) |
VLYNQ_CTRL_CLOCK_DIV(i - vlynq_rdiv1),
&dev->local->control);
if (vlynq_linked(dev)) {
printk(KERN_DEBUG
"%s: using remote clock divisor %d\n",
dev_name(&dev->dev), i - vlynq_rdiv1 + 1);
dev->divisor = i;
return 0;
} else {
vlynq_reset(dev);
}
}
return -ENODEV;
}
/*
* A VLYNQ remote device can be clocked by the VLYNQ bus
* master using a dedicated clock line. In that case, only
* the bus master configures the serial clock divider.
* Iterate through the 8 possible dividers until we
* actually get a link with the device.
*/
static int __vlynq_try_local(struct vlynq_device *dev)
{
int i;
vlynq_reset(dev);
for (i = dev->dev_id ? vlynq_ldiv2 : vlynq_ldiv8; dev->dev_id ?
i <= vlynq_ldiv8 : i >= vlynq_ldiv2;
dev->dev_id ? i++ : i--) {
writel((readl(&dev->local->control) &
~VLYNQ_CTRL_CLOCK_MASK) |
VLYNQ_CTRL_CLOCK_INT |
VLYNQ_CTRL_CLOCK_DIV(i - vlynq_ldiv1),
&dev->local->control);
if (vlynq_linked(dev)) {
printk(KERN_DEBUG
"%s: using local clock divisor %d\n",
dev_name(&dev->dev), i - vlynq_ldiv1 + 1);
dev->divisor = i;
return 0;
} else {
vlynq_reset(dev);
}
}
return -ENODEV;
}
/*
* When using external clocking method, serial clock
* is supplied by an external oscillator, therefore we
* should mask the local clock bit in the clock control
* register for both the bus master and the remote device.
*/
static int __vlynq_try_external(struct vlynq_device *dev)
{
vlynq_reset(dev);
if (!vlynq_linked(dev))
return -ENODEV;
writel((readl(&dev->remote->control) &
~VLYNQ_CTRL_CLOCK_INT),
&dev->remote->control);
writel((readl(&dev->local->control) &
~VLYNQ_CTRL_CLOCK_INT),
&dev->local->control);
if (vlynq_linked(dev)) {
printk(KERN_DEBUG "%s: using external clock\n",
dev_name(&dev->dev));
dev->divisor = vlynq_div_external;
return 0;
}
return -ENODEV;
}
static int __vlynq_enable_device(struct vlynq_device *dev)
{
int result;
struct plat_vlynq_ops *ops = dev->dev.platform_data;
result = ops->on(dev);
if (result)
return result;
switch (dev->divisor) {
case vlynq_div_external:
case vlynq_div_auto:
/* When the device is brought from reset it should have clock
* generation negotiated by hardware.
* Check which device is generating clocks and perform setup
* accordingly */
if (vlynq_linked(dev) && readl(&dev->remote->control) &
VLYNQ_CTRL_CLOCK_INT) {
if (!__vlynq_try_remote(dev) ||
!__vlynq_try_local(dev) ||
!__vlynq_try_external(dev))
return 0;
} else {
if (!__vlynq_try_external(dev) ||
!__vlynq_try_local(dev) ||
!__vlynq_try_remote(dev))
return 0;
}
break;
case vlynq_ldiv1:
case vlynq_ldiv2:
case vlynq_ldiv3:
case vlynq_ldiv4:
case vlynq_ldiv5:
case vlynq_ldiv6:
case vlynq_ldiv7:
case vlynq_ldiv8:
writel(VLYNQ_CTRL_CLOCK_INT |
VLYNQ_CTRL_CLOCK_DIV(dev->divisor -
vlynq_ldiv1), &dev->local->control);
writel(0, &dev->remote->control);
if (vlynq_linked(dev)) {
printk(KERN_DEBUG
"%s: using local clock divisor %d\n",
dev_name(&dev->dev),
dev->divisor - vlynq_ldiv1 + 1);
return 0;
}
break;
case vlynq_rdiv1:
case vlynq_rdiv2:
case vlynq_rdiv3:
case vlynq_rdiv4:
case vlynq_rdiv5:
case vlynq_rdiv6:
case vlynq_rdiv7:
case vlynq_rdiv8:
writel(0, &dev->local->control);
writel(VLYNQ_CTRL_CLOCK_INT |
VLYNQ_CTRL_CLOCK_DIV(dev->divisor -
vlynq_rdiv1), &dev->remote->control);
if (vlynq_linked(dev)) {
printk(KERN_DEBUG
"%s: using remote clock divisor %d\n",
dev_name(&dev->dev),
dev->divisor - vlynq_rdiv1 + 1);
return 0;
}
break;
}
ops->off(dev);
return -ENODEV;
}
int vlynq_enable_device(struct vlynq_device *dev)
{
struct plat_vlynq_ops *ops = dev->dev.platform_data;
int result = -ENODEV;
result = __vlynq_enable_device(dev);
if (result)
return result;
result = vlynq_setup_irq(dev);
if (result)
ops->off(dev);
dev->enabled = !result;
return result;
}
EXPORT_SYMBOL(vlynq_enable_device);
void vlynq_disable_device(struct vlynq_device *dev)
{
struct plat_vlynq_ops *ops = dev->dev.platform_data;
dev->enabled = 0;
free_irq(dev->irq, dev);
ops->off(dev);
}
EXPORT_SYMBOL(vlynq_disable_device);
int vlynq_set_local_mapping(struct vlynq_device *dev, u32 tx_offset,
struct vlynq_mapping *mapping)
{
int i;
if (!dev->enabled)
return -ENXIO;
writel(tx_offset, &dev->local->tx_offset);
for (i = 0; i < 4; i++) {
writel(mapping[i].offset, &dev->local->rx_mapping[i].offset);
writel(mapping[i].size, &dev->local->rx_mapping[i].size);
}
return 0;
}
EXPORT_SYMBOL(vlynq_set_local_mapping);
int vlynq_set_remote_mapping(struct vlynq_device *dev, u32 tx_offset,
struct vlynq_mapping *mapping)
{
int i;
if (!dev->enabled)
return -ENXIO;
writel(tx_offset, &dev->remote->tx_offset);
for (i = 0; i < 4; i++) {
writel(mapping[i].offset, &dev->remote->rx_mapping[i].offset);
writel(mapping[i].size, &dev->remote->rx_mapping[i].size);
}
return 0;
}
EXPORT_SYMBOL(vlynq_set_remote_mapping);
int vlynq_set_local_irq(struct vlynq_device *dev, int virq)
{
int irq = dev->irq_start + virq;
if (dev->enabled)
return -EBUSY;
if ((irq < dev->irq_start) || (irq > dev->irq_end))
return -EINVAL;
if (virq == dev->remote_irq)
return -EINVAL;
dev->local_irq = virq;
return 0;
}
EXPORT_SYMBOL(vlynq_set_local_irq);
int vlynq_set_remote_irq(struct vlynq_device *dev, int virq)
{
int irq = dev->irq_start + virq;
if (dev->enabled)
return -EBUSY;
if ((irq < dev->irq_start) || (irq > dev->irq_end))
return -EINVAL;
if (virq == dev->local_irq)
return -EINVAL;
dev->remote_irq = virq;
return 0;
}
EXPORT_SYMBOL(vlynq_set_remote_irq);
static int vlynq_probe(struct platform_device *pdev)
{
struct vlynq_device *dev;
struct resource *regs_res, *mem_res, *irq_res;
int len, result;
regs_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
if (!regs_res)
return -ENODEV;
mem_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem");
if (!mem_res)
return -ENODEV;
irq_res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "devirq");
if (!irq_res)
return -ENODEV;
dev = kzalloc(sizeof(*dev), GFP_KERNEL);
if (!dev) {
printk(KERN_ERR
"vlynq: failed to allocate device structure\n");
return -ENOMEM;
}
dev->id = pdev->id;
dev->dev.bus = &vlynq_bus_type;
dev->dev.parent = &pdev->dev;
dev_set_name(&dev->dev, "vlynq%d", dev->id);
dev->dev.platform_data = pdev->dev.platform_data;
dev->dev.release = vlynq_device_release;
dev->regs_start = regs_res->start;
dev->regs_end = regs_res->end;
dev->mem_start = mem_res->start;
dev->mem_end = mem_res->end;
len = resource_size(regs_res);
if (!request_mem_region(regs_res->start, len, dev_name(&dev->dev))) {
printk(KERN_ERR "%s: Can't request vlynq registers\n",
dev_name(&dev->dev));
result = -ENXIO;
goto fail_request;
}
dev->local = ioremap(regs_res->start, len);
if (!dev->local) {
printk(KERN_ERR "%s: Can't remap vlynq registers\n",
dev_name(&dev->dev));
result = -ENXIO;
goto fail_remap;
}
dev->remote = (struct vlynq_regs *)((void *)dev->local +
VLYNQ_REMOTE_OFFSET);
dev->irq = platform_get_irq_byname(pdev, "irq");
dev->irq_start = irq_res->start;
dev->irq_end = irq_res->end;
dev->local_irq = dev->irq_end - dev->irq_start;
dev->remote_irq = dev->local_irq - 1;
if (device_register(&dev->dev))
goto fail_register;
platform_set_drvdata(pdev, dev);
printk(KERN_INFO "%s: regs 0x%p, irq %d, mem 0x%p\n",
dev_name(&dev->dev), (void *)dev->regs_start, dev->irq,
(void *)dev->mem_start);
dev->dev_id = 0;
dev->divisor = vlynq_div_auto;
result = __vlynq_enable_device(dev);
if (result == 0) {
dev->dev_id = readl(&dev->remote->chip);
((struct plat_vlynq_ops *)(dev->dev.platform_data))->off(dev);
}
if (dev->dev_id)
printk(KERN_INFO "Found a VLYNQ device: %08x\n", dev->dev_id);
return 0;
fail_register:
iounmap(dev->local);
fail_remap:
fail_request:
release_mem_region(regs_res->start, len);
kfree(dev);
return result;
}
static int vlynq_remove(struct platform_device *pdev)
{
struct vlynq_device *dev = platform_get_drvdata(pdev);
device_unregister(&dev->dev);
iounmap(dev->local);
release_mem_region(dev->regs_start,
dev->regs_end - dev->regs_start + 1);
kfree(dev);
return 0;
}
static struct platform_driver vlynq_platform_driver = {
.driver.name = "vlynq",
.probe = vlynq_probe,
.remove = vlynq_remove,
};
struct bus_type vlynq_bus_type = {
.name = "vlynq",
.match = vlynq_device_match,
.probe = vlynq_device_probe,
.remove = vlynq_device_remove,
};
EXPORT_SYMBOL(vlynq_bus_type);
static int vlynq_init(void)
{
int res = 0;
res = bus_register(&vlynq_bus_type);
if (res)
goto fail_bus;
res = platform_driver_register(&vlynq_platform_driver);
if (res)
goto fail_platform;
return 0;
fail_platform:
bus_unregister(&vlynq_bus_type);
fail_bus:
return res;
}
static void vlynq_exit(void)
{
platform_driver_unregister(&vlynq_platform_driver);
bus_unregister(&vlynq_bus_type);
}
module_init(vlynq_init);
module_exit(vlynq_exit);

6
drivers/watchdog/Kconfig
View File

@ -1768,12 +1768,6 @@ config SIBYTE_WDOG
To compile this driver as a loadable module, choose M here.
The module will be called sb_wdog.
config AR7_WDT
tristate "TI AR7 Watchdog Timer"
depends on AR7 || (MIPS && 32BIT && COMPILE_TEST)
help
Hardware driver for the TI AR7 Watchdog Timer.
config TXX9_WDT
tristate "Toshiba TXx9 Watchdog Timer"
depends on CPU_TX49XX || (MIPS && COMPILE_TEST)

1
drivers/watchdog/Makefile
View File

@ -168,7 +168,6 @@ obj-$(CONFIG_INDYDOG) += indydog.o
obj-$(CONFIG_JZ4740_WDT) += jz4740_wdt.o
obj-$(CONFIG_WDT_MTX1) += mtx-1_wdt.o
obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o
obj-$(CONFIG_AR7_WDT) += ar7_wdt.o
obj-$(CONFIG_TXX9_WDT) += txx9wdt.o
obj-$(CONFIG_OCTEON_WDT) += octeon-wdt.o
octeon-wdt-y := octeon-wdt-main.o octeon-wdt-nmi.o

315
drivers/watchdog/ar7_wdt.c
View File

@ -1,315 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* drivers/watchdog/ar7_wdt.c
*
* Copyright (C) 2007 Nicolas Thill <nico@openwrt.org>
* Copyright (c) 2005 Enrik Berkhan <Enrik.Berkhan@akk.org>
*
* Some code taken from:
* National Semiconductor SCx200 Watchdog support
* Copyright (c) 2001,2002 Christer Weinigel <wingel@nano-system.com>
*
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/errno.h>
#include <linux/miscdevice.h>
#include <linux/platform_device.h>
#include <linux/watchdog.h>
#include <linux/fs.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/uaccess.h>
#include <linux/clk.h>
#include <asm/addrspace.h>
#include <asm/mach-ar7/ar7.h>
#define LONGNAME "TI AR7 Watchdog Timer"
MODULE_AUTHOR("Nicolas Thill <nico@openwrt.org>");
MODULE_DESCRIPTION(LONGNAME);
MODULE_LICENSE("GPL");
static int margin = 60;
module_param(margin, int, 0);
MODULE_PARM_DESC(margin, "Watchdog margin in seconds");
static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Disable watchdog shutdown on close");
#define READ_REG(x) readl((void __iomem *)&(x))
#define WRITE_REG(x, v) writel((v), (void __iomem *)&(x))
struct ar7_wdt {
u32 kick_lock;
u32 kick;
u32 change_lock;
u32 change;
u32 disable_lock;
u32 disable;
u32 prescale_lock;
u32 prescale;
};
static unsigned long wdt_is_open;
static unsigned expect_close;
static DEFINE_SPINLOCK(wdt_lock);
/* XXX currently fixed, allows max margin ~68.72 secs */
#define prescale_value 0xffff
/* Pointer to the remapped WDT IO space */
static struct ar7_wdt *ar7_wdt;
static struct clk *vbus_clk;
static void ar7_wdt_kick(u32 value)
{
WRITE_REG(ar7_wdt->kick_lock, 0x5555);
if ((READ_REG(ar7_wdt->kick_lock) & 3) == 1) {
WRITE_REG(ar7_wdt->kick_lock, 0xaaaa);
if ((READ_REG(ar7_wdt->kick_lock) & 3) == 3) {
WRITE_REG(ar7_wdt->kick, value);
return;
}
}
pr_err("failed to unlock WDT kick reg\n");
}
static void ar7_wdt_prescale(u32 value)
{
WRITE_REG(ar7_wdt->prescale_lock, 0x5a5a);
if ((READ_REG(ar7_wdt->prescale_lock) & 3) == 1) {
WRITE_REG(ar7_wdt->prescale_lock, 0xa5a5);
if ((READ_REG(ar7_wdt->prescale_lock) & 3) == 3) {
WRITE_REG(ar7_wdt->prescale, value);
return;
}
}
pr_err("failed to unlock WDT prescale reg\n");
}
static void ar7_wdt_change(u32 value)
{
WRITE_REG(ar7_wdt->change_lock, 0x6666);
if ((READ_REG(ar7_wdt->change_lock) & 3) == 1) {
WRITE_REG(ar7_wdt->change_lock, 0xbbbb);
if ((READ_REG(ar7_wdt->change_lock) & 3) == 3) {
WRITE_REG(ar7_wdt->change, value);
return;
}
}
pr_err("failed to unlock WDT change reg\n");
}
static void ar7_wdt_disable(u32 value)
{
WRITE_REG(ar7_wdt->disable_lock, 0x7777);
if ((READ_REG(ar7_wdt->disable_lock) & 3) == 1) {
WRITE_REG(ar7_wdt->disable_lock, 0xcccc);
if ((READ_REG(ar7_wdt->disable_lock) & 3) == 2) {
WRITE_REG(ar7_wdt->disable_lock, 0xdddd);
if ((READ_REG(ar7_wdt->disable_lock) & 3) == 3) {
WRITE_REG(ar7_wdt->disable, value);
return;
}
}
}
pr_err("failed to unlock WDT disable reg\n");
}
static void ar7_wdt_update_margin(int new_margin)
{
u32 change;
u32 vbus_rate;
vbus_rate = clk_get_rate(vbus_clk);
change = new_margin * (vbus_rate / prescale_value);
if (change < 1)
change = 1;
if (change > 0xffff)
change = 0xffff;
ar7_wdt_change(change);
margin = change * prescale_value / vbus_rate;
pr_info("timer margin %d seconds (prescale %d, change %d, freq %d)\n",
margin, prescale_value, change, vbus_rate);
}
static void ar7_wdt_enable_wdt(void)
{
pr_debug("enabling watchdog timer\n");
ar7_wdt_disable(1);
ar7_wdt_kick(1);
}
static void ar7_wdt_disable_wdt(void)
{
pr_debug("disabling watchdog timer\n");
ar7_wdt_disable(0);
}
static int ar7_wdt_open(struct inode *inode, struct file *file)
{
/* only allow one at a time */
if (test_and_set_bit(0, &wdt_is_open))
return -EBUSY;
ar7_wdt_enable_wdt();
expect_close = 0;
return stream_open(inode, file);
}
static int ar7_wdt_release(struct inode *inode, struct file *file)
{
if (!expect_close)
pr_warn("watchdog device closed unexpectedly, will not disable the watchdog timer\n");
else if (!nowayout)
ar7_wdt_disable_wdt();
clear_bit(0, &wdt_is_open);
return 0;
}
static ssize_t ar7_wdt_write(struct file *file, const char *data,
size_t len, loff_t *ppos)
{
/* check for a magic close character */
if (len) {
size_t i;
spin_lock(&wdt_lock);
ar7_wdt_kick(1);
spin_unlock(&wdt_lock);
expect_close = 0;
for (i = 0; i < len; ++i) {
char c;
if (get_user(c, data + i))
return -EFAULT;
if (c == 'V')
expect_close = 1;
}
}
return len;
}
static long ar7_wdt_ioctl(struct file *file,
unsigned int cmd, unsigned long arg)
{
static const struct watchdog_info ident = {
.identity = LONGNAME,
.firmware_version = 1,
.options = (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
WDIOF_MAGICCLOSE),
};
int new_margin;
switch (cmd) {
case WDIOC_GETSUPPORT:
if (copy_to_user((struct watchdog_info *)arg, &ident,
sizeof(ident)))
return -EFAULT;
return 0;
case WDIOC_GETSTATUS:
case WDIOC_GETBOOTSTATUS:
if (put_user(0, (int *)arg))
return -EFAULT;
return 0;
case WDIOC_KEEPALIVE:
ar7_wdt_kick(1);
return 0;
case WDIOC_SETTIMEOUT:
if (get_user(new_margin, (int *)arg))
return -EFAULT;
if (new_margin < 1)
return -EINVAL;
spin_lock(&wdt_lock);
ar7_wdt_update_margin(new_margin);
ar7_wdt_kick(1);
spin_unlock(&wdt_lock);
fallthrough;
case WDIOC_GETTIMEOUT:
if (put_user(margin, (int *)arg))
return -EFAULT;
return 0;
default:
return -ENOTTY;
}
}
static const struct file_operations ar7_wdt_fops = {
.owner = THIS_MODULE,
.write = ar7_wdt_write,
.unlocked_ioctl = ar7_wdt_ioctl,
.compat_ioctl = compat_ptr_ioctl,
.open = ar7_wdt_open,
.release = ar7_wdt_release,
.llseek = no_llseek,
};
static struct miscdevice ar7_wdt_miscdev = {
.minor = WATCHDOG_MINOR,
.name = "watchdog",
.fops = &ar7_wdt_fops,
};
static int ar7_wdt_probe(struct platform_device *pdev)
{
int rc;
ar7_wdt = devm_platform_ioremap_resource_byname(pdev, "regs");
if (IS_ERR(ar7_wdt))
return PTR_ERR(ar7_wdt);
vbus_clk = clk_get(NULL, "vbus");
if (IS_ERR(vbus_clk)) {
pr_err("could not get vbus clock\n");
return PTR_ERR(vbus_clk);
}
ar7_wdt_disable_wdt();
ar7_wdt_prescale(prescale_value);
ar7_wdt_update_margin(margin);
rc = misc_register(&ar7_wdt_miscdev);
if (rc) {
pr_err("unable to register misc device\n");
goto out;
}
return 0;
out:
clk_put(vbus_clk);
vbus_clk = NULL;
return rc;
}
static void ar7_wdt_remove(struct platform_device *pdev)
{
misc_deregister(&ar7_wdt_miscdev);
clk_put(vbus_clk);
vbus_clk = NULL;
}
static void ar7_wdt_shutdown(struct platform_device *pdev)
{
if (!nowayout)
ar7_wdt_disable_wdt();
}
static struct platform_driver ar7_wdt_driver = {
.probe = ar7_wdt_probe,
.remove_new = ar7_wdt_remove,
.shutdown = ar7_wdt_shutdown,
.driver = {
.name = "ar7_wdt",
},
};
module_platform_driver(ar7_wdt_driver);

149
include/linux/vlynq.h
View File

@ -1,149 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2006, 2007 Eugene Konev <ejka@openwrt.org>
*/
#ifndef __VLYNQ_H__
#define __VLYNQ_H__
#include <linux/device.h>
#include <linux/types.h>
struct module;
#define VLYNQ_NUM_IRQS 32
struct vlynq_mapping {
u32 size;
u32 offset;
};
enum vlynq_divisor {
vlynq_div_auto = 0,
vlynq_ldiv1,
vlynq_ldiv2,
vlynq_ldiv3,
vlynq_ldiv4,
vlynq_ldiv5,
vlynq_ldiv6,
vlynq_ldiv7,
vlynq_ldiv8,
vlynq_rdiv1,
vlynq_rdiv2,
vlynq_rdiv3,
vlynq_rdiv4,
vlynq_rdiv5,
vlynq_rdiv6,
vlynq_rdiv7,
vlynq_rdiv8,
vlynq_div_external
};
struct vlynq_device_id {
u32 id;
enum vlynq_divisor divisor;
unsigned long driver_data;
};
struct vlynq_regs;
struct vlynq_device {
u32 id, dev_id;
int local_irq;
int remote_irq;
enum vlynq_divisor divisor;
u32 regs_start, regs_end;
u32 mem_start, mem_end;
u32 irq_start, irq_end;
int irq;
int enabled;
struct vlynq_regs *local;
struct vlynq_regs *remote;
struct device dev;
};
struct vlynq_driver {
char *name;
struct vlynq_device_id *id_table;
int (*probe)(struct vlynq_device *dev, struct vlynq_device_id *id);
void (*remove)(struct vlynq_device *dev);
struct device_driver driver;
};
struct plat_vlynq_ops {
int (*on)(struct vlynq_device *dev);
void (*off)(struct vlynq_device *dev);
};
static inline struct vlynq_driver *to_vlynq_driver(struct device_driver *drv)
{
return container_of(drv, struct vlynq_driver, driver);
}
static inline struct vlynq_device *to_vlynq_device(struct device *device)
{
return container_of(device, struct vlynq_device, dev);
}
extern struct bus_type vlynq_bus_type;
extern int __vlynq_register_driver(struct vlynq_driver *driver,
struct module *owner);
static inline int vlynq_register_driver(struct vlynq_driver *driver)
{
return __vlynq_register_driver(driver, THIS_MODULE);
}
static inline void *vlynq_get_drvdata(struct vlynq_device *dev)
{
return dev_get_drvdata(&dev->dev);
}
static inline void vlynq_set_drvdata(struct vlynq_device *dev, void *data)
{
dev_set_drvdata(&dev->dev, data);
}
static inline u32 vlynq_mem_start(struct vlynq_device *dev)
{
return dev->mem_start;
}
static inline u32 vlynq_mem_end(struct vlynq_device *dev)
{
return dev->mem_end;
}
static inline u32 vlynq_mem_len(struct vlynq_device *dev)
{
return dev->mem_end - dev->mem_start + 1;
}
static inline int vlynq_virq_to_irq(struct vlynq_device *dev, int virq)
{
int irq = dev->irq_start + virq;
if ((irq < dev->irq_start) || (irq > dev->irq_end))
return -EINVAL;
return irq;
}
static inline int vlynq_irq_to_virq(struct vlynq_device *dev, int irq)
{
if ((irq < dev->irq_start) || (irq > dev->irq_end))
return -EINVAL;
return irq - dev->irq_start;
}
extern void vlynq_unregister_driver(struct vlynq_driver *driver);
extern int vlynq_enable_device(struct vlynq_device *dev);
extern void vlynq_disable_device(struct vlynq_device *dev);
extern int vlynq_set_local_mapping(struct vlynq_device *dev, u32 tx_offset,
struct vlynq_mapping *mapping);
extern int vlynq_set_remote_mapping(struct vlynq_device *dev, u32 tx_offset,
struct vlynq_mapping *mapping);
extern int vlynq_set_local_irq(struct vlynq_device *dev, int virq);
extern int vlynq_set_remote_irq(struct vlynq_device *dev, int virq);
#endif /* __VLYNQ_H__ */