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soc: mediatek: Support reset bit mapping in mmsys driver
- Reset ID must starts from 0 and be consecutive, but the reset bits in our hardware design is not continuous, some bits are left unused, we need a map to solve the problem - Use old style 1-to-1 mapping if .rst_tb is not defined Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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@ -324,6 +324,15 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l
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u32 offset;
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u32 reg;
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if (mmsys->data->rst_tb) {
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if (id >= mmsys->data->num_resets) {
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dev_err(rcdev->dev, "Invalid reset ID: %lu (>=%u)\n",
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id, mmsys->data->num_resets);
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return -EINVAL;
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}
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id = mmsys->data->rst_tb[id];
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}
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offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
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id = id % MMSYS_SW_RESET_PER_REG;
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reg = mmsys->data->sw0_rst_offset + offset;
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@ -78,6 +78,8 @@
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#define DSI_SEL_IN_RDMA 0x1
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#define DSI_SEL_IN_MASK 0x1
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#define MMSYS_RST_NR(bank, bit) (((bank) * 32) + (bit))
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struct mtk_mmsys_routes {
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u32 from_comp;
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u32 to_comp;
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@ -119,6 +121,7 @@ struct mtk_mmsys_driver_data {
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const struct mtk_mmsys_routes *routes;
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const unsigned int num_routes;
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const u16 sw0_rst_offset;
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const u8 *rst_tb;
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const u32 num_resets;
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const bool is_vppsys;
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const u8 vsync_len;
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