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net: phy: introduce core support for phy-mode = "10g-qxgmii"
10G-QXGMII is a MAC-to-PHY interface defined by the USXGMII multiport specification. It uses the same signaling as USXGMII, but it multiplexes 4 ports over the link, resulting in a maximum speed of 2.5G per port. Some in-tree SoCs like the NXP LS1028A use "usxgmii" when they mean either the single-port USXGMII or the quad-port 10G-QXGMII variant, and they could get away just fine with that thus far. But there is a need to distinguish between the 2 as far as SerDes drivers are concerned. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Luo Jie <quic_luoj@quicinc.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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@ -327,6 +327,12 @@ Some of the interface modes are described below:
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This is the Penta SGMII mode, it is similar to QSGMII but it combines 5
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SGMII lines into a single link compared to 4 on QSGMII.
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``PHY_INTERFACE_MODE_10G_QXGMII``
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Represents the 10G-QXGMII PHY-MAC interface as defined by the Cisco USXGMII
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Multiport Copper Interface document. It supports 4 ports over a 10.3125 GHz
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SerDes lane, each port having speeds of 2.5G / 1G / 100M / 10M achieved
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through symbol replication. The PCS expects the standard USXGMII code word.
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Pause frames / flow control
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===========================
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@ -141,6 +141,7 @@ int phy_interface_num_ports(phy_interface_t interface)
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return 1;
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case PHY_INTERFACE_MODE_QSGMII:
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case PHY_INTERFACE_MODE_QUSGMII:
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case PHY_INTERFACE_MODE_10G_QXGMII:
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return 4;
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case PHY_INTERFACE_MODE_PSGMII:
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return 5;
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@ -231,6 +231,7 @@ static int phylink_interface_max_speed(phy_interface_t interface)
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return SPEED_1000;
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case PHY_INTERFACE_MODE_2500BASEX:
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case PHY_INTERFACE_MODE_10G_QXGMII:
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return SPEED_2500;
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case PHY_INTERFACE_MODE_5GBASER:
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@ -500,7 +501,11 @@ static unsigned long phylink_get_capabilities(phy_interface_t interface,
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switch (interface) {
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case PHY_INTERFACE_MODE_USXGMII:
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caps |= MAC_10000FD | MAC_5000FD | MAC_2500FD;
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caps |= MAC_10000FD | MAC_5000FD;
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fallthrough;
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case PHY_INTERFACE_MODE_10G_QXGMII:
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caps |= MAC_2500FD;
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fallthrough;
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case PHY_INTERFACE_MODE_RGMII_TXID:
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@ -926,6 +931,7 @@ static int phylink_parse_mode(struct phylink *pl,
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case PHY_INTERFACE_MODE_5GBASER:
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case PHY_INTERFACE_MODE_25GBASER:
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case PHY_INTERFACE_MODE_USXGMII:
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case PHY_INTERFACE_MODE_10G_QXGMII:
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case PHY_INTERFACE_MODE_10GKR:
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case PHY_INTERFACE_MODE_10GBASER:
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case PHY_INTERFACE_MODE_XLGMII:
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@ -1124,6 +1130,7 @@ static unsigned int phylink_pcs_neg_mode(unsigned int mode,
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case PHY_INTERFACE_MODE_QSGMII:
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case PHY_INTERFACE_MODE_QUSGMII:
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case PHY_INTERFACE_MODE_USXGMII:
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case PHY_INTERFACE_MODE_10G_QXGMII:
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/* These protocols are designed for use with a PHY which
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* communicates its negotiation result back to the MAC via
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* inband communication. Note: there exist PHYs that run
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@ -128,6 +128,7 @@ extern const int phy_10gbit_features_array[1];
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* @PHY_INTERFACE_MODE_10GKR: 10GBASE-KR - with Clause 73 AN
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* @PHY_INTERFACE_MODE_QUSGMII: Quad Universal SGMII
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* @PHY_INTERFACE_MODE_1000BASEKX: 1000Base-KX - with Clause 73 AN
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* @PHY_INTERFACE_MODE_10G_QXGMII: 10G-QXGMII - 4 ports over 10G USXGMII
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* @PHY_INTERFACE_MODE_MAX: Book keeping
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*
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* Describes the interface between the MAC and PHY.
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@ -168,6 +169,7 @@ typedef enum {
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PHY_INTERFACE_MODE_10GKR,
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PHY_INTERFACE_MODE_QUSGMII,
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PHY_INTERFACE_MODE_1000BASEKX,
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PHY_INTERFACE_MODE_10G_QXGMII,
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PHY_INTERFACE_MODE_MAX,
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} phy_interface_t;
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@ -289,6 +291,8 @@ static inline const char *phy_modes(phy_interface_t interface)
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return "100base-x";
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case PHY_INTERFACE_MODE_QUSGMII:
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return "qusgmii";
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case PHY_INTERFACE_MODE_10G_QXGMII:
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return "10g-qxgmii";
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default:
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return "unknown";
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}
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@ -654,6 +654,7 @@ static inline int phylink_get_link_timer_ns(phy_interface_t interface)
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case PHY_INTERFACE_MODE_SGMII:
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case PHY_INTERFACE_MODE_QSGMII:
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case PHY_INTERFACE_MODE_USXGMII:
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case PHY_INTERFACE_MODE_10G_QXGMII:
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return 1600000;
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case PHY_INTERFACE_MODE_1000BASEX:
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