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[ARM] 3086/1: ixp2xxx error irq handling
Patch from Dave Jiang This provides support for IXP2xxx error interrupt handling. Previously there was a patch to remove this (although the original stuff was broken). Well, now the error bits are needed again. These are used extensively by the micro-engine drivers according to Deepak and also we will need it for the new EDAC code that Alan Cox is trying to push into the main kernel. Re-submit of 3072/1, generated against git tree pulled today. AFAICT, this git tree pulled in all the ARM changes that's in arm.diff. Please let me know if there are additional changes. Thx! Signed-off-by: Dave Jiang <djiang@mvista.com> Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -402,6 +402,40 @@ static void ixp2000_pci_irq_unmask(unsigned int irq)
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ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 27)));
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}
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/*
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* Error interrupts. These are used extensively by the microengine drivers
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*/
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static void ixp2000_err_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
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{
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int i;
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unsigned long status = *IXP2000_IRQ_ERR_STATUS;
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for(i = 31; i >= 0; i--) {
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if(status & (1 << i)) {
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desc = irq_desc + IRQ_IXP2000_DRAM0_MIN_ERR + i;
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desc->handle(IRQ_IXP2000_DRAM0_MIN_ERR + i, desc, regs);
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}
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}
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}
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static void ixp2000_err_irq_mask(unsigned int irq)
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{
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ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_CLR,
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(1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
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}
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static void ixp2000_err_irq_unmask(unsigned int irq)
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{
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ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_SET,
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(1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
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}
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static struct irqchip ixp2000_err_irq_chip = {
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.ack = ixp2000_err_irq_mask,
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.mask = ixp2000_err_irq_mask,
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.unmask = ixp2000_err_irq_unmask
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};
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static struct irqchip ixp2000_pci_irq_chip = {
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.ack = ixp2000_pci_irq_mask,
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.mask = ixp2000_pci_irq_mask,
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@ -459,6 +493,18 @@ void __init ixp2000_init_irq(void)
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} else set_irq_flags(irq, 0);
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}
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for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) {
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if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) &
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IXP2000_VALID_ERR_IRQ_MASK) {
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set_irq_chip(irq, &ixp2000_err_irq_chip);
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set_irq_handler(irq, do_level_IRQ);
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set_irq_flags(irq, IRQF_VALID);
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}
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else
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set_irq_flags(irq, 0);
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}
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set_irq_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler);
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/*
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* GPIO IRQs are invalid until someone sets the interrupt mode
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* by calling set_irq_type().
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@ -67,12 +67,45 @@
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#define IRQ_IXP2000_PCIA 40
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#define IRQ_IXP2000_PCIB 41
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#define NR_IXP2000_IRQS 42
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/* Int sources from IRQ_ERROR_STATUS */
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#define IRQ_IXP2000_DRAM0_MIN_ERR 42
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#define IRQ_IXP2000_DRAM0_MAJ_ERR 43
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#define IRQ_IXP2000_DRAM1_MIN_ERR 44
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#define IRQ_IXP2000_DRAM1_MAJ_ERR 45
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#define IRQ_IXP2000_DRAM2_MIN_ERR 46
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#define IRQ_IXP2000_DRAM2_MAJ_ERR 47
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/* 48-57 reserved */
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#define IRQ_IXP2000_SRAM0_ERR 58
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#define IRQ_IXP2000_SRAM1_ERR 59
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#define IRQ_IXP2000_SRAM2_ERR 60
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#define IRQ_IXP2000_SRAM3_ERR 61
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/* 62-65 reserved */
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#define IRQ_IXP2000_MEDIA_ERR 66
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#define IRQ_IXP2000_PCI_ERR 67
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#define IRQ_IXP2000_SP_INT 68
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#define NR_IXP2000_IRQS 69
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#define IXP2000_BOARD_IRQ(x) (NR_IXP2000_IRQS + (x))
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#define IXP2000_BOARD_IRQ_MASK(irq) (1 << (irq - NR_IXP2000_IRQS))
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#define IXP2000_ERR_IRQ_MASK(irq) ( 1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR))
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#define IXP2000_VALID_ERR_IRQ_MASK (\
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IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM0_MIN_ERR) | \
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IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM0_MAJ_ERR) | \
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IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM1_MIN_ERR) | \
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IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM1_MAJ_ERR) | \
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IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM2_MIN_ERR) | \
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IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM2_MAJ_ERR) | \
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IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM0_ERR) | \
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IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM1_ERR) | \
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IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM2_ERR) | \
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IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM3_ERR) | \
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IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_MEDIA_ERR) | \
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IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_PCI_ERR) | \
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IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SP_INT) )
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/*
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* This allows for all the on-chip sources plus up to 32 CPLD based
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* IRQs. Should be more than enough.
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