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clk: qcom: dispcc-sdm845: convert to parent data
Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210405224743.590029-12-dmitry.baryshkov@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Dmitry Baryshkov
Stephen Boyd
parent
2e30f6492c
commit
7acd225129
@ -33,6 +33,21 @@ enum {
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P_DP_PHY_PLL_VCO_DIV_CLK,
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};
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static struct clk_alpha_pll disp_cc_pll0 = {
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.offset = 0x0,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_pll0",
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.parent_data = &(const struct clk_parent_data){
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.fw_name = "bi_tcxo", .name = "bi_tcxo",
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_fabia_ops,
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},
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},
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};
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static const struct parent_map disp_cc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
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@ -40,11 +55,11 @@ static const struct parent_map disp_cc_parent_map_0[] = {
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const char * const disp_cc_parent_names_0[] = {
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"bi_tcxo",
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"dsi0_phy_pll_out_byteclk",
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"dsi1_phy_pll_out_byteclk",
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"core_bi_pll_test_se",
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static const struct clk_parent_data disp_cc_parent_data_0[] = {
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{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
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{ .fw_name = "dsi0_phy_pll_out_byteclk", .name = "dsi0_phy_pll_out_byteclk" },
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{ .fw_name = "dsi1_phy_pll_out_byteclk", .name = "dsi1_phy_pll_out_byteclk" },
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{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
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};
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static const struct parent_map disp_cc_parent_map_1[] = {
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@ -54,11 +69,11 @@ static const struct parent_map disp_cc_parent_map_1[] = {
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const char * const disp_cc_parent_names_1[] = {
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"bi_tcxo",
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"dp_link_clk_divsel_ten",
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"dp_vco_divided_clk_src_mux",
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"core_bi_pll_test_se",
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static const struct clk_parent_data disp_cc_parent_data_1[] = {
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{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
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{ .fw_name = "dp_link_clk_divsel_ten", .name = "dp_link_clk_divsel_ten" },
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{ .fw_name = "dp_vco_divided_clk_src_mux", .name = "dp_vco_divided_clk_src_mux" },
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{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
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};
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static const struct parent_map disp_cc_parent_map_2[] = {
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@ -66,9 +81,9 @@ static const struct parent_map disp_cc_parent_map_2[] = {
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const char * const disp_cc_parent_names_2[] = {
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"bi_tcxo",
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"core_bi_pll_test_se",
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static const struct clk_parent_data disp_cc_parent_data_2[] = {
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{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
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{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
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};
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static const struct parent_map disp_cc_parent_map_3[] = {
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@ -79,12 +94,12 @@ static const struct parent_map disp_cc_parent_map_3[] = {
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const char * const disp_cc_parent_names_3[] = {
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"bi_tcxo",
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"disp_cc_pll0",
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"gcc_disp_gpll0_clk_src",
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"gcc_disp_gpll0_div_clk_src",
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"core_bi_pll_test_se",
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static const struct clk_parent_data disp_cc_parent_data_3[] = {
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{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
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{ .hw = &disp_cc_pll0.clkr.hw },
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{ .fw_name = "gcc_disp_gpll0_clk_src", .name = "gcc_disp_gpll0_clk_src" },
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{ .fw_name = "gcc_disp_gpll0_div_clk_src", .name = "gcc_disp_gpll0_div_clk_src" },
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{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
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};
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static const struct parent_map disp_cc_parent_map_4[] = {
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@ -94,24 +109,11 @@ static const struct parent_map disp_cc_parent_map_4[] = {
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const char * const disp_cc_parent_names_4[] = {
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"bi_tcxo",
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"dsi0_phy_pll_out_dsiclk",
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"dsi1_phy_pll_out_dsiclk",
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"core_bi_pll_test_se",
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};
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static struct clk_alpha_pll disp_cc_pll0 = {
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.offset = 0x0,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_pll0",
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.parent_names = (const char *[]){ "bi_tcxo" },
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.num_parents = 1,
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.ops = &clk_alpha_pll_fabia_ops,
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},
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},
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static const struct clk_parent_data disp_cc_parent_data_4[] = {
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{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
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{ .fw_name = "dsi0_phy_pll_out_dsiclk", .name = "dsi0_phy_pll_out_dsiclk" },
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{ .fw_name = "dsi1_phy_pll_out_dsiclk", .name = "dsi1_phy_pll_out_dsiclk" },
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{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
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};
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/* Return the HW recalc rate for idle use case */
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@ -122,8 +124,8 @@ static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
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.parent_map = disp_cc_parent_map_0,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_byte0_clk_src",
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.parent_names = disp_cc_parent_names_0,
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.num_parents = 4,
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.parent_data = disp_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_byte2_ops,
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},
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@ -137,8 +139,8 @@ static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
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.parent_map = disp_cc_parent_map_0,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_byte1_clk_src",
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.parent_names = disp_cc_parent_names_0,
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.num_parents = 4,
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.parent_data = disp_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_byte2_ops,
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},
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@ -157,8 +159,8 @@ static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
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.freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_dp_aux_clk_src",
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.parent_names = disp_cc_parent_names_2,
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.num_parents = 2,
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.parent_data = disp_cc_parent_data_2,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_ops,
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},
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@ -171,8 +173,8 @@ static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
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.parent_map = disp_cc_parent_map_1,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_dp_crypto_clk_src",
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.parent_names = disp_cc_parent_names_1,
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.num_parents = 4,
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.parent_data = disp_cc_parent_data_1,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
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.ops = &clk_byte2_ops,
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},
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};
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@ -184,8 +186,8 @@ static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
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.parent_map = disp_cc_parent_map_1,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_dp_link_clk_src",
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.parent_names = disp_cc_parent_names_1,
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.num_parents = 4,
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.parent_data = disp_cc_parent_data_1,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_byte2_ops,
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},
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@ -198,8 +200,8 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = {
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.parent_map = disp_cc_parent_map_1,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_dp_pixel1_clk_src",
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.parent_names = disp_cc_parent_names_1,
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.num_parents = 4,
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.parent_data = disp_cc_parent_data_1,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_dp_ops,
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},
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@ -212,8 +214,8 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
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.parent_map = disp_cc_parent_map_1,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_dp_pixel_clk_src",
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.parent_names = disp_cc_parent_names_1,
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.num_parents = 4,
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.parent_data = disp_cc_parent_data_1,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_dp_ops,
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},
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@ -232,8 +234,8 @@ static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
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.freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_esc0_clk_src",
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.parent_names = disp_cc_parent_names_0,
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.num_parents = 4,
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.parent_data = disp_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
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.ops = &clk_rcg2_ops,
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},
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};
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@ -246,8 +248,8 @@ static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {
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.freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_esc1_clk_src",
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.parent_names = disp_cc_parent_names_0,
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.num_parents = 4,
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.parent_data = disp_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
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.ops = &clk_rcg2_ops,
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},
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};
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@ -273,8 +275,8 @@ static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
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.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_mdp_clk_src",
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.parent_names = disp_cc_parent_names_3,
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.num_parents = 5,
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.parent_data = disp_cc_parent_data_3,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
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.ops = &clk_rcg2_shared_ops,
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},
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};
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@ -287,8 +289,8 @@ static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
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.parent_map = disp_cc_parent_map_4,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_pclk0_clk_src",
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.parent_names = disp_cc_parent_names_4,
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.num_parents = 4,
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.parent_data = disp_cc_parent_data_4,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_pixel_ops,
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},
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@ -302,8 +304,8 @@ static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = {
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.parent_map = disp_cc_parent_map_4,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_pclk1_clk_src",
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.parent_names = disp_cc_parent_names_4,
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.num_parents = 4,
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.parent_data = disp_cc_parent_data_4,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_pixel_ops,
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},
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@ -326,8 +328,8 @@ static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
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.freq_tbl = ftbl_disp_cc_mdss_rot_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_rot_clk_src",
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.parent_names = disp_cc_parent_names_3,
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.num_parents = 5,
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.parent_data = disp_cc_parent_data_3,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
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.ops = &clk_rcg2_shared_ops,
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},
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};
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@ -340,8 +342,8 @@ static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
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.freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_vsync_clk_src",
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.parent_names = disp_cc_parent_names_2,
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.num_parents = 2,
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.parent_data = disp_cc_parent_data_2,
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
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.ops = &clk_rcg2_ops,
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},
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};
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@ -381,8 +383,8 @@ static struct clk_branch disp_cc_mdss_byte0_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_byte0_clk",
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.parent_names = (const char *[]){
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"disp_cc_mdss_byte0_clk_src",
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.parent_hws = (const struct clk_hw*[]){
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&disp_cc_mdss_byte0_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -399,8 +401,8 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_byte0_div_clk_src",
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.parent_names = (const char *[]){
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"disp_cc_mdss_byte0_clk_src",
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.parent_hws = (const struct clk_hw*[]){
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&disp_cc_mdss_byte0_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.ops = &clk_regmap_div_ops,
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@ -417,8 +419,8 @@ static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_byte0_intf_clk",
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.parent_names = (const char *[]){
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"disp_cc_mdss_byte0_div_clk_src",
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.parent_hws = (const struct clk_hw*[]){
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&disp_cc_mdss_byte0_div_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -436,8 +438,8 @@ static struct clk_branch disp_cc_mdss_byte1_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_byte1_clk",
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.parent_names = (const char *[]){
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"disp_cc_mdss_byte1_clk_src",
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.parent_hws = (const struct clk_hw*[]){
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&disp_cc_mdss_byte1_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -454,8 +456,8 @@ static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = {
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_byte1_div_clk_src",
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.parent_names = (const char *[]){
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"disp_cc_mdss_byte1_clk_src",
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.parent_hws = (const struct clk_hw*[]){
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&disp_cc_mdss_byte1_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.ops = &clk_regmap_div_ops,
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@ -472,8 +474,8 @@ static struct clk_branch disp_cc_mdss_byte1_intf_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_byte1_intf_clk",
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.parent_names = (const char *[]){
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"disp_cc_mdss_byte1_div_clk_src",
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.parent_hws = (const struct clk_hw*[]){
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&disp_cc_mdss_byte1_div_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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@ -490,8 +492,8 @@ static struct clk_branch disp_cc_mdss_dp_aux_clk = {
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "disp_cc_mdss_dp_aux_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"disp_cc_mdss_dp_aux_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_dp_aux_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -508,8 +510,8 @@ static struct clk_branch disp_cc_mdss_dp_crypto_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_dp_crypto_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"disp_cc_mdss_dp_crypto_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_dp_crypto_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -526,8 +528,8 @@ static struct clk_branch disp_cc_mdss_dp_link_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_dp_link_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"disp_cc_mdss_dp_link_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_dp_link_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -545,8 +547,8 @@ static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_dp_link_intf_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"disp_cc_mdss_dp_link_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_dp_link_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_branch2_ops,
|
||||
@ -562,8 +564,8 @@ static struct clk_branch disp_cc_mdss_dp_pixel1_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_dp_pixel1_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"disp_cc_mdss_dp_pixel1_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_dp_pixel1_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -580,8 +582,8 @@ static struct clk_branch disp_cc_mdss_dp_pixel_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_dp_pixel_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"disp_cc_mdss_dp_pixel_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_dp_pixel_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -598,8 +600,8 @@ static struct clk_branch disp_cc_mdss_esc0_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_esc0_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"disp_cc_mdss_esc0_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_esc0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -616,8 +618,8 @@ static struct clk_branch disp_cc_mdss_esc1_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_esc1_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"disp_cc_mdss_esc1_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_esc1_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -634,8 +636,8 @@ static struct clk_branch disp_cc_mdss_mdp_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_mdp_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"disp_cc_mdss_mdp_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_mdp_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -652,8 +654,8 @@ static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_mdp_lut_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"disp_cc_mdss_mdp_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_mdp_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_branch2_ops,
|
||||
@ -670,8 +672,8 @@ static struct clk_branch disp_cc_mdss_pclk0_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_pclk0_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"disp_cc_mdss_pclk0_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_pclk0_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -689,8 +691,8 @@ static struct clk_branch disp_cc_mdss_pclk1_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_pclk1_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"disp_cc_mdss_pclk1_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_pclk1_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -707,8 +709,8 @@ static struct clk_branch disp_cc_mdss_rot_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_rot_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"disp_cc_mdss_rot_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_rot_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -738,8 +740,8 @@ static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_rscc_vsync_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"disp_cc_mdss_vsync_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_vsync_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
@ -756,8 +758,8 @@ static struct clk_branch disp_cc_mdss_vsync_clk = {
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "disp_cc_mdss_vsync_clk",
|
||||
.parent_names = (const char *[]){
|
||||
"disp_cc_mdss_vsync_clk_src",
|
||||
.parent_hws = (const struct clk_hw*[]){
|
||||
&disp_cc_mdss_vsync_clk_src.clkr.hw,
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user