mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
synced 2025-01-18 06:15:12 +00:00
spi: Fixes for v5.14
A collection of driver specific fixes, there was a bit of a kerfuffle with some last minute review on hte spi-cadence-quadspi division by zero change but otherwise nothing terribly remarkable here - important fixes if you have the hardware but nothing with too wide an impact. -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEreZoqmdXGLWf4p/qJNaLcl1Uh9AFAmD4WjwACgkQJNaLcl1U h9CofQf/exao6MVAh2aMFv4A0UjQ4jI/wOWzhDY84ooxtTpcSlmAcPNR/yXt7yvc 2s7OcDOSRL8uO9agrnLINDzRrB/+Z8N7ra3sUwzzkNEe6YoOcLYW+GvFSYbyqqPQ w8Ij6xn05RINQ63WuwwNHNwxlNBcXAT/bkKUkuzAinQi91hehwVQrAgoaNmbDzvI B0NhSwVEYvlEsfvmVwOJN4VUDbFor31oE3hNvK685ATRvPEQssbQarloK4OsPajv hOKqDNY/UKggSEFSaeN8gExrylhqEsXk1r+p0S8kKfZnyoNkemPa9xK2QD5YjulE V9rDs90qjWoA1Rw90e61HvDbtDBgdQ== =74y9 -----END PGP SIGNATURE----- Merge tag 'spi-fix-v5.14-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi fixes from Mark Brown: "A collection of driver specific fixes, there was a bit of a kerfuffle with some last minute review on hte spi-cadence-quadspi division by zero change but otherwise nothing terribly remarkable here - important fixes if you have the hardware but nothing with too wide an impact" * tag 'spi-fix-v5.14-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: spi: spi-bcm2835: Fix deadlock spi: cadence: Correct initialisation of runtime PM again spi: cadence-quadspi: Disable Auto-HW polling spi: spi-cadence-quadspi: Fix division by zero warning spi: spi-cadence-quadspi: Revert "Fix division by zero warning" spi: spi-cadence-quadspi: Fix division by zero warning spi: mediatek: move devm_spi_register_master position spi: mediatek: fix fifo rx mode spi: atmel: Fix CS and initialization bug spi: stm32: fixes pm_runtime calls in probe/remove spi: imx: mx51-ecspi: Reinstate low-speed CONFIGREG delay spi: stm32h7: fix full duplex irq handler handling
This commit is contained in:
Linus Torvalds
commit
7b6ae471e5
@ -352,8 +352,6 @@ static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
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}
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mr = spi_readl(as, MR);
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if (spi->cs_gpiod)
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gpiod_set_value(spi->cs_gpiod, 1);
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} else {
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u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
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int i;
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@ -369,8 +367,6 @@ static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
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mr = spi_readl(as, MR);
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mr = SPI_BFINS(PCS, ~(1 << chip_select), mr);
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if (spi->cs_gpiod)
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gpiod_set_value(spi->cs_gpiod, 1);
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spi_writel(as, MR, mr);
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}
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@ -400,8 +396,6 @@ static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
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if (!spi->cs_gpiod)
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spi_writel(as, CR, SPI_BIT(LASTXFER));
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else
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gpiod_set_value(spi->cs_gpiod, 0);
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}
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static void atmel_spi_lock(struct atmel_spi *as) __acquires(&as->lock)
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@ -1483,7 +1477,8 @@ static int atmel_spi_probe(struct platform_device *pdev)
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master->bus_num = pdev->id;
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master->num_chipselect = 4;
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master->setup = atmel_spi_setup;
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master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX);
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master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX |
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SPI_MASTER_GPIO_SS);
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master->transfer_one = atmel_spi_one_transfer;
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master->set_cs = atmel_spi_set_cs;
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master->cleanup = atmel_spi_cleanup;
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@ -83,6 +83,7 @@ MODULE_PARM_DESC(polling_limit_us,
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* struct bcm2835_spi - BCM2835 SPI controller
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* @regs: base address of register map
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* @clk: core clock, divided to calculate serial clock
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* @clk_hz: core clock cached speed
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* @irq: interrupt, signals TX FIFO empty or RX FIFO ¾ full
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* @tfr: SPI transfer currently processed
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* @ctlr: SPI controller reverse lookup
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@ -116,6 +117,7 @@ MODULE_PARM_DESC(polling_limit_us,
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struct bcm2835_spi {
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void __iomem *regs;
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struct clk *clk;
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unsigned long clk_hz;
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int irq;
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struct spi_transfer *tfr;
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struct spi_controller *ctlr;
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@ -1045,19 +1047,18 @@ static int bcm2835_spi_transfer_one(struct spi_controller *ctlr,
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{
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struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
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struct bcm2835_spidev *slv = spi_get_ctldata(spi);
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unsigned long spi_hz, clk_hz, cdiv;
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unsigned long spi_hz, cdiv;
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unsigned long hz_per_byte, byte_limit;
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u32 cs = slv->prepare_cs;
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/* set clock */
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spi_hz = tfr->speed_hz;
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clk_hz = clk_get_rate(bs->clk);
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if (spi_hz >= clk_hz / 2) {
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if (spi_hz >= bs->clk_hz / 2) {
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cdiv = 2; /* clk_hz/2 is the fastest we can go */
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} else if (spi_hz) {
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/* CDIV must be a multiple of two */
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cdiv = DIV_ROUND_UP(clk_hz, spi_hz);
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cdiv = DIV_ROUND_UP(bs->clk_hz, spi_hz);
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cdiv += (cdiv % 2);
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if (cdiv >= 65536)
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@ -1065,7 +1066,7 @@ static int bcm2835_spi_transfer_one(struct spi_controller *ctlr,
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} else {
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cdiv = 0; /* 0 is the slowest we can go */
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}
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tfr->effective_speed_hz = cdiv ? (clk_hz / cdiv) : (clk_hz / 65536);
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tfr->effective_speed_hz = cdiv ? (bs->clk_hz / cdiv) : (bs->clk_hz / 65536);
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bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv);
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/* handle all the 3-wire mode */
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@ -1354,6 +1355,7 @@ static int bcm2835_spi_probe(struct platform_device *pdev)
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return bs->irq ? bs->irq : -ENODEV;
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clk_prepare_enable(bs->clk);
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bs->clk_hz = clk_get_rate(bs->clk);
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err = bcm2835_dma_init(ctlr, &pdev->dev, bs);
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if (err)
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@ -309,6 +309,9 @@ static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op, bool dtr)
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{
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unsigned int dummy_clk;
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if (!op->dummy.nbytes)
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return 0;
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dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth);
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if (dtr)
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dummy_clk /= 2;
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@ -797,19 +800,20 @@ static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata,
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reg = cqspi_calc_rdreg(f_pdata);
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writel(reg, reg_base + CQSPI_REG_RD_INSTR);
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if (f_pdata->dtr) {
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/*
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* Some flashes like the cypress Semper flash expect a 4-byte
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* dummy address with the Read SR command in DTR mode, but this
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* controller does not support sending address with the Read SR
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* command. So, disable write completion polling on the
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* controller's side. spi-nor will take care of polling the
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* status register.
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*/
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reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
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reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL;
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writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
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}
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/*
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* SPI NAND flashes require the address of the status register to be
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* passed in the Read SR command. Also, some SPI NOR flashes like the
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* cypress Semper flash expect a 4-byte dummy address in the Read SR
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* command in DTR mode.
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*
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* But this controller does not support address phase in the Read SR
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* command when doing auto-HW polling. So, disable write completion
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* polling on the controller's side. spinand and spi-nor will take
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* care of polling the status register.
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*/
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reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
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reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL;
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writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
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reg = readl(reg_base + CQSPI_REG_SIZE);
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reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
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@ -517,6 +517,12 @@ static int cdns_spi_probe(struct platform_device *pdev)
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goto clk_dis_apb;
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}
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pm_runtime_use_autosuspend(&pdev->dev);
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pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
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pm_runtime_get_noresume(&pdev->dev);
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pm_runtime_set_active(&pdev->dev);
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pm_runtime_enable(&pdev->dev);
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ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
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if (ret < 0)
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master->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS;
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@ -531,11 +537,6 @@ static int cdns_spi_probe(struct platform_device *pdev)
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/* SPI controller initializations */
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cdns_spi_init_hw(xspi);
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pm_runtime_set_active(&pdev->dev);
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pm_runtime_enable(&pdev->dev);
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pm_runtime_use_autosuspend(&pdev->dev);
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pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
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irq = platform_get_irq(pdev, 0);
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if (irq <= 0) {
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ret = -ENXIO;
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@ -566,6 +567,9 @@ static int cdns_spi_probe(struct platform_device *pdev)
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master->bits_per_word_mask = SPI_BPW_MASK(8);
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pm_runtime_mark_last_busy(&pdev->dev);
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pm_runtime_put_autosuspend(&pdev->dev);
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ret = spi_register_master(master);
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if (ret) {
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dev_err(&pdev->dev, "spi_register_master failed\n");
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@ -506,7 +506,7 @@ static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx,
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{
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struct spi_device *spi = msg->spi;
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u32 ctrl = MX51_ECSPI_CTRL_ENABLE;
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u32 testreg;
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u32 testreg, delay;
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u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
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/* set Master or Slave mode */
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@ -567,6 +567,23 @@ static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx,
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writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
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/*
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* Wait until the changes in the configuration register CONFIGREG
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* propagate into the hardware. It takes exactly one tick of the
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* SCLK clock, but we will wait two SCLK clock just to be sure. The
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* effect of the delay it takes for the hardware to apply changes
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* is noticable if the SCLK clock run very slow. In such a case, if
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* the polarity of SCLK should be inverted, the GPIO ChipSelect might
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* be asserted before the SCLK polarity changes, which would disrupt
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* the SPI communication as the device on the other end would consider
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* the change of SCLK polarity as a clock tick already.
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*/
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delay = (2 * 1000000) / spi_imx->spi_bus_clk;
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if (likely(delay < 10)) /* SCLK is faster than 100 kHz */
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udelay(delay);
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else /* SCLK is _very_ slow */
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usleep_range(delay, delay + 10);
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return 0;
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}
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@ -574,7 +591,7 @@ static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
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struct spi_device *spi)
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{
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u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
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u32 clk, delay;
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u32 clk;
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/* Clear BL field and set the right value */
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ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
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@ -596,23 +613,6 @@ static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
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writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
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/*
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* Wait until the changes in the configuration register CONFIGREG
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* propagate into the hardware. It takes exactly one tick of the
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* SCLK clock, but we will wait two SCLK clock just to be sure. The
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* effect of the delay it takes for the hardware to apply changes
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* is noticable if the SCLK clock run very slow. In such a case, if
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* the polarity of SCLK should be inverted, the GPIO ChipSelect might
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* be asserted before the SCLK polarity changes, which would disrupt
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* the SPI communication as the device on the other end would consider
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* the change of SCLK polarity as a clock tick already.
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*/
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delay = (2 * 1000000) / clk;
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if (likely(delay < 10)) /* SCLK is faster than 100 kHz */
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udelay(delay);
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else /* SCLK is _very_ slow */
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usleep_range(delay, delay + 10);
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return 0;
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}
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@ -427,13 +427,23 @@ static int mtk_spi_fifo_transfer(struct spi_master *master,
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mtk_spi_setup_packet(master);
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cnt = xfer->len / 4;
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iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt);
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if (xfer->tx_buf)
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iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt);
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if (xfer->rx_buf)
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ioread32_rep(mdata->base + SPI_RX_DATA_REG, xfer->rx_buf, cnt);
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remainder = xfer->len % 4;
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if (remainder > 0) {
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reg_val = 0;
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memcpy(®_val, xfer->tx_buf + (cnt * 4), remainder);
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writel(reg_val, mdata->base + SPI_TX_DATA_REG);
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if (xfer->tx_buf) {
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memcpy(®_val, xfer->tx_buf + (cnt * 4), remainder);
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writel(reg_val, mdata->base + SPI_TX_DATA_REG);
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}
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if (xfer->rx_buf) {
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reg_val = readl(mdata->base + SPI_RX_DATA_REG);
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memcpy(xfer->rx_buf + (cnt * 4), ®_val, remainder);
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}
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}
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mtk_spi_enable_transfer(master);
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@ -793,12 +803,6 @@ static int mtk_spi_probe(struct platform_device *pdev)
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pm_runtime_enable(&pdev->dev);
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ret = devm_spi_register_master(&pdev->dev, master);
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if (ret) {
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dev_err(&pdev->dev, "failed to register master (%d)\n", ret);
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goto err_disable_runtime_pm;
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}
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if (mdata->dev_comp->need_pad_sel) {
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if (mdata->pad_num != master->num_chipselect) {
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dev_err(&pdev->dev,
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@ -838,6 +842,12 @@ static int mtk_spi_probe(struct platform_device *pdev)
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dev_notice(&pdev->dev, "SPI dma_set_mask(%d) failed, ret:%d\n",
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addr_bits, ret);
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ret = devm_spi_register_master(&pdev->dev, master);
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if (ret) {
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dev_err(&pdev->dev, "failed to register master (%d)\n", ret);
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goto err_disable_runtime_pm;
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}
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return 0;
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err_disable_runtime_pm:
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@ -884,15 +884,18 @@ static irqreturn_t stm32h7_spi_irq_thread(int irq, void *dev_id)
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ier = readl_relaxed(spi->base + STM32H7_SPI_IER);
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mask = ier;
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/* EOTIE is triggered on EOT, SUSP and TXC events. */
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/*
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* EOTIE enables irq from EOT, SUSP and TXC events. We need to set
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* SUSP to acknowledge it later. TXC is automatically cleared
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*/
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mask |= STM32H7_SPI_SR_SUSP;
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/*
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* When TXTF is set, DXPIE and TXPIE are cleared. So in case of
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* Full-Duplex, need to poll RXP event to know if there are remaining
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* data, before disabling SPI.
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* DXPIE is set in Full-Duplex, one IT will be raised if TXP and RXP
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* are set. So in case of Full-Duplex, need to poll TXP and RXP event.
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*/
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if (spi->rx_buf && !spi->cur_usedma)
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mask |= STM32H7_SPI_SR_RXP;
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if ((spi->cur_comm == SPI_FULL_DUPLEX) && !spi->cur_usedma)
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mask |= STM32H7_SPI_SR_TXP | STM32H7_SPI_SR_RXP;
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if (!(sr & mask)) {
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dev_warn(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
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@ -1925,6 +1928,7 @@ static int stm32_spi_probe(struct platform_device *pdev)
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master->can_dma = stm32_spi_can_dma;
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pm_runtime_set_active(&pdev->dev);
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pm_runtime_get_noresume(&pdev->dev);
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pm_runtime_enable(&pdev->dev);
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ret = spi_register_master(master);
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@ -1940,6 +1944,8 @@ static int stm32_spi_probe(struct platform_device *pdev)
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err_pm_disable:
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pm_runtime_disable(&pdev->dev);
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pm_runtime_put_noidle(&pdev->dev);
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pm_runtime_set_suspended(&pdev->dev);
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err_dma_release:
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if (spi->dma_tx)
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dma_release_channel(spi->dma_tx);
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@ -1956,9 +1962,14 @@ static int stm32_spi_remove(struct platform_device *pdev)
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struct spi_master *master = platform_get_drvdata(pdev);
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struct stm32_spi *spi = spi_master_get_devdata(master);
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pm_runtime_get_sync(&pdev->dev);
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spi_unregister_master(master);
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spi->cfg->disable(spi);
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pm_runtime_disable(&pdev->dev);
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pm_runtime_put_noidle(&pdev->dev);
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pm_runtime_set_suspended(&pdev->dev);
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if (master->dma_tx)
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dma_release_channel(master->dma_tx);
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if (master->dma_rx)
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@ -1966,7 +1977,6 @@ static int stm32_spi_remove(struct platform_device *pdev)
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clk_disable_unprepare(spi->clk);
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pm_runtime_disable(&pdev->dev);
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pinctrl_pm_select_sleep_state(&pdev->dev);
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