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net: pcs: add Renesas MII converter driver
Add a PCS driver for the MII converter that is present on the Renesas RZ/N1 SoC. This MII converter is reponsible for converting MII to RMII/RGMII or act as a MII pass-trough. Exposing it as a PCS allows to reuse it in both the switch driver and the stmmac driver. Currently, this driver only allows the PCS to be used by the dual Cortex-A7 subsystem since the register locking system is not used. Signed-off-by: Clément Léger <clement.leger@bootlin.com> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Clément Léger
David S. Miller
parent
c823c2bf91
commit
7dc54d3b8d
@ -18,4 +18,12 @@ config PCS_LYNX
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This module provides helpers to phylink for managing the Lynx PCS
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which is part of the Layerscape and QorIQ Ethernet SERDES.
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config PCS_RZN1_MIIC
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tristate "Renesas RZ/N1 MII converter"
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depends on OF && (ARCH_RZN1 || COMPILE_TEST)
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help
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This module provides a driver for the MII converter that is available
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on RZ/N1 SoCs. This PCS converts MII to RMII/RGMII or can be set in
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pass-through mode for MII.
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endmenu
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@ -5,3 +5,4 @@ pcs_xpcs-$(CONFIG_PCS_XPCS) := pcs-xpcs.o pcs-xpcs-nxp.o
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obj-$(CONFIG_PCS_XPCS) += pcs_xpcs.o
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obj-$(CONFIG_PCS_LYNX) += pcs-lynx.o
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obj-$(CONFIG_PCS_RZN1_MIIC) += pcs-rzn1-miic.o
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520
drivers/net/pcs/pcs-rzn1-miic.c
Normal file
520
drivers/net/pcs/pcs-rzn1-miic.c
Normal file
@ -0,0 +1,520 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2022 Schneider Electric
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*
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* Clément Léger <clement.leger@bootlin.com>
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*/
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/mdio.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/pcs-rzn1-miic.h>
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#include <linux/phylink.h>
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#include <linux/pm_runtime.h>
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#include <dt-bindings/net/pcs-rzn1-miic.h>
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#define MIIC_PRCMD 0x0
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#define MIIC_ESID_CODE 0x4
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#define MIIC_MODCTRL 0x20
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#define MIIC_MODCTRL_SW_MODE GENMASK(4, 0)
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#define MIIC_CONVCTRL(port) (0x100 + (port) * 4)
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#define MIIC_CONVCTRL_CONV_SPEED GENMASK(1, 0)
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#define CONV_MODE_10MBPS 0
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#define CONV_MODE_100MBPS 1
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#define CONV_MODE_1000MBPS 2
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#define MIIC_CONVCTRL_CONV_MODE GENMASK(3, 2)
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#define CONV_MODE_MII 0
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#define CONV_MODE_RMII 1
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#define CONV_MODE_RGMII 2
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#define MIIC_CONVCTRL_FULLD BIT(8)
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#define MIIC_CONVCTRL_RGMII_LINK BIT(12)
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#define MIIC_CONVCTRL_RGMII_DUPLEX BIT(13)
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#define MIIC_CONVCTRL_RGMII_SPEED GENMASK(15, 14)
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#define MIIC_CONVRST 0x114
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#define MIIC_CONVRST_PHYIF_RST(port) BIT(port)
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#define MIIC_CONVRST_PHYIF_RST_MASK GENMASK(4, 0)
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#define MIIC_SWCTRL 0x304
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#define MIIC_SWDUPC 0x308
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#define MIIC_MAX_NR_PORTS 5
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#define MIIC_MODCTRL_CONF_CONV_NUM 6
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#define MIIC_MODCTRL_CONF_NONE -1
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/**
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* struct modctrl_match - Matching table entry for convctrl configuration
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* See section 8.2.1 of manual.
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* @mode_cfg: Configuration value for convctrl
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* @conv: Configuration of ethernet port muxes. First index is SWITCH_PORTIN,
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* then index 1 - 5 are CONV1 - CONV5.
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*/
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struct modctrl_match {
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u32 mode_cfg;
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u8 conv[MIIC_MODCTRL_CONF_CONV_NUM];
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};
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static struct modctrl_match modctrl_match_table[] = {
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{0x0, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
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MIIC_SWITCH_PORTC, MIIC_SERCOS_PORTB, MIIC_SERCOS_PORTA}},
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{0x1, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
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MIIC_SWITCH_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}},
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{0x2, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
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MIIC_ETHERCAT_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}},
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{0x3, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
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MIIC_SWITCH_PORTC, MIIC_SWITCH_PORTB, MIIC_SWITCH_PORTA}},
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{0x8, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
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MIIC_SWITCH_PORTC, MIIC_SERCOS_PORTB, MIIC_SERCOS_PORTA}},
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{0x9, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
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MIIC_SWITCH_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}},
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{0xA, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
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MIIC_ETHERCAT_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}},
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{0xB, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
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MIIC_SWITCH_PORTC, MIIC_SWITCH_PORTB, MIIC_SWITCH_PORTA}},
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{0x10, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
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MIIC_SWITCH_PORTC, MIIC_SERCOS_PORTB, MIIC_SERCOS_PORTA}},
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{0x11, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
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MIIC_SWITCH_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}},
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{0x12, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
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MIIC_ETHERCAT_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}},
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{0x13, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
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MIIC_SWITCH_PORTC, MIIC_SWITCH_PORTB, MIIC_SWITCH_PORTA}}
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};
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static const char * const conf_to_string[] = {
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[MIIC_GMAC1_PORT] = "GMAC1_PORT",
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[MIIC_GMAC2_PORT] = "GMAC2_PORT",
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[MIIC_RTOS_PORT] = "RTOS_PORT",
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[MIIC_SERCOS_PORTA] = "SERCOS_PORTA",
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[MIIC_SERCOS_PORTB] = "SERCOS_PORTB",
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[MIIC_ETHERCAT_PORTA] = "ETHERCAT_PORTA",
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[MIIC_ETHERCAT_PORTB] = "ETHERCAT_PORTB",
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[MIIC_ETHERCAT_PORTC] = "ETHERCAT_PORTC",
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[MIIC_SWITCH_PORTA] = "SWITCH_PORTA",
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[MIIC_SWITCH_PORTB] = "SWITCH_PORTB",
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[MIIC_SWITCH_PORTC] = "SWITCH_PORTC",
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[MIIC_SWITCH_PORTD] = "SWITCH_PORTD",
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[MIIC_HSR_PORTA] = "HSR_PORTA",
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[MIIC_HSR_PORTB] = "HSR_PORTB",
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};
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static const char *index_to_string[MIIC_MODCTRL_CONF_CONV_NUM] = {
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"SWITCH_PORTIN",
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"CONV1",
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"CONV2",
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"CONV3",
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"CONV4",
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"CONV5",
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};
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/**
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* struct miic - MII converter structure
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* @base: base address of the MII converter
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* @dev: Device associated to the MII converter
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* @clks: Clocks used for this device
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* @nclk: Number of clocks
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* @lock: Lock used for read-modify-write access
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*/
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struct miic {
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void __iomem *base;
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struct device *dev;
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struct clk_bulk_data *clks;
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int nclk;
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spinlock_t lock;
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};
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/**
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* struct miic_port - Per port MII converter struct
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* @miic: backiling to MII converter structure
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* @pcs: PCS structure associated to the port
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* @port: port number
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*/
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struct miic_port {
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struct miic *miic;
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struct phylink_pcs pcs;
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int port;
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};
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static struct miic_port *phylink_pcs_to_miic_port(struct phylink_pcs *pcs)
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{
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return container_of(pcs, struct miic_port, pcs);
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}
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static void miic_reg_writel(struct miic *miic, int offset, u32 value)
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{
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writel(value, miic->base + offset);
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}
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static u32 miic_reg_readl(struct miic *miic, int offset)
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{
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return readl(miic->base + offset);
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}
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static void miic_reg_rmw(struct miic *miic, int offset, u32 mask, u32 val)
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{
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u32 reg;
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spin_lock(&miic->lock);
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reg = miic_reg_readl(miic, offset);
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reg &= ~mask;
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reg |= val;
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miic_reg_writel(miic, offset, reg);
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spin_unlock(&miic->lock);
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}
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static void miic_converter_enable(struct miic *miic, int port, int enable)
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{
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u32 val = 0;
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if (enable)
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val = MIIC_CONVRST_PHYIF_RST(port);
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miic_reg_rmw(miic, MIIC_CONVRST, MIIC_CONVRST_PHYIF_RST(port), val);
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}
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static int miic_config(struct phylink_pcs *pcs, unsigned int mode,
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phy_interface_t interface,
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const unsigned long *advertising, bool permit)
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{
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struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs);
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struct miic *miic = miic_port->miic;
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int port = miic_port->port;
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u32 speed, conv_mode, val;
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switch (interface) {
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case PHY_INTERFACE_MODE_RMII:
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conv_mode = CONV_MODE_RMII;
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speed = CONV_MODE_100MBPS;
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break;
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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case PHY_INTERFACE_MODE_RGMII_RXID:
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conv_mode = CONV_MODE_RGMII;
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speed = CONV_MODE_1000MBPS;
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break;
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case PHY_INTERFACE_MODE_MII:
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conv_mode = CONV_MODE_MII;
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/* When in MII mode, speed should be set to 0 (which is actually
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* CONV_MODE_10MBPS)
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*/
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speed = CONV_MODE_10MBPS;
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break;
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default:
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return -EOPNOTSUPP;
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}
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val = FIELD_PREP(MIIC_CONVCTRL_CONV_MODE, conv_mode) |
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FIELD_PREP(MIIC_CONVCTRL_CONV_SPEED, speed);
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miic_reg_rmw(miic, MIIC_CONVCTRL(port),
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MIIC_CONVCTRL_CONV_MODE | MIIC_CONVCTRL_CONV_SPEED, val);
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miic_converter_enable(miic_port->miic, miic_port->port, 1);
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return 0;
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}
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static void miic_link_up(struct phylink_pcs *pcs, unsigned int mode,
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phy_interface_t interface, int speed, int duplex)
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{
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struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs);
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struct miic *miic = miic_port->miic;
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u32 conv_speed = 0, val = 0;
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int port = miic_port->port;
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if (duplex == DUPLEX_FULL)
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val |= MIIC_CONVCTRL_FULLD;
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/* No speed in MII through-mode */
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if (interface != PHY_INTERFACE_MODE_MII) {
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switch (speed) {
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case SPEED_1000:
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conv_speed = CONV_MODE_1000MBPS;
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break;
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case SPEED_100:
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conv_speed = CONV_MODE_100MBPS;
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break;
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case SPEED_10:
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conv_speed = CONV_MODE_10MBPS;
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break;
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default:
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return;
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}
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}
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val |= FIELD_PREP(MIIC_CONVCTRL_CONV_SPEED, conv_speed);
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miic_reg_rmw(miic, MIIC_CONVCTRL(port),
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(MIIC_CONVCTRL_CONV_SPEED | MIIC_CONVCTRL_FULLD), val);
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}
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static int miic_validate(struct phylink_pcs *pcs, unsigned long *supported,
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const struct phylink_link_state *state)
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{
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if (phy_interface_mode_is_rgmii(state->interface) ||
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state->interface == PHY_INTERFACE_MODE_RMII ||
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state->interface == PHY_INTERFACE_MODE_MII)
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return 1;
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return -EINVAL;
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}
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static const struct phylink_pcs_ops miic_phylink_ops = {
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.pcs_validate = miic_validate,
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.pcs_config = miic_config,
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.pcs_link_up = miic_link_up,
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};
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struct phylink_pcs *miic_create(struct device *dev, struct device_node *np)
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{
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struct platform_device *pdev;
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struct miic_port *miic_port;
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struct device_node *pcs_np;
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struct miic *miic;
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u32 port;
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if (!of_device_is_available(np))
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return ERR_PTR(-ENODEV);
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if (of_property_read_u32(np, "reg", &port))
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return ERR_PTR(-EINVAL);
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if (port > MIIC_MAX_NR_PORTS || port < 1)
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return ERR_PTR(-EINVAL);
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/* The PCS pdev is attached to the parent node */
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pcs_np = of_get_parent(np);
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if (!pcs_np)
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return ERR_PTR(-ENODEV);
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if (!of_device_is_available(pcs_np)) {
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of_node_put(pcs_np);
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return ERR_PTR(-ENODEV);
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}
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pdev = of_find_device_by_node(pcs_np);
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of_node_put(pcs_np);
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if (!pdev || !platform_get_drvdata(pdev))
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return ERR_PTR(-EPROBE_DEFER);
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miic_port = kzalloc(sizeof(*miic_port), GFP_KERNEL);
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if (!miic_port)
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return ERR_PTR(-ENOMEM);
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miic = platform_get_drvdata(pdev);
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device_link_add(dev, miic->dev, DL_FLAG_AUTOREMOVE_CONSUMER);
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miic_port->miic = miic;
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miic_port->port = port - 1;
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miic_port->pcs.ops = &miic_phylink_ops;
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return &miic_port->pcs;
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}
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EXPORT_SYMBOL(miic_create);
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void miic_destroy(struct phylink_pcs *pcs)
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{
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struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs);
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miic_converter_enable(miic_port->miic, miic_port->port, 0);
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kfree(miic_port);
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}
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EXPORT_SYMBOL(miic_destroy);
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static int miic_init_hw(struct miic *miic, u32 cfg_mode)
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{
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int port;
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/* Unlock write access to accessory registers (cf datasheet). If this
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* is going to be used in conjunction with the Cortex-M3, this sequence
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* will have to be moved in register write
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*/
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miic_reg_writel(miic, MIIC_PRCMD, 0x00A5);
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miic_reg_writel(miic, MIIC_PRCMD, 0x0001);
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miic_reg_writel(miic, MIIC_PRCMD, 0xFFFE);
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miic_reg_writel(miic, MIIC_PRCMD, 0x0001);
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miic_reg_writel(miic, MIIC_MODCTRL,
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FIELD_PREP(MIIC_MODCTRL_SW_MODE, cfg_mode));
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for (port = 0; port < MIIC_MAX_NR_PORTS; port++) {
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miic_converter_enable(miic, port, 0);
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/* Disable speed/duplex control from these registers, datasheet
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* says switch registers should be used to setup switch port
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* speed and duplex.
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*/
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miic_reg_writel(miic, MIIC_SWCTRL, 0x0);
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miic_reg_writel(miic, MIIC_SWDUPC, 0x0);
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}
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return 0;
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}
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static bool miic_modctrl_match(s8 table_val[MIIC_MODCTRL_CONF_CONV_NUM],
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s8 dt_val[MIIC_MODCTRL_CONF_CONV_NUM])
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{
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int i;
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for (i = 0; i < MIIC_MODCTRL_CONF_CONV_NUM; i++) {
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if (dt_val[i] == MIIC_MODCTRL_CONF_NONE)
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continue;
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if (dt_val[i] != table_val[i])
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return false;
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}
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return true;
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}
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static void miic_dump_conf(struct device *dev,
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s8 conf[MIIC_MODCTRL_CONF_CONV_NUM])
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{
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const char *conf_name;
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int i;
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for (i = 0; i < MIIC_MODCTRL_CONF_CONV_NUM; i++) {
|
||||
if (conf[i] != MIIC_MODCTRL_CONF_NONE)
|
||||
conf_name = conf_to_string[conf[i]];
|
||||
else
|
||||
conf_name = "NONE";
|
||||
|
||||
dev_err(dev, "%s: %s\n", index_to_string[i], conf_name);
|
||||
}
|
||||
}
|
||||
|
||||
static int miic_match_dt_conf(struct device *dev,
|
||||
s8 dt_val[MIIC_MODCTRL_CONF_CONV_NUM],
|
||||
u32 *mode_cfg)
|
||||
{
|
||||
struct modctrl_match *table_entry;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(modctrl_match_table); i++) {
|
||||
table_entry = &modctrl_match_table[i];
|
||||
|
||||
if (miic_modctrl_match(table_entry->conv, dt_val)) {
|
||||
*mode_cfg = table_entry->mode_cfg;
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
dev_err(dev, "Failed to apply requested configuration\n");
|
||||
miic_dump_conf(dev, dt_val);
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int miic_parse_dt(struct device *dev, u32 *mode_cfg)
|
||||
{
|
||||
s8 dt_val[MIIC_MODCTRL_CONF_CONV_NUM];
|
||||
struct device_node *np = dev->of_node;
|
||||
struct device_node *conv;
|
||||
u32 conf;
|
||||
int port;
|
||||
|
||||
memset(dt_val, MIIC_MODCTRL_CONF_NONE, sizeof(dt_val));
|
||||
|
||||
if (of_property_read_u32(np, "renesas,miic-switch-portin", &conf) == 0)
|
||||
dt_val[0] = conf;
|
||||
|
||||
for_each_child_of_node(np, conv) {
|
||||
if (of_property_read_u32(conv, "reg", &port))
|
||||
continue;
|
||||
|
||||
if (!of_device_is_available(conv))
|
||||
continue;
|
||||
|
||||
if (of_property_read_u32(conv, "renesas,miic-input", &conf) == 0)
|
||||
dt_val[port] = conf;
|
||||
}
|
||||
|
||||
return miic_match_dt_conf(dev, dt_val, mode_cfg);
|
||||
}
|
||||
|
||||
static int miic_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct miic *miic;
|
||||
u32 mode_cfg;
|
||||
int ret;
|
||||
|
||||
ret = miic_parse_dt(dev, &mode_cfg);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
miic = devm_kzalloc(dev, sizeof(*miic), GFP_KERNEL);
|
||||
if (!miic)
|
||||
return -ENOMEM;
|
||||
|
||||
spin_lock_init(&miic->lock);
|
||||
miic->dev = dev;
|
||||
miic->base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (!miic->base)
|
||||
return -EINVAL;
|
||||
|
||||
ret = devm_pm_runtime_enable(dev);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ret = pm_runtime_resume_and_get(dev);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ret = miic_init_hw(miic, mode_cfg);
|
||||
if (ret)
|
||||
goto disable_runtime_pm;
|
||||
|
||||
/* miic_create() relies on that fact that data are attached to the
|
||||
* platform device to determine if the driver is ready so this needs to
|
||||
* be the last thing to be done after everything is initialized
|
||||
* properly.
|
||||
*/
|
||||
platform_set_drvdata(pdev, miic);
|
||||
|
||||
return 0;
|
||||
|
||||
disable_runtime_pm:
|
||||
pm_runtime_put(dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int miic_remove(struct platform_device *pdev)
|
||||
{
|
||||
pm_runtime_put(&pdev->dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id miic_of_mtable[] = {
|
||||
{ .compatible = "renesas,rzn1-miic" },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, miic_of_mtable);
|
||||
|
||||
static struct platform_driver miic_driver = {
|
||||
.driver = {
|
||||
.name = "rzn1_miic",
|
||||
.suppress_bind_attrs = true,
|
||||
.of_match_table = miic_of_mtable,
|
||||
},
|
||||
.probe = miic_probe,
|
||||
.remove = miic_remove,
|
||||
};
|
||||
module_platform_driver(miic_driver);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_DESCRIPTION("Renesas MII converter PCS driver");
|
||||
MODULE_AUTHOR("Clément Léger <clement.leger@bootlin.com>");
|
||||
18
include/linux/pcs-rzn1-miic.h
Normal file
18
include/linux/pcs-rzn1-miic.h
Normal file
@ -0,0 +1,18 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2022 Schneider Electric
|
||||
*
|
||||
* Clément Léger <clement.leger@bootlin.com>
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_PCS_MIIC_H
|
||||
#define __LINUX_PCS_MIIC_H
|
||||
|
||||
struct phylink;
|
||||
struct device_node;
|
||||
|
||||
struct phylink_pcs *miic_create(struct device *dev, struct device_node *np);
|
||||
|
||||
void miic_destroy(struct phylink_pcs *pcs);
|
||||
|
||||
#endif /* __LINUX_PCS_MIIC_H */
|
||||
Loading…
Reference in New Issue
Block a user