mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
synced 2025-01-18 22:34:48 +00:00
spi: davinci: let DMA operation be specified on per-device basis
Let DMA operation be specified on a per-device basis instead of selecting it once during probe. A side effect of this is the need to combine the PIO and DMA buffer txrx_bufs routine. This is good since they anyway share some common functionality. Signed-off-by: Brian Niebuhr <bniebuhr@efjohnson.com> Tested-By: Michael Williamson <michael.williamson@criticallink.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
This commit is contained in:
Brian Niebuhr
Sekhar Nori
parent
6dbd29b27b
commit
87467bd905
@ -41,6 +41,7 @@ struct davinci_spi_config {
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u8 parity_enable;
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#define SPI_IO_TYPE_INTR 0
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#define SPI_IO_TYPE_POLL 1
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#define SPI_IO_TYPE_DMA 2
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u8 io_type;
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u8 timer_disable;
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u8 c2tdelay;
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@ -500,6 +500,25 @@ out:
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return errors;
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}
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static void davinci_spi_dma_callback(unsigned lch, u16 status, void *data)
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{
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struct davinci_spi *davinci_spi = data;
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struct davinci_spi_dma *davinci_spi_dma = &davinci_spi->dma_channels;
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edma_stop(lch);
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if (status == DMA_COMPLETE) {
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if (lch == davinci_spi_dma->dma_rx_channel)
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davinci_spi->rcount = 0;
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if (lch == davinci_spi_dma->dma_tx_channel)
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davinci_spi->wcount = 0;
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}
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if ((!davinci_spi->wcount && !davinci_spi->rcount) ||
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(status != DMA_COMPLETE))
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complete(&davinci_spi->done);
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}
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/**
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* davinci_spi_bufs - functions which will handle transfer data
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* @spi: spi device on which data transfer to be done
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@ -509,25 +528,30 @@ out:
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* of SPI controller and then wait until the completion will be marked
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* by the IRQ Handler.
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*/
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static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t)
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static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
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{
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struct davinci_spi *davinci_spi;
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int ret;
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int data_type, ret;
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u32 tx_data, data1_reg_val;
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u32 errors = 0;
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struct davinci_spi_config *spicfg;
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struct davinci_spi_platform_data *pdata;
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unsigned uninitialized_var(rx_buf_count);
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struct device *sdev;
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davinci_spi = spi_master_get_devdata(spi->master);
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pdata = davinci_spi->pdata;
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spicfg = (struct davinci_spi_config *)spi->controller_data;
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if (!spicfg)
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spicfg = &davinci_spi_default_cfg;
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sdev = davinci_spi->bitbang.master->dev.parent;
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/* convert len to words based on bits_per_word */
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data_type = davinci_spi->bytes_per_word[spi->chip_select];
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davinci_spi->tx = t->tx_buf;
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davinci_spi->rx = t->rx_buf;
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davinci_spi->wcount = t->len /
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davinci_spi->bytes_per_word[spi->chip_select];
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davinci_spi->wcount = t->len / data_type;
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davinci_spi->rcount = davinci_spi->wcount;
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data1_reg_val = ioread32(davinci_spi->base + SPIDAT1);
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@ -535,20 +559,117 @@ static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t)
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/* Enable SPI */
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set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
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if (spicfg->io_type == SPI_IO_TYPE_INTR) {
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INIT_COMPLETION(davinci_spi->done);
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if (spicfg->io_type == SPI_IO_TYPE_INTR)
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set_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKINT);
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INIT_COMPLETION(davinci_spi->done);
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if (spicfg->io_type != SPI_IO_TYPE_DMA) {
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/* start the transfer */
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davinci_spi->wcount--;
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tx_data = davinci_spi->get_tx(davinci_spi);
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data1_reg_val &= 0xFFFF0000;
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data1_reg_val |= tx_data & 0xFFFF;
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iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
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} else {
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struct davinci_spi_dma *davinci_spi_dma;
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unsigned long tx_reg, rx_reg;
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struct edmacc_param param;
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void *rx_buf;
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davinci_spi_dma = &davinci_spi->dma_channels;
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tx_reg = (unsigned long)davinci_spi->pbase + SPIDAT1;
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rx_reg = (unsigned long)davinci_spi->pbase + SPIBUF;
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/*
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* Transmit DMA setup
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*
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* If there is transmit data, map the transmit buffer, set it
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* as the source of data and set the source B index to data
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* size. If there is no transmit data, set the transmit register
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* as the source of data, and set the source B index to zero.
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*
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* The destination is always the transmit register itself. And
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* the destination never increments.
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*/
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if (t->tx_buf) {
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t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf,
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davinci_spi->wcount, DMA_TO_DEVICE);
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if (dma_mapping_error(&spi->dev, t->tx_dma)) {
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dev_dbg(sdev, "Unable to DMA map %d bytes"
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"TX buffer\n",
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davinci_spi->wcount);
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return -ENOMEM;
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}
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}
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param.opt = TCINTEN | EDMA_TCC(davinci_spi_dma->dma_tx_channel);
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param.src = t->tx_buf ? t->tx_dma : tx_reg;
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param.a_b_cnt = davinci_spi->wcount << 16 | data_type;
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param.dst = tx_reg;
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param.src_dst_bidx = t->tx_buf ? data_type : 0;
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param.link_bcntrld = 0xffff;
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param.src_dst_cidx = 0;
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param.ccnt = 1;
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edma_write_slot(davinci_spi_dma->dma_tx_channel, ¶m);
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edma_link(davinci_spi_dma->dma_tx_channel,
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davinci_spi_dma->dummy_param_slot);
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/*
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* Receive DMA setup
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*
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* If there is receive buffer, use it to receive data. If there
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* is none provided, use a temporary receive buffer. Set the
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* destination B index to 0 so effectively only one byte is used
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* in the temporary buffer (address does not increment).
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*
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* The source of receive data is the receive data register. The
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* source address never increments.
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*/
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if (t->rx_buf) {
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rx_buf = t->rx_buf;
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rx_buf_count = davinci_spi->rcount;
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} else {
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rx_buf = davinci_spi->rx_tmp_buf;
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rx_buf_count = sizeof(davinci_spi->rx_tmp_buf);
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}
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t->rx_dma = dma_map_single(&spi->dev, rx_buf, rx_buf_count,
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DMA_FROM_DEVICE);
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if (dma_mapping_error(&spi->dev, t->rx_dma)) {
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dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n",
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rx_buf_count);
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if (t->tx_buf)
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dma_unmap_single(NULL, t->tx_dma,
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davinci_spi->wcount,
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DMA_TO_DEVICE);
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return -ENOMEM;
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}
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param.opt = TCINTEN | EDMA_TCC(davinci_spi_dma->dma_rx_channel);
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param.src = rx_reg;
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param.a_b_cnt = davinci_spi->rcount << 16 | data_type;
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param.dst = t->rx_dma;
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param.src_dst_bidx = (t->rx_buf ? data_type : 0) << 16;
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param.link_bcntrld = 0xffff;
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param.src_dst_cidx = 0;
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param.ccnt = 1;
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edma_write_slot(davinci_spi_dma->dma_rx_channel, ¶m);
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if (pdata->cshold_bug)
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iowrite16(data1_reg_val >> 16,
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davinci_spi->base + SPIDAT1 + 2);
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edma_start(davinci_spi_dma->dma_rx_channel);
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edma_start(davinci_spi_dma->dma_tx_channel);
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set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN);
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}
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/* start the transfer */
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davinci_spi->wcount--;
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tx_data = davinci_spi->get_tx(davinci_spi);
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data1_reg_val &= 0xFFFF0000;
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data1_reg_val |= tx_data & 0xFFFF;
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iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
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/* Wait for the transfer to complete */
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if (spicfg->io_type == SPI_IO_TYPE_INTR) {
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if (spicfg->io_type != SPI_IO_TYPE_POLL) {
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wait_for_completion_interruptible(&(davinci_spi->done));
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} else {
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while (davinci_spi->rcount > 0 || davinci_spi->wcount > 0) {
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@ -560,6 +681,17 @@ static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t)
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}
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clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL);
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if (spicfg->io_type == SPI_IO_TYPE_DMA) {
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if (t->tx_buf)
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dma_unmap_single(NULL, t->tx_dma, davinci_spi->wcount,
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DMA_TO_DEVICE);
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dma_unmap_single(NULL, t->rx_dma, rx_buf_count,
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DMA_FROM_DEVICE);
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clear_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN);
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}
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/*
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* Check for bit error, desync error,parity error,timeout error and
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@ -572,6 +704,11 @@ static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t)
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return ret;
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}
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if (davinci_spi->rcount != 0 || davinci_spi->wcount != 0) {
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dev_err(sdev, "SPI data transfer error\n");
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return -EIO;
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}
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return t->len;
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}
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@ -601,174 +738,6 @@ static irqreturn_t davinci_spi_irq(s32 irq, void *context_data)
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return IRQ_HANDLED;
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}
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static void davinci_spi_dma_callback(unsigned lch, u16 status, void *data)
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{
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struct davinci_spi *davinci_spi = data;
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struct davinci_spi_dma *davinci_spi_dma = &davinci_spi->dma_channels;
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edma_stop(lch);
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if (status == DMA_COMPLETE) {
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if (lch == davinci_spi_dma->dma_rx_channel)
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davinci_spi->rcount = 0;
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if (lch == davinci_spi_dma->dma_tx_channel)
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davinci_spi->wcount = 0;
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}
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if ((!davinci_spi->wcount && !davinci_spi->rcount) ||
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(status != DMA_COMPLETE))
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complete(&davinci_spi->done);
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}
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static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t)
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{
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struct davinci_spi *davinci_spi;
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int int_status = 0;
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unsigned rx_buf_count;
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struct davinci_spi_dma *davinci_spi_dma;
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int data_type, ret;
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unsigned long tx_reg, rx_reg;
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struct davinci_spi_platform_data *pdata;
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void *rx_buf;
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struct device *sdev;
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struct edmacc_param param;
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davinci_spi = spi_master_get_devdata(spi->master);
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pdata = davinci_spi->pdata;
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sdev = davinci_spi->bitbang.master->dev.parent;
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davinci_spi_dma = &davinci_spi->dma_channels;
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/* convert len to words based on bits_per_word */
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data_type = davinci_spi->bytes_per_word[spi->chip_select];
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tx_reg = (unsigned long)davinci_spi->pbase + SPIDAT1;
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rx_reg = (unsigned long)davinci_spi->pbase + SPIBUF;
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davinci_spi->tx = t->tx_buf;
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davinci_spi->rx = t->rx_buf;
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davinci_spi->wcount = t->len / data_type;
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davinci_spi->rcount = davinci_spi->wcount;
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INIT_COMPLETION(davinci_spi->done);
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/* disable all interrupts for dma transfers */
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clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL);
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/* Enable SPI */
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set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
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/*
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* Transmit DMA setup
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*
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* If there is transmit data, map the transmit buffer, set it as the
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* source of data and set the source B index to data size.
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* If there is no transmit data, set the transmit register as the
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* source of data, and set the source B index to zero.
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*
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* The destination is always the transmit register itself. And the
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* destination never increments.
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*/
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if (t->tx_buf) {
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t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf,
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davinci_spi->wcount, DMA_TO_DEVICE);
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if (dma_mapping_error(&spi->dev, t->tx_dma)) {
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dev_dbg(sdev, "Unable to DMA map %d bytes TX buffer\n",
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davinci_spi->wcount);
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return -ENOMEM;
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}
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}
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param.opt = TCINTEN | EDMA_TCC(davinci_spi_dma->dma_tx_channel);
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param.src = t->tx_buf ? t->tx_dma : tx_reg;
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param.a_b_cnt = davinci_spi->wcount << 16 | data_type;
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param.dst = tx_reg;
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param.src_dst_bidx = t->tx_buf ? data_type : 0;
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param.link_bcntrld = 0xffff;
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param.src_dst_cidx = 0;
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param.ccnt = 1;
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edma_write_slot(davinci_spi_dma->dma_tx_channel, ¶m);
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edma_link(davinci_spi_dma->dma_tx_channel,
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davinci_spi_dma->dummy_param_slot);
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/*
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* Receive DMA setup
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*
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* If there is receive buffer, use it to receive data. If there
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* is none provided, use a temporary receive buffer. Set the
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* destination B index to 0 so effectively only one byte is used
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* in the temporary buffer (address does not increment).
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*
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* The source of receive data is the receive data register. The
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* source address never increments.
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*/
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if (t->rx_buf) {
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rx_buf = t->rx_buf;
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rx_buf_count = davinci_spi->rcount;
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} else {
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rx_buf = davinci_spi->rx_tmp_buf;
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rx_buf_count = sizeof(davinci_spi->rx_tmp_buf);
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}
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t->rx_dma = dma_map_single(&spi->dev, rx_buf, rx_buf_count,
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DMA_FROM_DEVICE);
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if (dma_mapping_error(&spi->dev, t->rx_dma)) {
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dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n",
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rx_buf_count);
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if (t->tx_buf)
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dma_unmap_single(NULL, t->tx_dma, davinci_spi->wcount,
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DMA_TO_DEVICE);
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return -ENOMEM;
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}
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param.opt = TCINTEN | EDMA_TCC(davinci_spi_dma->dma_rx_channel);
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param.src = rx_reg;
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param.a_b_cnt = davinci_spi->rcount << 16 | data_type;
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param.dst = t->rx_dma;
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param.src_dst_bidx = (t->rx_buf ? data_type : 0) << 16;
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param.link_bcntrld = 0xffff;
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param.src_dst_cidx = 0;
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param.ccnt = 1;
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edma_write_slot(davinci_spi_dma->dma_rx_channel, ¶m);
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if (pdata->cshold_bug) {
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u16 spidat1 = ioread16(davinci_spi->base + SPIDAT1 + 2);
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iowrite16(spidat1, davinci_spi->base + SPIDAT1 + 2);
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}
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edma_start(davinci_spi_dma->dma_rx_channel);
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edma_start(davinci_spi_dma->dma_tx_channel);
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set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN);
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wait_for_completion_interruptible(&davinci_spi->done);
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if (t->tx_buf)
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dma_unmap_single(NULL, t->tx_dma, davinci_spi->wcount,
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DMA_TO_DEVICE);
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dma_unmap_single(NULL, t->rx_dma, rx_buf_count, DMA_FROM_DEVICE);
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clear_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN);
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/*
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* Check for bit error, desync error,parity error,timeout error and
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* receive overflow errors
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*/
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int_status = ioread32(davinci_spi->base + SPIFLG);
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ret = davinci_spi_check_error(davinci_spi, int_status);
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if (ret != 0)
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return ret;
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if (davinci_spi->rcount != 0 || davinci_spi->wcount != 0) {
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dev_err(sdev, "SPI data transfer error\n");
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return -EIO;
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}
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return t->len;
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}
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static int davinci_spi_request_dma(struct davinci_spi *davinci_spi)
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{
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int r;
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@ -918,7 +887,7 @@ static int davinci_spi_probe(struct platform_device *pdev)
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if (r)
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dma_eventq = r->start;
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davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_pio;
|
||||
davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs;
|
||||
if (dma_rx_chan != SPI_NO_RESOURCE &&
|
||||
dma_tx_chan != SPI_NO_RESOURCE &&
|
||||
dma_eventq != SPI_NO_RESOURCE) {
|
||||
@ -930,10 +899,9 @@ static int davinci_spi_probe(struct platform_device *pdev)
|
||||
if (ret)
|
||||
goto free_clk;
|
||||
|
||||
davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_dma;
|
||||
dev_info(&pdev->dev, "DaVinci SPI driver in EDMA mode\n"
|
||||
"Using RX channel = %d , TX channel = %d and "
|
||||
"event queue = %d", dma_rx_chan, dma_tx_chan,
|
||||
dev_info(&pdev->dev, "DMA: supported\n");
|
||||
dev_info(&pdev->dev, "DMA: RX channel: %d, TX channel: %d, "
|
||||
"event queue: %d\n", dma_rx_chan, dma_tx_chan,
|
||||
dma_eventq);
|
||||
}
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user