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[IA64] Update processor_info features
Add the printing of additional processor features to proc_features. Based on Rev 2.2 of Volume 2 of "Intel Itanium Architecture Software Developer's Manual" (January 2006) fields (pages 2:430-2:432). This patch gets the features back in sync with the spec. Sample output before: -------------------------------------------------------------- cobra:~ # cat /proc/pal/cpu0/processor_info XIP,XPSR,XFS implemented : On NoCtrl XR1-XR3 implemented : On NoCtrl Disable dynamic predicate prediction : NotImpl Disable processor physical number : NotImpl Disable dynamic data cache prefetch : NotImpl Disable dynamic inst cache prefetch : NotImpl Disable dynamic branch prediction : NotImpl Disable BINIT on processor time-out : On Ctrl Disable dynamic power management (DPM) : NotImpl Disable coherency : NotImpl Disable cache : NotImpl Enable CMCI promotion : Off Ctrl Enable MCA to BINIT promotion : Off Ctrl Enable MCA promotion : NotImpl Enable BERR promotion : NotImpl cobra:~ # -------------------------------------------------------------- Sample output after: -------------------------------------------------------------- cobra:~ # cat /proc/pal/cpu0/processor_info Unimplemented instruction address fault : NotImpl INIT, PMI, and LINT pins : NotImpl Simple unimplimented instr addresses : On NoCtrl Variable P-state performance : NotImpl Virtual machine features implemeted : On NoCtrl XIP,XPSR,XFS implemented : On NoCtrl XR1-XR3 implemented : On NoCtrl Disable dynamic predicate prediction : NotImpl Disable processor physical number : NotImpl Disable dynamic data cache prefetch : NotImpl Disable dynamic inst cache prefetch : NotImpl Disable dynamic branch prediction : NotImpl Disable P-states : Off Ctrl Enable MCA on Data Poisoning : Off Ctrl Enable vmsw instruction : On Ctrl Enable extern environmental notification : NotImpl Disable BINIT on processor time-out : On Ctrl Disable dynamic power management (DPM) : NotImpl Disable coherency : NotImpl Disable cache : NotImpl Enable CMCI promotion : Off Ctrl Enable MCA to BINIT promotion : Off Ctrl Enable MCA promotion : NotImpl Enable BERR promotion : NotImpl cobra:~ # -------------------------------------------------------------- Signed-off-by: Russ Anderson (rja@sgi.com) Signed-off-by: Tony Luck <tony.luck@intel.com>
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@ -16,6 +16,7 @@
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* 02/05/2001 S.Eranian fixed module support
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* 10/23/2001 S.Eranian updated pal_perf_mon_info bug fixes
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* 03/24/2004 Ashok Raj updated to work with CPU Hotplug
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* 10/26/2006 Russ Anderson updated processor features to rev 2.2 spec
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*/
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#include <linux/types.h>
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#include <linux/errno.h>
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@ -467,7 +468,11 @@ static const char *proc_features[]={
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NULL,NULL,NULL,NULL,NULL,NULL,NULL, NULL,NULL,
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NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,
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NULL,NULL,NULL,NULL,NULL, NULL,NULL,NULL,NULL,
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NULL,NULL,NULL,NULL,NULL,
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"Unimplemented instruction address fault",
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"INIT, PMI, and LINT pins",
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"Simple unimplemented instr addresses",
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"Variable P-state performance",
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"Virtual machine features implemented",
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"XIP,XPSR,XFS implemented",
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"XR1-XR3 implemented",
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"Disable dynamic predicate prediction",
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@ -475,7 +480,11 @@ static const char *proc_features[]={
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"Disable dynamic data cache prefetch",
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"Disable dynamic inst cache prefetch",
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"Disable dynamic branch prediction",
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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"Disable P-states",
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"Enable MCA on Data Poisoning",
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"Enable vmsw instruction",
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"Enable extern environmental notification",
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"Disable BINIT on processor time-out",
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"Disable dynamic power management (DPM)",
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"Disable coherency",
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