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ARM: pxa: remove unused pxa3xx-ulpi
This was only used by the cm-x300 board, which is now gone. Cc: Alan Stern <stern@rowland.harvard.edu> Cc: linux-usb@vger.kernel.org Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
parent
0ddc052416
commit
8ca79aaad8
@ -144,7 +144,6 @@ config CPU_PXA300
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config CPU_PXA310
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bool
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select CPU_PXA300
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select PXA310_ULPI if USB_ULPI
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help
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PXA310 (codename Monahans-LV)
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@ -172,7 +171,4 @@ config SHARPSL_PM_MAX1111
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select SPI
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select SPI_MASTER
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config PXA310_ULPI
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bool
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endif
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@ -12,7 +12,7 @@ obj-$(CONFIG_PM) += pm.o sleep.o standby.o
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# SoC-specific code
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obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o pxa2xx.o pxa25x.o
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obj-$(CONFIG_PXA27x) += mfp-pxa2xx.o pxa2xx.o pxa27x.o
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obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o pxa3xx.o smemc.o pxa3xx-ulpi.o
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obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o pxa3xx.o smemc.o
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obj-$(CONFIG_CPU_PXA300) += pxa300.o
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obj-$(CONFIG_CPU_PXA320) += pxa320.o
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@ -12,7 +12,6 @@
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#include <linux/soc/pxa/cpu.h>
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#include "udc.h"
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#include <linux/platform_data/usb-pxa3xx-ulpi.h>
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#include <linux/platform_data/video-pxafb.h>
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#include <linux/platform_data/mmc-pxamci.h>
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#include "irqs.h"
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@ -130,33 +129,6 @@ struct platform_device pxa27x_device_udc = {
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}
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};
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#ifdef CONFIG_PXA3xx
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static struct resource pxa3xx_u2d_resources[] = {
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[0] = {
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.start = 0x54100000,
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.end = 0x54100fff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_USB2,
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.end = IRQ_USB2,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device pxa3xx_device_u2d = {
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.name = "pxa3xx-u2d",
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.id = -1,
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.resource = pxa3xx_u2d_resources,
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.num_resources = ARRAY_SIZE(pxa3xx_u2d_resources),
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};
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void __init pxa3xx_set_u2d_info(struct pxa3xx_u2d_platform_data *info)
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{
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pxa_register_device(&pxa3xx_device_u2d, info);
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}
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#endif /* CONFIG_PXA3xx */
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static struct resource pxafb_resources[] = {
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[0] = {
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.start = 0x44000000,
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@ -9,7 +9,6 @@ extern struct platform_device pxa3xx_device_mci2;
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extern struct platform_device pxa3xx_device_mci3;
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extern struct platform_device pxa25x_device_udc;
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extern struct platform_device pxa27x_device_udc;
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extern struct platform_device pxa3xx_device_u2d;
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extern struct platform_device pxa_device_fb;
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extern struct platform_device pxa_device_ffuart;
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extern struct platform_device pxa_device_btuart;
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@ -1,385 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* linux/arch/arm/mach-pxa/pxa3xx-ulpi.c
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*
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* code specific to pxa3xx aka Monahans
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*
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* Copyright (C) 2010 CompuLab Ltd.
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*
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* 2010-13-07: Igor Grinberg <grinberg@compulab.co.il>
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* initial version: pxa310 USB Host mode support
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/usb.h>
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#include <linux/usb/otg.h>
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#include <linux/soc/pxa/cpu.h>
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#include "regs-u2d.h"
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#include <linux/platform_data/usb-pxa3xx-ulpi.h>
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struct pxa3xx_u2d_ulpi {
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struct clk *clk;
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void __iomem *mmio_base;
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struct usb_phy *otg;
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unsigned int ulpi_mode;
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};
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static struct pxa3xx_u2d_ulpi *u2d;
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static inline u32 u2d_readl(u32 reg)
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{
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return __raw_readl(u2d->mmio_base + reg);
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}
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static inline void u2d_writel(u32 reg, u32 val)
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{
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__raw_writel(val, u2d->mmio_base + reg);
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}
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#if defined(CONFIG_PXA310_ULPI)
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enum u2d_ulpi_phy_mode {
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SYNCH = 0,
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CARKIT = (1 << 0),
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SER_3PIN = (1 << 1),
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SER_6PIN = (1 << 2),
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LOWPOWER = (1 << 3),
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};
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static inline enum u2d_ulpi_phy_mode pxa310_ulpi_get_phymode(void)
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{
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return (u2d_readl(U2DOTGUSR) >> 28) & 0xF;
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}
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static int pxa310_ulpi_poll(void)
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{
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int timeout = 50000;
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while (timeout--) {
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if (!(u2d_readl(U2DOTGUCR) & U2DOTGUCR_RUN))
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return 0;
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cpu_relax();
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}
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pr_warn("%s: ULPI access timed out!\n", __func__);
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return -ETIMEDOUT;
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}
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static int pxa310_ulpi_read(struct usb_phy *otg, u32 reg)
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{
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int err;
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if (pxa310_ulpi_get_phymode() != SYNCH) {
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pr_warn("%s: PHY is not in SYNCH mode!\n", __func__);
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return -EBUSY;
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}
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u2d_writel(U2DOTGUCR, U2DOTGUCR_RUN | U2DOTGUCR_RNW | (reg << 16));
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msleep(5);
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err = pxa310_ulpi_poll();
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if (err)
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return err;
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return u2d_readl(U2DOTGUCR) & U2DOTGUCR_RDATA;
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}
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static int pxa310_ulpi_write(struct usb_phy *otg, u32 val, u32 reg)
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{
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if (pxa310_ulpi_get_phymode() != SYNCH) {
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pr_warn("%s: PHY is not in SYNCH mode!\n", __func__);
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return -EBUSY;
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}
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u2d_writel(U2DOTGUCR, U2DOTGUCR_RUN | (reg << 16) | (val << 8));
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msleep(5);
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return pxa310_ulpi_poll();
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}
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struct usb_phy_io_ops pxa310_ulpi_access_ops = {
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.read = pxa310_ulpi_read,
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.write = pxa310_ulpi_write,
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};
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static void pxa310_otg_transceiver_rtsm(void)
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{
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u32 u2dotgcr;
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/* put PHY to sync mode */
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u2dotgcr = u2d_readl(U2DOTGCR);
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u2dotgcr |= U2DOTGCR_RTSM | U2DOTGCR_UTMID;
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u2d_writel(U2DOTGCR, u2dotgcr);
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msleep(10);
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/* setup OTG sync mode */
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u2dotgcr = u2d_readl(U2DOTGCR);
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u2dotgcr |= U2DOTGCR_ULAF;
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u2dotgcr &= ~(U2DOTGCR_SMAF | U2DOTGCR_CKAF);
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u2d_writel(U2DOTGCR, u2dotgcr);
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}
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static int pxa310_start_otg_host_transcvr(struct usb_bus *host)
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{
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int err;
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pxa310_otg_transceiver_rtsm();
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err = usb_phy_init(u2d->otg);
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if (err) {
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pr_err("OTG transceiver init failed");
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return err;
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}
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err = otg_set_vbus(u2d->otg->otg, 1);
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if (err) {
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pr_err("OTG transceiver VBUS set failed");
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return err;
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}
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err = otg_set_host(u2d->otg->otg, host);
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if (err)
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pr_err("OTG transceiver Host mode set failed");
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return err;
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}
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static int pxa310_start_otg_hc(struct usb_bus *host)
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{
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u32 u2dotgcr;
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int err;
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/* disable USB device controller */
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u2d_writel(U2DCR, u2d_readl(U2DCR) & ~U2DCR_UDE);
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u2d_writel(U2DOTGCR, u2d_readl(U2DOTGCR) | U2DOTGCR_UTMID);
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u2d_writel(U2DOTGICR, u2d_readl(U2DOTGICR) & ~0x37F7F);
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err = pxa310_start_otg_host_transcvr(host);
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if (err)
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return err;
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/* set xceiver mode */
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if (u2d->ulpi_mode & ULPI_IC_6PIN_SERIAL)
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u2d_writel(U2DP3CR, u2d_readl(U2DP3CR) & ~U2DP3CR_P2SS);
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else if (u2d->ulpi_mode & ULPI_IC_3PIN_SERIAL)
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u2d_writel(U2DP3CR, u2d_readl(U2DP3CR) | U2DP3CR_P2SS);
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/* start OTG host controller */
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u2dotgcr = u2d_readl(U2DOTGCR) | U2DOTGCR_SMAF;
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u2d_writel(U2DOTGCR, u2dotgcr & ~(U2DOTGCR_ULAF | U2DOTGCR_CKAF));
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return 0;
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}
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static void pxa310_stop_otg_hc(void)
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{
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pxa310_otg_transceiver_rtsm();
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otg_set_host(u2d->otg->otg, NULL);
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otg_set_vbus(u2d->otg->otg, 0);
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usb_phy_shutdown(u2d->otg);
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}
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static void pxa310_u2d_setup_otg_hc(void)
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{
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u32 u2dotgcr;
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u2dotgcr = u2d_readl(U2DOTGCR);
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u2dotgcr |= U2DOTGCR_ULAF | U2DOTGCR_UTMID;
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u2dotgcr &= ~(U2DOTGCR_SMAF | U2DOTGCR_CKAF);
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u2d_writel(U2DOTGCR, u2dotgcr);
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msleep(5);
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u2d_writel(U2DOTGCR, u2dotgcr | U2DOTGCR_ULE);
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msleep(5);
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u2d_writel(U2DOTGICR, u2d_readl(U2DOTGICR) & ~0x37F7F);
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}
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static int pxa310_otg_init(struct pxa3xx_u2d_platform_data *pdata)
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{
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unsigned int ulpi_mode = ULPI_OTG_DRVVBUS;
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if (pdata) {
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if (pdata->ulpi_mode & ULPI_SER_6PIN)
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ulpi_mode |= ULPI_IC_6PIN_SERIAL;
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else if (pdata->ulpi_mode & ULPI_SER_3PIN)
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ulpi_mode |= ULPI_IC_3PIN_SERIAL;
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}
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u2d->ulpi_mode = ulpi_mode;
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u2d->otg = otg_ulpi_create(&pxa310_ulpi_access_ops, ulpi_mode);
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if (!u2d->otg)
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return -ENOMEM;
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u2d->otg->io_priv = u2d->mmio_base;
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return 0;
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}
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static void pxa310_otg_exit(void)
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{
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kfree(u2d->otg);
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}
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#else
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static inline void pxa310_u2d_setup_otg_hc(void) {}
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static inline int pxa310_start_otg_hc(struct usb_bus *host)
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{
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return 0;
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}
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static inline void pxa310_stop_otg_hc(void) {}
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static inline int pxa310_otg_init(struct pxa3xx_u2d_platform_data *pdata)
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{
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return 0;
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}
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static inline void pxa310_otg_exit(void) {}
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#endif /* CONFIG_PXA310_ULPI */
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int pxa3xx_u2d_start_hc(struct usb_bus *host)
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{
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int err = 0;
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/* In case the PXA3xx ULPI isn't used, do nothing. */
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if (!u2d)
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return 0;
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clk_prepare_enable(u2d->clk);
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if (cpu_is_pxa310()) {
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pxa310_u2d_setup_otg_hc();
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err = pxa310_start_otg_hc(host);
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}
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return err;
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}
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EXPORT_SYMBOL_GPL(pxa3xx_u2d_start_hc);
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void pxa3xx_u2d_stop_hc(struct usb_bus *host)
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{
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/* In case the PXA3xx ULPI isn't used, do nothing. */
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if (!u2d)
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return;
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if (cpu_is_pxa310())
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pxa310_stop_otg_hc();
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clk_disable_unprepare(u2d->clk);
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}
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EXPORT_SYMBOL_GPL(pxa3xx_u2d_stop_hc);
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static int pxa3xx_u2d_probe(struct platform_device *pdev)
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{
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struct pxa3xx_u2d_platform_data *pdata = pdev->dev.platform_data;
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struct resource *r;
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int err;
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u2d = kzalloc(sizeof(*u2d), GFP_KERNEL);
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if (!u2d)
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return -ENOMEM;
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u2d->clk = clk_get(&pdev->dev, NULL);
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if (IS_ERR(u2d->clk)) {
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dev_err(&pdev->dev, "failed to get u2d clock\n");
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err = PTR_ERR(u2d->clk);
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goto err_free_mem;
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}
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!r) {
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dev_err(&pdev->dev, "no IO memory resource defined\n");
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err = -ENODEV;
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goto err_put_clk;
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}
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r = request_mem_region(r->start, resource_size(r), pdev->name);
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if (!r) {
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dev_err(&pdev->dev, "failed to request memory resource\n");
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err = -EBUSY;
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goto err_put_clk;
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}
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u2d->mmio_base = ioremap(r->start, resource_size(r));
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if (!u2d->mmio_base) {
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dev_err(&pdev->dev, "ioremap() failed\n");
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err = -ENODEV;
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goto err_free_res;
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}
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if (pdata->init) {
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err = pdata->init(&pdev->dev);
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if (err)
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goto err_free_io;
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}
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/* Only PXA310 U2D has OTG functionality */
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if (cpu_is_pxa310()) {
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err = pxa310_otg_init(pdata);
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if (err)
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goto err_free_plat;
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}
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platform_set_drvdata(pdev, u2d);
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return 0;
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err_free_plat:
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if (pdata->exit)
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pdata->exit(&pdev->dev);
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err_free_io:
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iounmap(u2d->mmio_base);
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err_free_res:
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release_mem_region(r->start, resource_size(r));
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err_put_clk:
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clk_put(u2d->clk);
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err_free_mem:
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kfree(u2d);
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return err;
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}
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static int pxa3xx_u2d_remove(struct platform_device *pdev)
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{
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struct pxa3xx_u2d_platform_data *pdata = pdev->dev.platform_data;
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struct resource *r;
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if (cpu_is_pxa310()) {
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pxa310_stop_otg_hc();
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pxa310_otg_exit();
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}
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if (pdata->exit)
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pdata->exit(&pdev->dev);
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platform_set_drvdata(pdev, NULL);
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iounmap(u2d->mmio_base);
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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release_mem_region(r->start, resource_size(r));
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clk_put(u2d->clk);
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kfree(u2d);
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return 0;
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}
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|
||||
static struct platform_driver pxa3xx_u2d_ulpi_driver = {
|
||||
.driver = {
|
||||
.name = "pxa3xx-u2d",
|
||||
},
|
||||
.probe = pxa3xx_u2d_probe,
|
||||
.remove = pxa3xx_u2d_remove,
|
||||
};
|
||||
module_platform_driver(pxa3xx_u2d_ulpi_driver);
|
||||
|
||||
MODULE_DESCRIPTION("PXA3xx U2D ULPI driver");
|
||||
MODULE_AUTHOR("Igor Grinberg");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
@ -1,199 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __ASM_ARCH_PXA3xx_U2D_H
|
||||
#define __ASM_ARCH_PXA3xx_U2D_H
|
||||
|
||||
/*
|
||||
* USB2 device controller registers and bits definitions
|
||||
*/
|
||||
#define U2DCR (0x0000) /* U2D Control Register */
|
||||
#define U2DCR_NDC (1 << 31) /* NAK During Config */
|
||||
#define U2DCR_HSTC (0x7 << 28) /* High Speed Timeout Calibration */
|
||||
#define U2DCR_SPEOREN (1 << 27) /* Short Packet EOR INTR generation Enable */
|
||||
#define U2DCR_FSTC (0x7 << 24) /* Full Speed Timeout Calibration */
|
||||
#define U2DCR_UCLKOVR (1 << 22) /* UTM Clock Override */
|
||||
#define U2DCR_ABP (1 << 21) /* Application Bus Power */
|
||||
#define U2DCR_ADD (1 << 20) /* Application Device Disconnect */
|
||||
#define U2DCR_CC (1 << 19) /* Configuration Change */
|
||||
#define U2DCR_HS (1 << 18) /* High Speed USB Detection */
|
||||
#define U2DCR_SMAC (1 << 17) /* Switch Endpoint Memory to Active Configuration */
|
||||
#define U2DCR_DWRE (1 << 16) /* Device Remote Wake-up Feature */
|
||||
#define U2DCR_ACN (0xf << 12) /* Active U2D Configuration Number */
|
||||
#define U2DCR_AIN (0xf << 8) /* Active U2D Interface Number */
|
||||
#define U2DCR_AAISN (0xf << 4) /* Active U2D Alternate Interface Setting Number */
|
||||
#define U2DCR_EMCE (1 << 3) /* Endpoint Memory Configuration Error */
|
||||
#define U2DCR_UDR (1 << 2) /* U2D Resume */
|
||||
#define U2DCR_UDA (1 << 1) /* U2D Active */
|
||||
#define U2DCR_UDE (1 << 0) /* U2D Enable */
|
||||
|
||||
#define U2DICR (0x0004) /* U2D Interrupt Control Register */
|
||||
#define U2DISR (0x000C) /* U2D Interrupt Status Register */
|
||||
#define U2DINT_CC (1 << 31) /* Interrupt - Configuration Change */
|
||||
#define U2DINT_SOF (1 << 30) /* Interrupt - SOF */
|
||||
#define U2DINT_USOF (1 << 29) /* Interrupt - micro SOF */
|
||||
#define U2DINT_RU (1 << 28) /* Interrupt - Resume */
|
||||
#define U2DINT_SU (1 << 27) /* Interrupt - Suspend */
|
||||
#define U2DINT_RS (1 << 26) /* Interrupt - Reset */
|
||||
#define U2DINT_DPE (1 << 25) /* Interrupt - Data Packet Error */
|
||||
#define U2DINT_FIFOERR (0x4) /* Interrupt - endpoint FIFO error */
|
||||
#define U2DINT_PACKETCMP (0x2) /* Interrupt - endpoint packet complete */
|
||||
#define U2DINT_SPACKETCMP (0x1) /* Interrupt - endpoint short packet complete */
|
||||
|
||||
#define U2DFNR (0x0014) /* U2D Frame Number Register */
|
||||
|
||||
#define U2DINT(n, intr) (((intr) & 0x07) << (((n) & 0x07) * 3))
|
||||
#define U2DICR2 (0x0008) /* U2D Interrupt Control Register 2 */
|
||||
#define U2DISR2 (0x0010) /* U2D Interrupt Status Register 2 */
|
||||
|
||||
#define U2DOTGCR (0x0020) /* U2D OTG Control Register */
|
||||
#define U2DOTGCR_OTGEN (1 << 31) /* On-The-Go Enable */
|
||||
#define U2DOTGCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation Protocal Port Support */
|
||||
#define U2DOTGCR_AHNP (1 << 29) /* A-device Host Negotiation Protocal Support */
|
||||
#define U2DOTGCR_BHNP (1 << 28) /* B-device Host Negotiation Protocal Enable */
|
||||
|
||||
#ifdef CONFIG_CPU_PXA930
|
||||
#define U2DOTGCR_LPA (1 << 15) /* ULPI low power mode active */
|
||||
#define U2DOTGCR_IESI (1 << 13) /* OTG interrupt Enable */
|
||||
#define U2DOTGCR_ISSI (1 << 12) /* OTG interrupt status */
|
||||
#endif
|
||||
|
||||
#define U2DOTGCR_CKAF (1 << 5) /* Carkit Mode Alternate Function Select */
|
||||
#define U2DOTGCR_UTMID (1 << 4) /* UTMI Interface Disable */
|
||||
#define U2DOTGCR_ULAF (1 << 3) /* ULPI Mode Alternate Function Select */
|
||||
#define U2DOTGCR_SMAF (1 << 2) /* Serial Mode Alternate Function Select */
|
||||
#define U2DOTGCR_RTSM (1 << 1) /* Return to Synchronous Mode (ULPI Mode) */
|
||||
#define U2DOTGCR_ULE (1 << 0) /* ULPI Wrapper Enable */
|
||||
|
||||
#define U2DOTGICR (0x0024) /* U2D OTG Interrupt Control Register */
|
||||
#define U2DOTGISR (0x0028) /* U2D OTG Interrupt Status Register */
|
||||
|
||||
#define U2DOTGINT_SF (1 << 17) /* OTG Set Feature Command Received */
|
||||
#define U2DOTGINT_SI (1 << 16) /* OTG Interrupt */
|
||||
#define U2DOTGINT_RLS1 (1 << 14) /* RXCMD Linestate[1] Change Interrupt Rise */
|
||||
#define U2DOTGINT_RLS0 (1 << 13) /* RXCMD Linestate[0] Change Interrupt Rise */
|
||||
#define U2DOTGINT_RID (1 << 12) /* RXCMD OTG ID Change Interrupt Rise */
|
||||
#define U2DOTGINT_RSE (1 << 11) /* RXCMD OTG Session End Interrupt Rise */
|
||||
#define U2DOTGINT_RSV (1 << 10) /* RXCMD OTG Session Valid Interrupt Rise */
|
||||
#define U2DOTGINT_RVV (1 << 9) /* RXCMD OTG Vbus Valid Interrupt Rise */
|
||||
#define U2DOTGINT_RCK (1 << 8) /* RXCMD Carkit Interrupt Rise */
|
||||
#define U2DOTGINT_FLS1 (1 << 6) /* RXCMD Linestate[1] Change Interrupt Fall */
|
||||
#define U2DOTGINT_FLS0 (1 << 5) /* RXCMD Linestate[0] Change Interrupt Fall */
|
||||
#define U2DOTGINT_FID (1 << 4) /* RXCMD OTG ID Change Interrupt Fall */
|
||||
#define U2DOTGINT_FSE (1 << 3) /* RXCMD OTG Session End Interrupt Fall */
|
||||
#define U2DOTGINT_FSV (1 << 2) /* RXCMD OTG Session Valid Interrupt Fall */
|
||||
#define U2DOTGINT_FVV (1 << 1) /* RXCMD OTG Vbus Valid Interrupt Fall */
|
||||
#define U2DOTGINT_FCK (1 << 0) /* RXCMD Carkit Interrupt Fall */
|
||||
|
||||
#define U2DOTGUSR (0x002C) /* U2D OTG ULPI Status Register */
|
||||
#define U2DOTGUSR_LPA (1 << 31) /* ULPI Low Power Mode Active */
|
||||
#define U2DOTGUSR_S6A (1 << 30) /* ULPI Serial Mode (6-pin) Active */
|
||||
#define U2DOTGUSR_S3A (1 << 29) /* ULPI Serial Mode (3-pin) Active */
|
||||
#define U2DOTGUSR_CKA (1 << 28) /* ULPI Car Kit Mode Active */
|
||||
#define U2DOTGUSR_LS1 (1 << 6) /* RXCMD Linestate 1 Status */
|
||||
#define U2DOTGUSR_LS0 (1 << 5) /* RXCMD Linestate 0 Status */
|
||||
#define U2DOTGUSR_ID (1 << 4) /* OTG IDGnd Status */
|
||||
#define U2DOTGUSR_SE (1 << 3) /* OTG Session End Status */
|
||||
#define U2DOTGUSR_SV (1 << 2) /* OTG Session Valid Status */
|
||||
#define U2DOTGUSR_VV (1 << 1) /* OTG Vbus Valid Status */
|
||||
#define U2DOTGUSR_CK (1 << 0) /* Carkit Interrupt Status */
|
||||
|
||||
#define U2DOTGUCR (0x0030) /* U2D OTG ULPI Control Register */
|
||||
#define U2DOTGUCR_RUN (1 << 25) /* RUN */
|
||||
#define U2DOTGUCR_RNW (1 << 24) /* Read or Write operation */
|
||||
#define U2DOTGUCR_ADDR (0x3f << 16) /* Address of the ULPI PHY register */
|
||||
#define U2DOTGUCR_WDATA (0xff << 8) /* The data for a WRITE command */
|
||||
#define U2DOTGUCR_RDATA (0xff << 0) /* The data for a READ command */
|
||||
|
||||
#define U2DP3CR (0x0034) /* U2D Port 3 Control Register */
|
||||
#define U2DP3CR_P2SS (0x3 << 8) /* Host Port 2 Serial Mode Select */
|
||||
#define U2DP3CR_P3SS (0x7 << 4) /* Host Port 3 Serial Mode Select */
|
||||
#define U2DP3CR_VPVMBEN (0x1 << 2) /* Host Port 3 Vp/Vm Block Enable */
|
||||
#define U2DP3CR_CFG (0x3 << 0) /* Host Port 3 Configuration */
|
||||
|
||||
#define U2DCSR0 (0x0100) /* U2D Control/Status Register - Endpoint 0 */
|
||||
#define U2DCSR0_IPA (1 << 8) /* IN Packet Adjusted */
|
||||
#define U2DCSR0_SA (1 << 7) /* SETUP Active */
|
||||
#define U2DCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */
|
||||
#define U2DCSR0_FST (1 << 5) /* Force Stall */
|
||||
#define U2DCSR0_SST (1 << 4) /* Send Stall */
|
||||
#define U2DCSR0_DME (1 << 3) /* DMA Enable */
|
||||
#define U2DCSR0_FTF (1 << 2) /* Flush Transmit FIFO */
|
||||
#define U2DCSR0_IPR (1 << 1) /* IN Packet Ready */
|
||||
#define U2DCSR0_OPC (1 << 0) /* OUT Packet Complete */
|
||||
|
||||
#define U2DCSR(x) (0x0100 + ((x) << 2)) /* U2D Control/Status Register - Endpoint x */
|
||||
#define U2DCSR_BF (1 << 10) /* Buffer Full, for OUT eps */
|
||||
#define U2DCSR_BE (1 << 10) /* Buffer Empty, for IN eps */
|
||||
#define U2DCSR_DPE (1 << 9) /* Data Packet Error, for ISO eps only */
|
||||
#define U2DCSR_FEF (1 << 8) /* Flush Endpoint FIFO */
|
||||
#define U2DCSR_SP (1 << 7) /* Short Packet Control/Status, for OUT eps only, readonly */
|
||||
#define U2DCSR_BNE (1 << 6) /* Buffer Not Empty, for OUT eps */
|
||||
#define U2DCSR_BNF (1 << 6) /* Buffer Not Full, for IN eps */
|
||||
#define U2DCSR_FST (1 << 5) /* Force STALL, write 1 set */
|
||||
#define U2DCSR_SST (1 << 4) /* Sent STALL, write 1 clear */
|
||||
#define U2DCSR_DME (1 << 3) /* DMA Enable */
|
||||
#define U2DCSR_TRN (1 << 2) /* Tx/Rx NAK, write 1 clear */
|
||||
#define U2DCSR_PC (1 << 1) /* Packet Complete, write 1 clear */
|
||||
#define U2DCSR_FS (1 << 0) /* FIFO needs Service */
|
||||
|
||||
#define U2DBCR0 (0x0200) /* U2D Byte Count Register - Endpoint 0 */
|
||||
#define U2DBCR(x) (0x0200 + ((x) << 2)) /* U2D Byte Count Register - Endpoint x */
|
||||
|
||||
#define U2DDR0 (0x0300) /* U2D Data Register - Endpoint 0 */
|
||||
|
||||
#define U2DEPCR(x) (0x0400 + ((x) << 2)) /* U2D Configuration Register - Endpoint x */
|
||||
#define U2DEPCR_EE (1 << 0) /* Endpoint Enable */
|
||||
#define U2DEPCR_BS_MASK (0x3FE) /* Buffer Size, BS*8=FIFO size, max 8184B = 8KB */
|
||||
|
||||
#define U2DSCA (0x0500) /* U2D Setup Command Address */
|
||||
#define U2DSCA_VALUE (0x0120)
|
||||
|
||||
#define U2DEN0 (0x0504) /* U2D Endpoint Information Register - Endpoint 0 */
|
||||
#define U2DEN(x) (0x0504 + ((x) << 2)) /* U2D Endpoint Information Register - Endpoint x */
|
||||
|
||||
/* U2DMA registers */
|
||||
#define U2DMACSR0 (0x1000) /* U2DMA Control/Status Register - Channel 0 */
|
||||
#define U2DMACSR(x) (0x1000 + ((x) << 2)) /* U2DMA Control/Status Register - Channel x */
|
||||
#define U2DMACSR_RUN (1 << 31) /* Run Bit (read / write) */
|
||||
#define U2DMACSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */
|
||||
#define U2DMACSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */
|
||||
#define U2DMACSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
|
||||
#define U2DMACSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
|
||||
#define U2DMACSR_RASIRQEN (1 << 23) /* Request After Cnannel Stopped Interrupt Enable */
|
||||
#define U2DMACSR_MASKRUN (1 << 22) /* Mask Run */
|
||||
#define U2DMACSR_SCEMC (3 << 18) /* System Bus Split Completion Error Message Class */
|
||||
#define U2DMACSR_SCEMI (0x1f << 13) /* System Bus Split Completion Error Message Index */
|
||||
#define U2DMACSR_BUSERRTYPE (7 << 10) /* PX Bus Error Type */
|
||||
#define U2DMACSR_EORINTR (1 << 9) /* End Of Receive */
|
||||
#define U2DMACSR_REQPEND (1 << 8) /* Request Pending */
|
||||
#define U2DMACSR_RASINTR (1 << 4) /* Request After Channel Stopped (read / write 1 clear) */
|
||||
#define U2DMACSR_STOPINTR (1 << 3) /* Stop Interrupt (read only) */
|
||||
#define U2DMACSR_ENDINTR (1 << 2) /* End Interrupt (read / write 1 clear) */
|
||||
#define U2DMACSR_STARTINTR (1 << 1) /* Start Interrupt (read / write 1 clear) */
|
||||
#define U2DMACSR_BUSERRINTR (1 << 0) /* Bus Error Interrupt (read / write 1 clear) */
|
||||
|
||||
#define U2DMACR (0x1080) /* U2DMA Control Register */
|
||||
#define U2DMAINT (0x10F0) /* U2DMA Interrupt Register */
|
||||
|
||||
#define U2DMABR0 (0x1100) /* U2DMA Branch Register - Channel 0 */
|
||||
#define U2DMABR(x) (0x1100 + (x) << 2) /* U2DMA Branch Register - Channel x */
|
||||
|
||||
#define U2DMADADR0 (0x1200) /* U2DMA Descriptor Address Register - Channel 0 */
|
||||
#define U2DMADADR(x) (0x1200 + (x) * 0x10) /* U2DMA Descriptor Address Register - Channel x */
|
||||
|
||||
#define U2DMADADR_STOP (1U << 0)
|
||||
|
||||
#define U2DMASADR0 (0x1204) /* U2DMA Source Address Register - Channel 0 */
|
||||
#define U2DMASADR(x) (0x1204 + (x) * 0x10) /* U2DMA Source Address Register - Channel x */
|
||||
#define U2DMATADR0 (0x1208) /* U2DMA Target Address Register - Channel 0 */
|
||||
#define U2DMATADR(x) (0x1208 + (x) * 0x10) /* U2DMA Target Address Register - Channel x */
|
||||
|
||||
#define U2DMACMDR0 (0x120C) /* U2DMA Command Address Register - Channel 0 */
|
||||
#define U2DMACMDR(x) (0x120C + (x) * 0x10) /* U2DMA Command Address Register - Channel x */
|
||||
|
||||
#define U2DMACMDR_XFRDIS (1 << 31) /* Transfer Direction */
|
||||
#define U2DMACMDR_STARTIRQEN (1 << 22) /* Start Interrupt Enable */
|
||||
#define U2DMACMDR_ENDIRQEN (1 << 21) /* End Interrupt Enable */
|
||||
#define U2DMACMDR_PACKCOMP (1 << 13) /* Packet Complete */
|
||||
#define U2DMACMDR_LEN (0x07ff) /* length mask (max = 2K - 1) */
|
||||
|
||||
#endif /* __ASM_ARCH_PXA3xx_U2D_H */
|
||||
@ -29,7 +29,6 @@
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/of_gpio.h>
|
||||
#include <linux/platform_data/usb-ohci-pxa27x.h>
|
||||
#include <linux/platform_data/usb-pxa3xx-ulpi.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/regulator/consumer.h>
|
||||
#include <linux/signal.h>
|
||||
@ -275,7 +274,6 @@ static int pxa27x_start_hc(struct pxa27x_ohci *pxa_ohci, struct device *dev)
|
||||
int retval;
|
||||
struct pxaohci_platform_data *inf;
|
||||
uint32_t uhchr;
|
||||
struct usb_hcd *hcd = dev_get_drvdata(dev);
|
||||
|
||||
inf = dev_get_platdata(dev);
|
||||
|
||||
@ -301,9 +299,6 @@ static int pxa27x_start_hc(struct pxa27x_ohci *pxa_ohci, struct device *dev)
|
||||
return retval;
|
||||
}
|
||||
|
||||
if (cpu_is_pxa3xx())
|
||||
pxa3xx_u2d_start_hc(&hcd->self);
|
||||
|
||||
uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR) & ~UHCHR_SSE;
|
||||
__raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);
|
||||
__raw_writel(UHCHIE_UPRIE | UHCHIE_RWIE, pxa_ohci->mmio_base + UHCHIE);
|
||||
@ -316,14 +311,10 @@ static int pxa27x_start_hc(struct pxa27x_ohci *pxa_ohci, struct device *dev)
|
||||
static void pxa27x_stop_hc(struct pxa27x_ohci *pxa_ohci, struct device *dev)
|
||||
{
|
||||
struct pxaohci_platform_data *inf;
|
||||
struct usb_hcd *hcd = dev_get_drvdata(dev);
|
||||
uint32_t uhccoms;
|
||||
|
||||
inf = dev_get_platdata(dev);
|
||||
|
||||
if (cpu_is_pxa3xx())
|
||||
pxa3xx_u2d_stop_hc(&hcd->self);
|
||||
|
||||
if (inf->exit)
|
||||
inf->exit(dev);
|
||||
|
||||
|
||||
@ -1,32 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* PXA3xx U2D header
|
||||
*
|
||||
* Copyright (C) 2010 CompuLab Ltd.
|
||||
*
|
||||
* Igor Grinberg <grinberg@compulab.co.il>
|
||||
*/
|
||||
#ifndef __PXA310_U2D__
|
||||
#define __PXA310_U2D__
|
||||
|
||||
#include <linux/usb/ulpi.h>
|
||||
|
||||
struct pxa3xx_u2d_platform_data {
|
||||
|
||||
#define ULPI_SER_6PIN (1 << 0)
|
||||
#define ULPI_SER_3PIN (1 << 1)
|
||||
unsigned int ulpi_mode;
|
||||
|
||||
int (*init)(struct device *);
|
||||
void (*exit)(struct device *);
|
||||
};
|
||||
|
||||
|
||||
/* Start PXA3xx U2D host */
|
||||
int pxa3xx_u2d_start_hc(struct usb_bus *host);
|
||||
/* Stop PXA3xx U2D host */
|
||||
void pxa3xx_u2d_stop_hc(struct usb_bus *host);
|
||||
|
||||
extern void pxa3xx_set_u2d_info(struct pxa3xx_u2d_platform_data *info);
|
||||
|
||||
#endif /* __PXA310_U2D__ */
|
||||
Loading…
Reference in New Issue
Block a user