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SPI NOR core changes:

Browse Source 
- move SECT_4K_PMC flag out of the core as it's a vendor specific flag
 - s/addr_width/addr_nbytes: address width means the number of IO lines
   used for the address, whereas in the code it is used as the number of
   address bytes.
 - do not change nor->addr_nbytes at SFDP parsing time. At the SFDP parsing
   time we should not change members of struct spi_nor, but instead fill
   members of struct spi_nor_flash_parameters which could later on be used
   by the callers.
 - track flash's internal address mode so that we can use 4B opcodes
   together with opcodes that don't have a 4B opcode correspondent.
 
 SPI NOR manufacturer drivers changes:
 - esmt: Rename "f25l32qa" flash name to "f25l32qa-2s".
 - micron-st: Skip FSR reading if SPI controller does not support it to
   allow flashes that support FSR to work even when attached to such SPI
   controllers.
 - spansion: Add s25hl-t/s25hs-t IDs and fixups.
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Merge tag 'spi-nor/for-5.20' into mtd/next

SPI NOR core changes:
- move SECT_4K_PMC flag out of the core as it's a vendor specific flag
- s/addr_width/addr_nbytes: address width means the number of IO lines
  used for the address, whereas in the code it is used as the number of
  address bytes.
- do not change nor->addr_nbytes at SFDP parsing time. At the SFDP parsing
  time we should not change members of struct spi_nor, but instead fill
  members of struct spi_nor_flash_parameters which could later on be used
  by the callers.
- track flash's internal address mode so that we can use 4B opcodes
  together with opcodes that don't have a 4B opcode correspondent.

SPI NOR manufacturer drivers changes:
- esmt: Rename "f25l32qa" flash name to "f25l32qa-2s".
- micron-st: Skip FSR reading if SPI controller does not support it to
  allow flashes that support FSR to work even when attached to such SPI
  controllers.
- spansion: Add s25hl-t/s25hs-t IDs and fixups.
This commit is contained in:
Richard Weinberger 2022-08-01 21:31:22 +02:00
commit 9661524b9b
1069 changed files with 12113 additions and 7585 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
.mailmap
View File

@ -10,6 +10,8 @@
# Please keep this list dictionary sorted.
#
Aaron Durbin <adurbin@google.com>
Abel Vesa <abelvesa@kernel.org> <abel.vesa@nxp.com>
Abel Vesa <abelvesa@kernel.org> <abelvesa@gmail.com>
Abhinav Kumar <quic_abhinavk@quicinc.com> <abhinavk@codeaurora.org>
Adam Oldham <oldhamca@gmail.com>
Adam Radford <aradford@gmail.com>
@ -85,6 +87,7 @@ Christian Borntraeger <borntraeger@linux.ibm.com> <borntrae@de.ibm.com>
Christian Brauner <brauner@kernel.org> <christian@brauner.io>
Christian Brauner <brauner@kernel.org> <christian.brauner@canonical.com>
Christian Brauner <brauner@kernel.org> <christian.brauner@ubuntu.com>
Christian Marangi <ansuelsmth@gmail.com>
Christophe Ricard <christophe.ricard@gmail.com>
Christoph Hellwig <hch@lst.de>
Colin Ian King <colin.king@intel.com> <colin.king@canonical.com>
@ -165,6 +168,7 @@ Jan Glauber <jan.glauber@gmail.com> <jang@de.ibm.com>
Jan Glauber <jan.glauber@gmail.com> <jang@linux.vnet.ibm.com>
Jan Glauber <jan.glauber@gmail.com> <jglauber@cavium.com>
Jarkko Sakkinen <jarkko@kernel.org> <jarkko.sakkinen@linux.intel.com>
Jarkko Sakkinen <jarkko@kernel.org> <jarkko@profian.com>
Jason Gunthorpe <jgg@ziepe.ca> <jgg@mellanox.com>
Jason Gunthorpe <jgg@ziepe.ca> <jgg@nvidia.com>
Jason Gunthorpe <jgg@ziepe.ca> <jgunthorpe@obsidianresearch.com>

11
Documentation/ABI/testing/sysfs-ata
View File

@ -107,13 +107,14 @@ Description:
described in ATA8 7.16 and 7.17. Only valid if
the device is not a PM.
pio_mode: (RO) Transfer modes supported by the device when
in PIO mode. Mostly used by PATA device.
pio_mode: (RO) PIO transfer mode used by the device.
Mostly used by PATA devices.
xfer_mode: (RO) Current transfer mode
xfer_mode: (RO) Current transfer mode. Mostly used by
PATA devices.
dma_mode: (RO) Transfer modes supported by the device when
in DMA mode. Mostly used by PATA device.
dma_mode: (RO) DMA transfer mode used by the device.
Mostly used by PATA devices.
class: (RO) Device class. Can be "ata" for disk,
"atapi" for packet device, "pmp" for PM, or

2
Documentation/ABI/testing/sysfs-bus-iio-vf610
View File

@ -1,4 +1,4 @@
What: /sys/bus/iio/devices/iio:deviceX/conversion_mode
What: /sys/bus/iio/devices/iio:deviceX/in_conversion_mode
KernelVersion: 4.2
Contact: linux-iio@vger.kernel.org
Description:

1
Documentation/ABI/testing/sysfs-devices-system-cpu
View File

@ -526,6 +526,7 @@ What: /sys/devices/system/cpu/vulnerabilities
/sys/devices/system/cpu/vulnerabilities/srbds
/sys/devices/system/cpu/vulnerabilities/tsx_async_abort
/sys/devices/system/cpu/vulnerabilities/itlb_multihit
/sys/devices/system/cpu/vulnerabilities/mmio_stale_data
Date: January 2018
Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
Description: Information about CPU vulnerabilities

2
Documentation/ABI/testing/sysfs-driver-bd9571mwv-regulator
View File

@ -26,6 +26,6 @@ Description: Read/write the current state of DDR Backup Mode, which controls
DDR Backup Mode must be explicitly enabled by the user,
to invoke step 1.
See also Documentation/devicetree/bindings/mfd/bd9571mwv.txt.
See also Documentation/devicetree/bindings/mfd/rohm,bd9571mwv.yaml.
Users: User space applications for embedded boards equipped with a
BD9571MWV PMIC.

1
Documentation/admin-guide/hw-vuln/index.rst
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@ -17,3 +17,4 @@ are configurable at compile, boot or run time.
special-register-buffer-data-sampling.rst
core-scheduling.rst
l1d_flush.rst
processor_mmio_stale_data.rst

246
Documentation/admin-guide/hw-vuln/processor_mmio_stale_data.rst Normal file
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@ -0,0 +1,246 @@
=========================================
Processor MMIO Stale Data Vulnerabilities
=========================================
Processor MMIO Stale Data Vulnerabilities are a class of memory-mapped I/O
(MMIO) vulnerabilities that can expose data. The sequences of operations for
exposing data range from simple to very complex. Because most of the
vulnerabilities require the attacker to have access to MMIO, many environments
are not affected. System environments using virtualization where MMIO access is
provided to untrusted guests may need mitigation. These vulnerabilities are
not transient execution attacks. However, these vulnerabilities may propagate
stale data into core fill buffers where the data can subsequently be inferred
by an unmitigated transient execution attack. Mitigation for these
vulnerabilities includes a combination of microcode update and software
changes, depending on the platform and usage model. Some of these mitigations
are similar to those used to mitigate Microarchitectural Data Sampling (MDS) or
those used to mitigate Special Register Buffer Data Sampling (SRBDS).
Data Propagators
================
Propagators are operations that result in stale data being copied or moved from
one microarchitectural buffer or register to another. Processor MMIO Stale Data
Vulnerabilities are operations that may result in stale data being directly
read into an architectural, software-visible state or sampled from a buffer or
register.
Fill Buffer Stale Data Propagator (FBSDP)
-----------------------------------------
Stale data may propagate from fill buffers (FB) into the non-coherent portion
of the uncore on some non-coherent writes. Fill buffer propagation by itself
does not make stale data architecturally visible. Stale data must be propagated
to a location where it is subject to reading or sampling.
Sideband Stale Data Propagator (SSDP)
-------------------------------------
The sideband stale data propagator (SSDP) is limited to the client (including
Intel Xeon server E3) uncore implementation. The sideband response buffer is
shared by all client cores. For non-coherent reads that go to sideband
destinations, the uncore logic returns 64 bytes of data to the core, including
both requested data and unrequested stale data, from a transaction buffer and
the sideband response buffer. As a result, stale data from the sideband
response and transaction buffers may now reside in a core fill buffer.
Primary Stale Data Propagator (PSDP)
------------------------------------
The primary stale data propagator (PSDP) is limited to the client (including
Intel Xeon server E3) uncore implementation. Similar to the sideband response
buffer, the primary response buffer is shared by all client cores. For some
processors, MMIO primary reads will return 64 bytes of data to the core fill
buffer including both requested data and unrequested stale data. This is
similar to the sideband stale data propagator.
Vulnerabilities
===============
Device Register Partial Write (DRPW) (CVE-2022-21166)
-----------------------------------------------------
Some endpoint MMIO registers incorrectly handle writes that are smaller than
the register size. Instead of aborting the write or only copying the correct
subset of bytes (for example, 2 bytes for a 2-byte write), more bytes than
specified by the write transaction may be written to the register. On
processors affected by FBSDP, this may expose stale data from the fill buffers
of the core that created the write transaction.
Shared Buffers Data Sampling (SBDS) (CVE-2022-21125)
----------------------------------------------------
After propagators may have moved data around the uncore and copied stale data
into client core fill buffers, processors affected by MFBDS can leak data from
the fill buffer. It is limited to the client (including Intel Xeon server E3)
uncore implementation.
Shared Buffers Data Read (SBDR) (CVE-2022-21123)
------------------------------------------------
It is similar to Shared Buffer Data Sampling (SBDS) except that the data is
directly read into the architectural software-visible state. It is limited to
the client (including Intel Xeon server E3) uncore implementation.
Affected Processors
===================
Not all the CPUs are affected by all the variants. For instance, most
processors for the server market (excluding Intel Xeon E3 processors) are
impacted by only Device Register Partial Write (DRPW).
Below is the list of affected Intel processors [#f1]_:
=================== ============ =========
Common name Family_Model Steppings
=================== ============ =========
HASWELL_X 06_3FH 2,4
SKYLAKE_L 06_4EH 3
BROADWELL_X 06_4FH All
SKYLAKE_X 06_55H 3,4,6,7,11
BROADWELL_D 06_56H 3,4,5
SKYLAKE 06_5EH 3
ICELAKE_X 06_6AH 4,5,6
ICELAKE_D 06_6CH 1
ICELAKE_L 06_7EH 5
ATOM_TREMONT_D 06_86H All
LAKEFIELD 06_8AH 1
KABYLAKE_L 06_8EH 9 to 12
ATOM_TREMONT 06_96H 1
ATOM_TREMONT_L 06_9CH 0
KABYLAKE 06_9EH 9 to 13
COMETLAKE 06_A5H 2,3,5
COMETLAKE_L 06_A6H 0,1
ROCKETLAKE 06_A7H 1
=================== ============ =========
If a CPU is in the affected processor list, but not affected by a variant, it
is indicated by new bits in MSR IA32_ARCH_CAPABILITIES. As described in a later
section, mitigation largely remains the same for all the variants, i.e. to
clear the CPU fill buffers via VERW instruction.
New bits in MSRs
================
Newer processors and microcode update on existing affected processors added new
bits to IA32_ARCH_CAPABILITIES MSR. These bits can be used to enumerate
specific variants of Processor MMIO Stale Data vulnerabilities and mitigation
capability.
MSR IA32_ARCH_CAPABILITIES
--------------------------
Bit 13 - SBDR_SSDP_NO - When set, processor is not affected by either the
Shared Buffers Data Read (SBDR) vulnerability or the sideband stale
data propagator (SSDP).
Bit 14 - FBSDP_NO - When set, processor is not affected by the Fill Buffer
Stale Data Propagator (FBSDP).
Bit 15 - PSDP_NO - When set, processor is not affected by Primary Stale Data
Propagator (PSDP).
Bit 17 - FB_CLEAR - When set, VERW instruction will overwrite CPU fill buffer
values as part of MD_CLEAR operations. Processors that do not
enumerate MDS_NO (meaning they are affected by MDS) but that do
enumerate support for both L1D_FLUSH and MD_CLEAR implicitly enumerate
FB_CLEAR as part of their MD_CLEAR support.
Bit 18 - FB_CLEAR_CTRL - Processor supports read and write to MSR
IA32_MCU_OPT_CTRL[FB_CLEAR_DIS]. On such processors, the FB_CLEAR_DIS
bit can be set to cause the VERW instruction to not perform the
FB_CLEAR action. Not all processors that support FB_CLEAR will support
FB_CLEAR_CTRL.
MSR IA32_MCU_OPT_CTRL
---------------------
Bit 3 - FB_CLEAR_DIS - When set, VERW instruction does not perform the FB_CLEAR
action. This may be useful to reduce the performance impact of FB_CLEAR in
cases where system software deems it warranted (for example, when performance
is more critical, or the untrusted software has no MMIO access). Note that
FB_CLEAR_DIS has no impact on enumeration (for example, it does not change
FB_CLEAR or MD_CLEAR enumeration) and it may not be supported on all processors
that enumerate FB_CLEAR.
Mitigation
==========
Like MDS, all variants of Processor MMIO Stale Data vulnerabilities have the
same mitigation strategy to force the CPU to clear the affected buffers before
an attacker can extract the secrets.
This is achieved by using the otherwise unused and obsolete VERW instruction in
combination with a microcode update. The microcode clears the affected CPU
buffers when the VERW instruction is executed.
Kernel reuses the MDS function to invoke the buffer clearing:
mds_clear_cpu_buffers()
On MDS affected CPUs, the kernel already invokes CPU buffer clear on
kernel/userspace, hypervisor/guest and C-state (idle) transitions. No
additional mitigation is needed on such CPUs.
For CPUs not affected by MDS or TAA, mitigation is needed only for the attacker
with MMIO capability. Therefore, VERW is not required for kernel/userspace. For
virtualization case, VERW is only needed at VMENTER for a guest with MMIO
capability.
Mitigation points
-----------------
Return to user space
^^^^^^^^^^^^^^^^^^^^
Same mitigation as MDS when affected by MDS/TAA, otherwise no mitigation
needed.
C-State transition
^^^^^^^^^^^^^^^^^^
Control register writes by CPU during C-state transition can propagate data
from fill buffer to uncore buffers. Execute VERW before C-state transition to
clear CPU fill buffers.
Guest entry point
^^^^^^^^^^^^^^^^^
Same mitigation as MDS when processor is also affected by MDS/TAA, otherwise
execute VERW at VMENTER only for MMIO capable guests. On CPUs not affected by
MDS/TAA, guest without MMIO access cannot extract secrets using Processor MMIO
Stale Data vulnerabilities, so there is no need to execute VERW for such guests.
Mitigation control on the kernel command line
---------------------------------------------
The kernel command line allows to control the Processor MMIO Stale Data
mitigations at boot time with the option "mmio_stale_data=". The valid
arguments for this option are:
========== =================================================================
full If the CPU is vulnerable, enable mitigation; CPU buffer clearing
on exit to userspace and when entering a VM. Idle transitions are
protected as well. It does not automatically disable SMT.
full,nosmt Same as full, with SMT disabled on vulnerable CPUs. This is the
complete mitigation.
off Disables mitigation completely.
========== =================================================================
If the CPU is affected and mmio_stale_data=off is not supplied on the kernel
command line, then the kernel selects the appropriate mitigation.
Mitigation status information
-----------------------------
The Linux kernel provides a sysfs interface to enumerate the current
vulnerability status of the system: whether the system is vulnerable, and
which mitigations are active. The relevant sysfs file is:
/sys/devices/system/cpu/vulnerabilities/mmio_stale_data
The possible values in this file are:
.. list-table::
* - 'Not affected'
- The processor is not vulnerable
* - 'Vulnerable'
- The processor is vulnerable, but no mitigation enabled
* - 'Vulnerable: Clear CPU buffers attempted, no microcode'
- The processor is vulnerable, but microcode is not updated. The
mitigation is enabled on a best effort basis.
* - 'Mitigation: Clear CPU buffers'
- The processor is vulnerable and the CPU buffer clearing mitigation is
enabled.
If the processor is vulnerable then the following information is appended to
the above information:
======================== ===========================================
'SMT vulnerable' SMT is enabled
'SMT disabled' SMT is disabled
'SMT Host state unknown' Kernel runs in a VM, Host SMT state unknown
======================== ===========================================
References
----------
.. [#f1] Affected Processors
https://www.intel.com/content/www/us/en/developer/topic-technology/software-security-guidance/processors-affected-consolidated-product-cpu-model.html

37
Documentation/admin-guide/kernel-parameters.txt
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@ -2469,7 +2469,6 @@
protected: nVHE-based mode with support for guests whose
state is kept private from the host.
Not valid if the kernel is running in EL2.
Defaults to VHE/nVHE based on hardware support. Setting
mode to "protected" will disable kexec and hibernation
@ -3176,6 +3175,7 @@
srbds=off [X86,INTEL]
no_entry_flush [PPC]
no_uaccess_flush [PPC]
mmio_stale_data=off [X86]
Exceptions:
This does not have any effect on
@ -3197,6 +3197,7 @@
Equivalent to: l1tf=flush,nosmt [X86]
mds=full,nosmt [X86]
tsx_async_abort=full,nosmt [X86]
mmio_stale_data=full,nosmt [X86]
mminit_loglevel=
[KNL] When CONFIG_DEBUG_MEMORY_INIT is set, this
@ -3206,6 +3207,40 @@
log everything. Information is printed at KERN_DEBUG
so loglevel=8 may also need to be specified.
mmio_stale_data=
[X86,INTEL] Control mitigation for the Processor
MMIO Stale Data vulnerabilities.
Processor MMIO Stale Data is a class of
vulnerabilities that may expose data after an MMIO
operation. Exposed data could originate or end in
the same CPU buffers as affected by MDS and TAA.
Therefore, similar to MDS and TAA, the mitigation
is to clear the affected CPU buffers.
This parameter controls the mitigation. The
options are:
full - Enable mitigation on vulnerable CPUs
full,nosmt - Enable mitigation and disable SMT on
vulnerable CPUs.
off - Unconditionally disable mitigation
On MDS or TAA affected machines,
mmio_stale_data=off can be prevented by an active
MDS or TAA mitigation as these vulnerabilities are
mitigated with the same mechanism so in order to
disable this mitigation, you need to specify
mds=off and tsx_async_abort=off too.
Not specifying this option is equivalent to
mmio_stale_data=full.
For details see:
Documentation/admin-guide/hw-vuln/processor_mmio_stale_data.rst
module.sig_enforce
[KNL] When CONFIG_MODULE_SIG is set, this means that
modules without (valid) signatures will fail to load.

2
Documentation/arm/tcm.rst
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@ -34,7 +34,7 @@ CPU so it is usually wise not to overlap any physical RAM with
the TCM.
The TCM memory can then be remapped to another address again using
the MMU, but notice that the TCM if often used in situations where
the MMU, but notice that the TCM is often used in situations where
the MMU is turned off. To avoid confusion the current Linux
implementation will map the TCM 1 to 1 from physical to virtual
memory in the location specified by the kernel. Currently Linux

2
Documentation/arm64/sme.rst
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@ -371,7 +371,7 @@ The regset data starts with struct user_za_header, containing:
Appendix A. SME programmer's model (informative)
=================================================
This section provides a minimal description of the additions made by SVE to the
This section provides a minimal description of the additions made by SME to the
ARMv8-A programmer's model that are relevant to this document.
Note: This section is for information only and not intended to be complete or

2
Documentation/devicetree/bindings/clock/idt,versaclock5.yaml
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@ -45,7 +45,7 @@ description: |
The case where SH and SP are both 1 is likely not very interesting.
maintainers:
- Luca Ceresoli <luca@lucaceresoli.net>
- Luca Ceresoli <luca.ceresoli@bootlin.com>
properties:
compatible:

2
Documentation/devicetree/bindings/cpufreq/brcm,stb-avs-cpu-freq.txt
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@ -16,7 +16,7 @@ has been processed. See [2] for more information on the brcm,l2-intc node.
firmware. On some SoCs, this firmware supports DFS and DVFS in addition to
Adaptive Voltage Scaling.
[2] Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt
[2] Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.yaml
Node brcm,avs-cpu-data-mem

7
Documentation/devicetree/bindings/display/arm,malidp.yaml
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@ -71,11 +71,6 @@ properties:
- description: number of output lines for the green channel (G)
- description: number of output lines for the blue channel (B)
arm,malidp-arqos-high-level:
$ref: /schemas/types.yaml#/definitions/uint32
description:
integer describing the ARQoS levels of DP500's QoS signaling
arm,malidp-arqos-value:
$ref: /schemas/types.yaml#/definitions/uint32
description:
@ -113,7 +108,7 @@ examples:
clocks = <&oscclk2>, <&fpgaosc0>, <&fpgaosc1>, <&fpgaosc1>;
clock-names = "pxlclk", "mclk", "aclk", "pclk";
arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
arm,malidp-arqos-high-level = <0xd000d000>;
arm,malidp-arqos-value = <0xd000d000>;
port {
dp0_output: endpoint {

2
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display DPU dt properties for SC7180 target
maintainers:
- Krishna Manikandan <mkrishn@codeaurora.org>
- Krishna Manikandan <quic_mkrishn@quicinc.com>
description: |
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates

2
Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display DPU dt properties for SC7280
maintainers:
- Krishna Manikandan <mkrishn@codeaurora.org>
- Krishna Manikandan <quic_mkrishn@quicinc.com>
description: |
Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates

2
Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display DPU dt properties for SDM845 target
maintainers:
- Krishna Manikandan <mkrishn@codeaurora.org>
- Krishna Manikandan <quic_mkrishn@quicinc.com>
description: |
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates

2
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display DSI controller
maintainers:
- Krishna Manikandan <mkrishn@codeaurora.org>
- Krishna Manikandan <quic_mkrishn@quicinc.com>
allOf:
- $ref: "../dsi-controller.yaml#"

2
Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display DSI 10nm PHY
maintainers:
- Krishna Manikandan <mkrishn@codeaurora.org>
- Krishna Manikandan <quic_mkrishn@quicinc.com>
allOf:
- $ref: dsi-phy-common.yaml#

2
Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display DSI 14nm PHY
maintainers:
- Krishna Manikandan <mkrishn@codeaurora.org>
- Krishna Manikandan <quic_mkrishn@quicinc.com>
allOf:
- $ref: dsi-phy-common.yaml#

2
Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display DSI 20nm PHY
maintainers:
- Krishna Manikandan <mkrishn@codeaurora.org>
- Krishna Manikandan <quic_mkrishn@quicinc.com>
allOf:
- $ref: dsi-phy-common.yaml#

2
Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display DSI 28nm PHY
maintainers:
- Krishna Manikandan <mkrishn@codeaurora.org>
- Krishna Manikandan <quic_mkrishn@quicinc.com>
allOf:
- $ref: dsi-phy-common.yaml#

2
Documentation/devicetree/bindings/display/msm/dsi-phy-common.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Description of Qualcomm Display DSI PHY common dt properties
maintainers:
- Krishna Manikandan <mkrishn@codeaurora.org>
- Krishna Manikandan <quic_mkrishn@quicinc.com>
description: |
This defines the DSI PHY dt properties which are common for all

5
Documentation/devicetree/bindings/hwmon/ti,tmp401.yaml
View File

@ -40,9 +40,8 @@ properties:
value to be used for converting remote channel measurements to
temperature.
$ref: /schemas/types.yaml#/definitions/int32
items:
minimum: -128
maximum: 127
minimum: -128
maximum: 127
ti,beta-compensation:
description:

2
Documentation/devicetree/bindings/hwmon/vexpress.txt
View File

@ -9,7 +9,7 @@ Requires node properties:
"arm,vexpress-power"
"arm,vexpress-energy"
- "arm,vexpress-sysreg,func" when controlled via vexpress-sysreg
(see Documentation/devicetree/bindings/arm/vexpress-sysreg.txt
(see Documentation/devicetree/bindings/arm/vexpress-config.yaml
for more details)
Optional node properties:

1
Documentation/devicetree/bindings/interrupt-controller/socionext,uniphier-aidet.yaml
View File

@ -30,6 +30,7 @@ properties:
- socionext,uniphier-ld11-aidet
- socionext,uniphier-ld20-aidet
- socionext,uniphier-pxs3-aidet
- socionext,uniphier-nx1-aidet
reg:
maxItems: 1

39
Documentation/devicetree/bindings/iommu/xen,grant-dma.yaml Normal file
View File

@ -0,0 +1,39 @@
# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iommu/xen,grant-dma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xen specific IOMMU for virtualized devices (e.g. virtio)
maintainers:
- Stefano Stabellini <sstabellini@kernel.org>
description:
The Xen IOMMU represents the Xen grant table interface. Grant mappings
are to be used with devices connected to the Xen IOMMU using the "iommus"
property, which also specifies the ID of the backend domain.
The binding is required to restrict memory access using Xen grant mappings.
properties:
compatible:
const: xen,grant-dma
'#iommu-cells':
const: 1
description:
The single cell is the domid (domain ID) of the domain where the backend
is running.
required:
- compatible
- "#iommu-cells"
additionalProperties: false
examples:
- |
iommu {
compatible = "xen,grant-dma";
#iommu-cells = <1>;
};

3
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
View File

@ -150,7 +150,6 @@ allOf:
description: 5 memory controller channels and 1 for stream-id registers
reg-names:
maxItems: 6
items:
- const: sid
- const: broadcast
@ -170,7 +169,6 @@ allOf:
description: 17 memory controller channels and 1 for stream-id registers
reg-names:
minItems: 18
items:
- const: sid
- const: broadcast
@ -202,7 +200,6 @@ allOf:
description: 17 memory controller channels and 1 for stream-id registers
reg-names:
minItems: 18
items:
- const: sid
- const: broadcast

2
Documentation/devicetree/bindings/mfd/maxim,max77714.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: MAX77714 PMIC with GPIO, RTC and watchdog from Maxim Integrated.
maintainers:
- Luca Ceresoli <luca@lucaceresoli.net>
- Luca Ceresoli <luca.ceresoli@bootlin.com>
description: |
MAX77714 is a Power Management IC with 4 buck regulators, 9

2
Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml
View File

@ -75,7 +75,6 @@ examples:
sd-uhs-sdr104;
sdhci,auto-cmd12;
interrupts = <0x0 0x26 0x4>;
interrupt-names = "sdio0_0";
clocks = <&scmi_clk 245>;
clock-names = "sw_sdio";
};
@ -94,7 +93,6 @@ examples:
non-removable;
bus-width = <0x8>;
interrupts = <0x0 0x27 0x4>;
interrupt-names = "sdio1_0";
clocks = <&scmi_clk 245>;
clock-names = "sw_sdio";
};

4
Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml
View File

@ -56,6 +56,9 @@ properties:
- const: core
- const: axi
interrupts:
maxItems: 1
marvell,xenon-sdhc-id:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
@ -145,7 +148,6 @@ allOf:
items:
- description: Xenon IP registers
- description: Armada 3700 SoC PHY PAD Voltage Control register
minItems: 2
marvell,pad-type:
$ref: /schemas/types.yaml#/definitions/string

1
Documentation/devicetree/bindings/nvme/apple,nvme-ans.yaml
View File

@ -55,7 +55,6 @@ properties:
maxItems: 1
apple,sart:
maxItems: 1
$ref: /schemas/types.yaml#/definitions/phandle
description: |
Reference to the SART address filter.

2
Documentation/devicetree/bindings/phy/phy-stih407-usb.txt
View File

@ -9,7 +9,7 @@ Required properties:
- resets : list of phandle and reset specifier pairs. There should be two entries, one
for the whole phy and one for the port
- reset-names : list of reset signal names. Should be "global" and "port"
See: Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
See: Documentation/devicetree/bindings/reset/st,stih407-powerdown.yaml
See: Documentation/devicetree/bindings/reset/reset.txt
Example:

2
Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
View File

@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Qualcomm QMP USB3 DP PHY controller
maintainers:
- Manu Gautam <mgautam@codeaurora.org>
- Wesley Cheng <quic_wcheng@quicinc.com>
properties:
compatible:

2
Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
View File

@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Qualcomm QUSB2 phy controller
maintainers:
- Manu Gautam <mgautam@codeaurora.org>
- Wesley Cheng <quic_wcheng@quicinc.com>
description:
QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.

2
Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml
View File

@ -7,7 +7,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Qualcomm Synopsys Femto High-Speed USB PHY V2
maintainers:
- Wesley Cheng <wcheng@codeaurora.org>
- Wesley Cheng <quic_wcheng@quicinc.com>
description: |
Qualcomm High-Speed USB PHY

2
Documentation/devicetree/bindings/pinctrl/pinctrl-rk805.txt
View File

@ -27,7 +27,7 @@ Required properties:
- pins: List of pins. Valid values of pins properties are: gpio0, gpio1.
First 2 properties must be added in the RK805 PMIC node, documented in
Documentation/devicetree/bindings/mfd/rk808.txt
Documentation/devicetree/bindings/mfd/rockchip,rk808.yaml
Optional properties:
-------------------

26
Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml
View File

@ -32,31 +32,37 @@ patternProperties:
groups:
description: The pin group to select.
enum: [
# common
i2c, spi, wdt,
# For MT7620 SoC
ephy, i2c, mdio, nd_sd, pa, pcie, rgmii1, rgmii2, spi, spi refclk,
uartf, uartlite, wdt, wled,
ephy, mdio, nd_sd, pa, pcie, rgmii1, rgmii2, spi refclk,
uartf, uartlite, wled,
# For MT7628 and MT7688 SoCs
gpio, i2c, i2s, p0led_an, p0led_kn, p1led_an, p1led_kn, p2led_an,
gpio, i2s, p0led_an, p0led_kn, p1led_an, p1led_kn, p2led_an,
p2led_kn, p3led_an, p3led_kn, p4led_an, p4led_kn, perst, pwm0,
pwm1, refclk, sdmode, spi, spi cs1, spis, uart0, uart1, uart2,
wdt, wled_an, wled_kn,
pwm1, refclk, sdmode, spi cs1, spis, uart0, uart1, uart2,
wled_an, wled_kn,
]
function:
description: The mux function to select.
enum: [
# common
gpio, i2c, refclk, spi,
# For MT7620 SoC
ephy, gpio, gpio i2s, gpio uartf, i2c, i2s uartf, mdio, nand, pa,
pcie refclk, pcie rst, pcm gpio, pcm i2s, pcm uartf, refclk,
rgmii1, rgmii2, sd, spi, spi refclk, uartf, uartlite, wdt refclk,
ephy, gpio i2s, gpio uartf, i2s uartf, mdio, nand, pa,
pcie refclk, pcie rst, pcm gpio, pcm i2s, pcm uartf,
rgmii1, rgmii2, sd, spi refclk, uartf, uartlite, wdt refclk,
wdt rst, wled,
# For MT7628 and MT7688 SoCs
antenna, debug, gpio, i2c, i2s, jtag, p0led_an, p0led_kn,
antenna, debug, i2s, jtag, p0led_an, p0led_kn,
p1led_an, p1led_kn, p2led_an, p2led_kn, p3led_an, p3led_kn,
p4led_an, p4led_kn, pcie, pcm, perst, pwm, pwm0, pwm1, pwm_uart2,
refclk, rsvd, sdxc, sdxc d5 d4, sdxc d6, sdxc d7, spi, spi cs1,
rsvd, sdxc, sdxc d5 d4, sdxc d6, sdxc d7, spi cs1,
spis, sw_r, uart0, uart1, uart2, utif, wdt, wled_an, wled_kn, -,
]

29
Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml
View File

@ -33,32 +33,29 @@ patternProperties:
groups:
description: The pin group to select.
enum: [
# common
i2c, jtag, led, mdio, rgmii, spi, spi_cs1, uartf, uartlite,
# For RT3050, RT3052 and RT3350 SoCs
i2c, jtag, mdio, rgmii, sdram, spi, uartf, uartlite,
sdram,
# For RT3352 SoC
i2c, jtag, led, lna, mdio, pa, rgmii, spi, spi_cs1, uartf,
uartlite,
# For RT5350 SoC
i2c, jtag, led, spi, spi_cs1, uartf, uartlite,
lna, pa
]
function:
description: The mux function to select.
enum: [
# For RT3050, RT3052 and RT3350 SoCs
gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, mdio, pcm gpio,
pcm i2s, pcm uartf, rgmii, sdram, spi, uartf, uartlite,
# For RT3352 SoC
gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, led, lna, mdio,
pa, pcm gpio, pcm i2s, pcm uartf, rgmii, spi, spi_cs1, uartf,
# common
gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, led, mdio,
pcm gpio, pcm i2s, pcm uartf, rgmii, spi, spi_cs1, uartf,
uartlite, wdg_cs1,
# For RT5350 SoC
gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, led, pcm gpio,
pcm i2s, pcm uartf, spi, spi_cs1, uartf, uartlite, wdg_cs1,
# For RT3050, RT3052 and RT3350 SoCs
sdram,
# For RT3352 SoC
lna, pa
]
required:

2
Documentation/devicetree/bindings/power/supply/maxim,max77976.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Maxim Integrated MAX77976 Battery charger
maintainers:
- Luca Ceresoli <luca@lucaceresoli.net>
- Luca Ceresoli <luca.ceresoli@bootlin.com>
description: |
The Maxim MAX77976 is a 19Vin / 5.5A, 1-Cell Li+ battery charger

2
Documentation/devicetree/bindings/regulator/qcom,usb-vbus-regulator.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: The Qualcomm PMIC VBUS output regulator driver
maintainers:
- Wesley Cheng <wcheng@codeaurora.org>
- Wesley Cheng <quic_wcheng@quicinc.com>
description: |
This regulator driver controls the VBUS output by the Qualcomm PMIC. This

2
Documentation/devicetree/bindings/regulator/vexpress.txt
View File

@ -4,7 +4,7 @@ Versatile Express voltage regulators
Requires node properties:
- "compatible" value: "arm,vexpress-volt"
- "arm,vexpress-sysreg,func" when controlled via vexpress-sysreg
(see Documentation/devicetree/bindings/arm/vexpress-sysreg.txt
(see Documentation/devicetree/bindings/arm/vexpress-config.yaml
for more details)
Required regulator properties:

1
Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
View File

@ -47,6 +47,5 @@ examples:
clocks = <&clkcfg CLK_SPI0>;
interrupt-parent = <&plic>;
interrupts = <54>;
spi-max-frequency = <25000000>;
};
...

1
Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml
View File

@ -110,7 +110,6 @@ examples:
pinctrl-names = "default";
pinctrl-0 = <&qup_spi1_default>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <0>;
};

2
Documentation/devicetree/bindings/usb/dwc3-st.txt
View File

@ -13,7 +13,7 @@ Required properties:
- resets : list of phandle and reset specifier pairs. There should be two entries, one
for the powerdown and softreset lines of the usb3 IP
- reset-names : list of reset signal names. Names should be "powerdown" and "softreset"
See: Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
See: Documentation/devicetree/bindings/reset/st,stih407-powerdown.yaml
See: Documentation/devicetree/bindings/reset/reset.txt
- #address-cells, #size-cells : should be '1' if the device has sub-nodes

2
Documentation/devicetree/bindings/usb/ehci-st.txt
View File

@ -17,7 +17,7 @@ See: Documentation/devicetree/bindings/clock/clock-bindings.txt
- resets : phandle + reset specifier pairs to the powerdown and softreset lines
of the USB IP
- reset-names : should be "power" and "softreset"
See: Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
See: Documentation/devicetree/bindings/reset/st,stih407-powerdown.yaml
See: Documentation/devicetree/bindings/reset/reset.txt
Example:

3
Documentation/devicetree/bindings/usb/generic-ehci.yaml
View File

@ -136,7 +136,8 @@ properties:
Phandle of a companion.
phys:
maxItems: 1
minItems: 1
maxItems: 3
phy-names:
const: usb

3
Documentation/devicetree/bindings/usb/generic-ohci.yaml
View File

@ -103,7 +103,8 @@ properties:
Overrides the detected port count
phys:
maxItems: 1
minItems: 1
maxItems: 3
phy-names:
const: usb

2
Documentation/devicetree/bindings/usb/ohci-st.txt
View File

@ -15,7 +15,7 @@ See: Documentation/devicetree/bindings/clock/clock-bindings.txt
- resets : phandle to the powerdown and reset controller for the USB IP
- reset-names : should be "power" and "softreset".
See: Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
See: Documentation/devicetree/bindings/reset/st,stih407-powerdown.yaml
See: Documentation/devicetree/bindings/reset/reset.txt
Example:

2
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SuperSpeed DWC3 USB SoC controller
maintainers:
- Manu Gautam <mgautam@codeaurora.org>
- Wesley Cheng <quic_wcheng@quicinc.com>
properties:
compatible:

3
Documentation/devicetree/bindings/vendor-prefixes.yaml
View File

@ -143,6 +143,9 @@ patternProperties:
description: ASPEED Technology Inc.
"^asus,.*":
description: AsusTek Computer Inc.
"^atheros,.*":
description: Qualcomm Atheros, Inc. (deprecated, use qca)
deprecated: true
"^atlas,.*":
description: Atlas Scientific LLC
"^atmel,.*":

1
Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml
View File

@ -64,7 +64,6 @@ if:
then:
properties:
clocks:
minItems: 2
items:
- description: High-frequency oscillator input, divided internally
- description: Low-frequency oscillator input

2
Documentation/driver-api/gpio/board.rst
View File

@ -6,7 +6,7 @@ This document explains how GPIOs can be assigned to given devices and functions.
Note that it only applies to the new descriptor-based interface. For a
description of the deprecated integer-based GPIO interface please refer to
gpio-legacy.txt (actually, there is no real mapping possible with the old
legacy.rst (actually, there is no real mapping possible with the old
interface; you just fetch an integer from somewhere and request the
corresponding GPIO).

6
Documentation/driver-api/gpio/consumer.rst
View File

@ -4,7 +4,7 @@ GPIO Descriptor Consumer Interface
This document describes the consumer interface of the GPIO framework. Note that
it describes the new descriptor-based interface. For a description of the
deprecated integer-based GPIO interface please refer to gpio-legacy.txt.
deprecated integer-based GPIO interface please refer to legacy.rst.
Guidelines for GPIOs consumers
@ -78,7 +78,7 @@ whether the line is configured active high or active low (see
The two last flags are used for use cases where open drain is mandatory, such
as I2C: if the line is not already configured as open drain in the mappings
(see board.txt), then open drain will be enforced anyway and a warning will be
(see board.rst), then open drain will be enforced anyway and a warning will be
printed that the board configuration needs to be updated to match the use case.
Both functions return either a valid GPIO descriptor, or an error code checkable
@ -270,7 +270,7 @@ driven.
The same is applicable for open drain or open source output lines: those do not
actively drive their output high (open drain) or low (open source), they just
switch their output to a high impedance value. The consumer should not need to
care. (For details read about open drain in driver.txt.)
care. (For details read about open drain in driver.rst.)
With this, all the gpiod_set_(array)_value_xxx() functions interpret the
parameter "value" as "asserted" ("1") or "de-asserted" ("0"). The physical line

6
Documentation/driver-api/gpio/intro.rst
View File

@ -14,12 +14,12 @@ Due to the history of GPIO interfaces in the kernel, there are two different
ways to obtain and use GPIOs:
- The descriptor-based interface is the preferred way to manipulate GPIOs,
and is described by all the files in this directory excepted gpio-legacy.txt.
and is described by all the files in this directory excepted legacy.rst.
- The legacy integer-based interface which is considered deprecated (but still
usable for compatibility reasons) is documented in gpio-legacy.txt.
usable for compatibility reasons) is documented in legacy.rst.
The remainder of this document applies to the new descriptor-based interface.
gpio-legacy.txt contains the same information applied to the legacy
legacy.rst contains the same information applied to the legacy
integer-based interface.

0
Documentation/hte/hte.rst → Documentation/driver-api/hte/hte.rst
View File

0
Documentation/hte/index.rst → Documentation/driver-api/hte/index.rst
View File

0
Documentation/hte/tegra194-hte.rst → Documentation/driver-api/hte/tegra194-hte.rst
View File

1
Documentation/driver-api/index.rst
View File

@ -108,6 +108,7 @@ available subsections can be seen below.
xilinx/index
xillybus
zorro
hte/index
.. only:: subproject and html

1
Documentation/features/core/cBPF-JIT/arch-support.txt
View File

@ -13,6 +13,7 @@
| csky: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
| loong: | TODO |
| m68k: | TODO |
| microblaze: | TODO |
| mips: | ok |

1
Documentation/features/core/eBPF-JIT/arch-support.txt
View File

@ -13,6 +13,7 @@
| csky: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
| loong: | TODO |
| m68k: | TODO |
| microblaze: | TODO |
| mips: | ok |

1
Documentation/features/core/generic-idle-thread/arch-support.txt
View File

@ -13,6 +13,7 @@
| csky: | ok |
| hexagon: | ok |
| ia64: | ok |
| loong: | ok |
| m68k: | TODO |
| microblaze: | TODO |
| mips: | ok |

1
Documentation/features/core/jump-labels/arch-support.txt
View File

@ -13,6 +13,7 @@
| csky: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
| loong: | TODO |
| m68k: | TODO |
| microblaze: | TODO |
| mips: | ok |

1
Documentation/features/core/thread-info-in-task/arch-support.txt
View File

@ -13,6 +13,7 @@
| csky: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
| loong: | TODO |
| m68k: | TODO |
| microblaze: | TODO |
| mips: | TODO |

1
Documentation/features/core/tracehook/arch-support.txt
View File

@ -13,6 +13,7 @@
| csky: | ok |
| hexagon: | ok |
| ia64: | ok |
| loong: | ok |
| m68k: | TODO |
| microblaze: | TODO |
| mips: | ok |

1
Documentation/features/debug/KASAN/arch-support.txt
View File

@ -13,6 +13,7 @@
| csky: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
| loong: | TODO |
| m68k: | TODO |
| microblaze: | TODO |
| mips: | TODO |

3
Documentation/features/debug/debug-vm-pgtable/arch-support.txt
View File

@ -13,12 +13,13 @@
| csky: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
| loong: | TODO |
| m68k: | TODO |
| microblaze: | TODO |
| mips: | TODO |
| nios2: | TODO |
| openrisc: | TODO |
| parisc: | TODO |
| parisc: | ok |
| powerpc: | ok |
| riscv: | ok |
| s390: | ok |

3
Documentation/features/debug/gcov-profile-all/arch-support.txt
View File

@ -13,6 +13,7 @@
| csky: | ok |
| hexagon: | TODO |
| ia64: | TODO |
| loong: | TODO |
| m68k: | TODO |
| microblaze: | ok |
| mips: | ok |
@ -24,7 +25,7 @@
| s390: | ok |
| sh: | ok |
| sparc: | TODO |
| um: | TODO |
| um: | ok |
| x86: | ok |
| xtensa: | TODO |
-----------------------

1
Documentation/features/debug/kcov/arch-support.txt
View File

@ -13,6 +13,7 @@
| csky: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
| loong: | TODO |
| m68k: | TODO |
| microblaze: | TODO |
| mips: | ok |

1
Documentation/features/debug/kgdb/arch-support.txt
View File

@ -13,6 +13,7 @@
| csky: | TODO |
| hexagon: | ok |
| ia64: | TODO |
| loong: | TODO |
| m68k: | TODO |
| microblaze: | ok |
| mips: | ok |

1
Documentation/features/debug/kmemleak/arch-support.txt
View File

@ -13,6 +13,7 @@
| csky: | ok |
| hexagon: | TODO |
| ia64: | TODO |
| loong: | TODO |
| m68k: | TODO |
| microblaze: | ok |
| mips: | ok |

1
Documentation/features/debug/kprobes-on-ftrace/arch-support.txt
View File

@ -13,6 +13,7 @@
| csky: | ok |
| hexagon: | TODO |
| ia64: | TODO |
| loong: | TODO |
| m68k: | TODO |
| microblaze: | TODO |
| mips: | TODO |

1
Documentation/features/debug/kprobes/arch-support.txt
View File

@ -13,6 +13,7 @@
| csky: | ok |
| hexagon: | TODO |
| ia64: | ok |
| loong: | TODO |
| m68k: | TODO |
| microblaze: | TODO |
| mips: | ok |

1
Documentation/features/debug/kretprobes/arch-support.txt
View File

@ -13,6 +13,7 @@
| csky: | ok |
| hexagon: | TODO |
| ia64: | ok |
| loong: | TODO |
| m68k: | TODO |
| microblaze: | TODO |
| mips: | ok |

1
Documentation/features/debug/optprobes/arch-support.txt
View File

@ -13,6 +13,7 @@
| csky: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
| loong: | TODO |
| m68k: | TODO |
| microblaze: | TODO |
| mips: | TODO |

1
Documentation/features/debug/stackprotector/arch-support.txt
View File

@ -13,6 +13,7 @@
| csky: | ok |
| hexagon: | TODO |
| ia64: | TODO |
| loong: | TODO |
| m68k: | TODO |
| microblaze: | TODO |
| mips: | ok |

1
Documentation/features/debug/uprobes/arch-support.txt
View File

@ -13,6 +13,7 @@
| csky: | ok |
| hexagon: | TODO |
| ia64: | TODO |
| loong: | TODO |
| m68k: | TODO |
| microblaze: | TODO |
| mips: | ok |

1
Documentation/features/debug/user-ret-profiler/arch-support.txt
View File

@ -13,6 +13,7 @@
| csky: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
| loong: | TODO |
| m68k: | TODO |
| microblaze: | TODO |
| mips: | TODO |

1
Documentation/features/io/dma-contiguous/arch-support.txt
View File

@ -13,6 +13,7 @@
| csky: | ok |
| hexagon: | TODO |
| ia64: | TODO |
| loong: | ok |
| m68k: | TODO |
| microblaze: | ok |
| mips: | ok |

1
Documentation/features/locking/cmpxchg-local/arch-support.txt
View File

@ -13,6 +13,7 @@
| csky: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
| loong: | TODO |
| m68k: | TODO |
| microblaze: | TODO |
| mips: | TODO |

1
Documentation/features/locking/lockdep/arch-support.txt
View File

@ -13,6 +13,7 @@
| csky: | ok |
| hexagon: | ok |
| ia64: | TODO |
| loong: | ok |
| m68k: | TODO |
| microblaze: | ok |
| mips: | ok |

3
Documentation/features/locking/queued-rwlocks/arch-support.txt
View File

@ -13,6 +13,7 @@
| csky: | ok |
| hexagon: | TODO |
| ia64: | TODO |
| loong: | ok |
| m68k: | TODO |
| microblaze: | TODO |
| mips: | ok |
@ -20,7 +21,7 @@
| openrisc: | ok |
| parisc: | TODO |
| powerpc: | ok |
| riscv: | TODO |
| riscv: | ok |
| s390: | TODO |
| sh: | TODO |
| sparc: | ok |

1
Documentation/features/locking/queued-spinlocks/arch-support.txt
View File

@ -13,6 +13,7 @@
| csky: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
| loong: | TODO |
| m68k: | TODO |
| microblaze: | TODO |
| mips: | ok |

3
Documentation/features/perf/kprobes-event/arch-support.txt
View File

@ -7,12 +7,13 @@
| arch |status|
-----------------------
| alpha: | TODO |
| arc: | TODO |
| arc: | ok |
| arm: | ok |
| arm64: | ok |
| csky: | ok |
| hexagon: | ok |
| ia64: | TODO |
| loong: | ok |
| m68k: | TODO |
| microblaze: | TODO |
| mips: | ok |

1
Documentation/features/perf/perf-regs/arch-support.txt
View File

@ -13,6 +13,7 @@
| csky: | ok |
| hexagon: | TODO |
| ia64: | TODO |
| loong: | TODO |
| m68k: | TODO |
| microblaze: | TODO |
| mips: | ok |

1
Documentation/features/perf/perf-stackdump/arch-support.txt
View File

@ -13,6 +13,7 @@
| csky: | ok |
| hexagon: | TODO |
| ia64: | TODO |
| loong: | TODO |
| m68k: | TODO |
| microblaze: | TODO |
| mips: | ok |

1
Documentation/features/sched/membarrier-sync-core/arch-support.txt
View File

@ -36,6 +36,7 @@
| csky: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
| loong: | TODO |
| m68k: | TODO |
| microblaze: | TODO |
| mips: | TODO |

1
Documentation/features/sched/numa-balancing/arch-support.txt
View File

@ -13,6 +13,7 @@
| csky: | .. |
| hexagon: | .. |
| ia64: | TODO |
| loong: | ok |
| m68k: | .. |
| microblaze: | .. |
| mips: | TODO |

1
Documentation/features/seccomp/seccomp-filter/arch-support.txt
View File

@ -13,6 +13,7 @@
| csky: | ok |
| hexagon: | TODO |
| ia64: | TODO |
| loong: | ok |
| m68k: | TODO |
| microblaze: | TODO |
| mips: | ok |

1
Documentation/features/time/arch-tick-broadcast/arch-support.txt
View File

@ -13,6 +13,7 @@
| csky: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
| loong: | ok |
| m68k: | TODO |
| microblaze: | TODO |
| mips: | ok |

1
Documentation/features/time/clockevents/arch-support.txt
View File

@ -13,6 +13,7 @@
| csky: | ok |
| hexagon: | ok |
| ia64: | TODO |
| loong: | ok |
| m68k: | TODO |
| microblaze: | ok |
| mips: | ok |

1
Documentation/features/time/context-tracking/arch-support.txt
View File

@ -13,6 +13,7 @@
| csky: | ok |
| hexagon: | TODO |
| ia64: | TODO |
| loong: | ok |
| m68k: | TODO |
| microblaze: | TODO |
| mips: | ok |

1
Documentation/features/time/irq-time-acct/arch-support.txt
View File

@ -13,6 +13,7 @@
| csky: | TODO |
| hexagon: | TODO |
| ia64: | .. |
| loong: | ok |
| m68k: | TODO |
| microblaze: | TODO |
| mips: | ok |

1
Documentation/features/time/virt-cpuacct/arch-support.txt
View File

@ -13,6 +13,7 @@
| csky: | ok |
| hexagon: | TODO |
| ia64: | ok |
| loong: | ok |
| m68k: | TODO |
| microblaze: | TODO |
| mips: | ok |

1
Documentation/features/vm/ELF-ASLR/arch-support.txt
View File

@ -13,6 +13,7 @@
| csky: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
| loong: | TODO |
| m68k: | TODO |
| microblaze: | TODO |
| mips: | ok |

1
Documentation/features/vm/PG_uncached/arch-support.txt
View File

@ -13,6 +13,7 @@
| csky: | TODO |
| hexagon: | TODO |
| ia64: | ok |
| loong: | TODO |
| m68k: | TODO |
| microblaze: | TODO |
| mips: | TODO |

1
Documentation/features/vm/THP/arch-support.txt
View File

@ -13,6 +13,7 @@
| csky: | .. |
| hexagon: | .. |
| ia64: | TODO |
| loong: | ok |
| m68k: | .. |
| microblaze: | .. |
| mips: | ok |

1
Documentation/features/vm/TLB/arch-support.txt
View File

@ -13,6 +13,7 @@
| csky: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
| loong: | TODO |
| m68k: | .. |
| microblaze: | .. |
| mips: | TODO |

1
Documentation/features/vm/huge-vmap/arch-support.txt
View File

@ -13,6 +13,7 @@
| csky: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
| loong: | TODO |
| m68k: | TODO |
| microblaze: | TODO |
| mips: | TODO |

1
Documentation/features/vm/ioremap_prot/arch-support.txt
View File

@ -13,6 +13,7 @@
| csky: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
| loong: | ok |
| m68k: | TODO |
| microblaze: | TODO |
| mips: | ok |

3
Documentation/features/vm/pte_special/arch-support.txt
View File

@ -13,12 +13,13 @@
| csky: | TODO |
| hexagon: | TODO |
| ia64: | TODO |
| loong: | ok |
| m68k: | TODO |
| microblaze: | TODO |
| mips: | ok |
| nios2: | TODO |
| openrisc: | TODO |
| parisc: | TODO |
| parisc: | ok |
| powerpc: | ok |
| riscv: | ok |
| s390: | ok |

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