mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
synced 2025-01-15 13:15:57 +00:00
Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc.git
This commit is contained in:
Stephen Rothwell
commit
99d3fb26b3
@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Qualcomm crypto engine driver
|
||||
|
||||
maintainers:
|
||||
- Bhupesh Sharma <bhupesh.sharma@linaro.org>
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Konrad Dybcio <konradybcio@kernel.org>
|
||||
|
||||
description:
|
||||
This document defines the binding for the QCE crypto
|
||||
|
||||
@ -1,54 +0,0 @@
|
||||
* Amlogic Meson6, Meson8 and Meson8b SDIO/MMC controller
|
||||
|
||||
The highspeed MMC host controller on Amlogic SoCs provides an interface
|
||||
for MMC, SD, SDIO and SDHC types of memory cards.
|
||||
|
||||
Supported maximum speeds are the ones of the eMMC standard 4.41 as well
|
||||
as the speed of SD standard 2.0.
|
||||
|
||||
The hardware provides an internal "mux" which allows up to three slots
|
||||
to be controlled. Only one slot can be accessed at a time.
|
||||
|
||||
Required properties:
|
||||
- compatible : must be one of
|
||||
- "amlogic,meson8-sdio"
|
||||
- "amlogic,meson8b-sdio"
|
||||
along with the generic "amlogic,meson-mx-sdio"
|
||||
- reg : mmc controller base registers
|
||||
- interrupts : mmc controller interrupt
|
||||
- #address-cells : must be 1
|
||||
- size-cells : must be 0
|
||||
- clocks : phandle to clock providers
|
||||
- clock-names : must contain "core" and "clkin"
|
||||
|
||||
Required child nodes:
|
||||
A node for each slot provided by the MMC controller is required.
|
||||
NOTE: due to a driver limitation currently only one slot (= child node)
|
||||
is supported!
|
||||
|
||||
Required properties on each child node (= slot):
|
||||
- compatible : must be "mmc-slot" (see mmc.txt within this directory)
|
||||
- reg : the slot (or "port") ID
|
||||
|
||||
Optional properties on each child node (= slot):
|
||||
- bus-width : must be 1 or 4 (8-bit bus is not supported)
|
||||
- for cd and all other additional generic mmc parameters
|
||||
please refer to mmc.txt within this directory
|
||||
|
||||
Examples:
|
||||
mmc@c1108c20 {
|
||||
compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio";
|
||||
reg = <0xc1108c20 0x20>;
|
||||
interrupts = <0 28 1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
|
||||
clock-names = "core", "clkin";
|
||||
|
||||
slot@1 {
|
||||
compatible = "mmc-slot";
|
||||
reg = <1>;
|
||||
|
||||
bus-width = <4>;
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,94 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mmc/amlogic,meson-mx-sdio.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Amlogic Meson6, Meson8 and Meson8b SDIO/MMC controller
|
||||
|
||||
description: |
|
||||
The highspeed MMC host controller on Amlogic SoCs provides an interface
|
||||
for MMC, SD, SDIO and SDHC types of memory cards.
|
||||
|
||||
Supported maximum speeds are the ones of the eMMC standard 4.41 as well
|
||||
as the speed of SD standard 2.0.
|
||||
|
||||
The hardware provides an internal "mux" which allows up to three slots
|
||||
to be controlled. Only one slot can be accessed at a time.
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- amlogic,meson8-sdio
|
||||
- amlogic,meson8b-sdio
|
||||
- const: amlogic,meson-mx-sdio
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: core
|
||||
- const: clkin
|
||||
|
||||
"#address-cells":
|
||||
const: 1
|
||||
|
||||
"#size-cells":
|
||||
const: 0
|
||||
|
||||
patternProperties:
|
||||
"slot@[0-2]$":
|
||||
$ref: mmc-slot.yaml#
|
||||
description:
|
||||
A node for each slot provided by the MMC controller
|
||||
|
||||
properties:
|
||||
reg:
|
||||
enum: [0, 1, 2]
|
||||
|
||||
bus-width:
|
||||
enum: [1, 4]
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- "#address-cells"
|
||||
- "#size-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
mmc@c1108c20 {
|
||||
compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio";
|
||||
reg = <0xc1108c20 0x20>;
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&clk_core>, <&clk_in>;
|
||||
clock-names = "core", "clkin";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
slot@1 {
|
||||
compatible = "mmc-slot";
|
||||
reg = <1>;
|
||||
bus-width = <4>;
|
||||
};
|
||||
};
|
||||
@ -22,6 +22,7 @@ properties:
|
||||
- items:
|
||||
- enum:
|
||||
- microchip,sam9x7-sdhci
|
||||
- microchip,sama7d65-sdhci
|
||||
- microchip,sama7g5-sdhci
|
||||
- const: microchip,sam9x60-sdhci
|
||||
|
||||
|
||||
@ -38,15 +38,9 @@ properties:
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
description: |
|
||||
For "marvell,armada-3700-sdhci", two register areas. The first one
|
||||
for Xenon IP register. The second one for the Armada 3700 SoC PHY PAD
|
||||
Voltage Control register. Please follow the examples with compatible
|
||||
"marvell,armada-3700-sdhci" in below.
|
||||
Please also check property marvell,pad-type in below.
|
||||
|
||||
For other compatible strings, one register area for Xenon IP.
|
||||
items:
|
||||
- description: Xenon IP registers
|
||||
- description: Armada 3700 SoC PHY PAD Voltage Control register
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
@ -61,6 +55,17 @@ properties:
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
marvell,pad-type:
|
||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
enum:
|
||||
- sd
|
||||
- fixed-1-8v
|
||||
description:
|
||||
Type of Armada 3700 SoC PHY PAD Voltage Controller register. If "sd" is
|
||||
selected, SoC PHY PAD is set as 3.3V at the beginning and is switched to
|
||||
1.8V when later in higher speed mode. If "fixed-1-8v" is selected, SoC PHY
|
||||
PAD is fixed 1.8V, such as for eMMC.
|
||||
|
||||
marvell,xenon-sdhc-id:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
@ -147,27 +152,18 @@ allOf:
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
items:
|
||||
- description: Xenon IP registers
|
||||
- description: Armada 3700 SoC PHY PAD Voltage Control register
|
||||
|
||||
marvell,pad-type:
|
||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
enum:
|
||||
- sd
|
||||
- fixed-1-8v
|
||||
description: |
|
||||
Type of Armada 3700 SoC PHY PAD Voltage Controller register.
|
||||
If "sd" is selected, SoC PHY PAD is set as 3.3V at the beginning
|
||||
and is switched to 1.8V when later in higher speed mode.
|
||||
If "fixed-1-8v" is selected, SoC PHY PAD is fixed 1.8V, such as for
|
||||
eMMC.
|
||||
Please follow the examples with compatible
|
||||
"marvell,armada-3700-sdhci" in below.
|
||||
minItems: 2
|
||||
|
||||
required:
|
||||
- marvell,pad-type
|
||||
|
||||
else:
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
marvell,pad-type: false
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
357
Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml
Normal file
357
Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml
Normal file
@ -0,0 +1,357 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mmc/mmc-controller-common.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MMC Controller & Slots Common Properties
|
||||
|
||||
maintainers:
|
||||
- Ulf Hansson <ulf.hansson@linaro.org>
|
||||
|
||||
description:
|
||||
These properties are common to multiple MMC host controllers and the
|
||||
possible slots or ports for multi-slot controllers.
|
||||
|
||||
properties:
|
||||
"#address-cells":
|
||||
const: 1
|
||||
description:
|
||||
The cell is the SDIO function number if a function subnode is used.
|
||||
|
||||
"#size-cells":
|
||||
const: 0
|
||||
|
||||
# Card Detection.
|
||||
# If none of these properties are supplied, the host native card
|
||||
# detect will be used. Only one of them should be provided.
|
||||
|
||||
broken-cd:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
There is no card detection available; polling must be used.
|
||||
|
||||
cd-gpios:
|
||||
maxItems: 1
|
||||
description:
|
||||
The card detection will be done using the GPIO provided.
|
||||
|
||||
non-removable:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
Non-removable slot (like eMMC); assume always present.
|
||||
|
||||
# *NOTE* on CD and WP polarity. To use common for all SD/MMC host
|
||||
# controllers line polarity properties, we have to fix the meaning
|
||||
# of the "normal" and "inverted" line levels. We choose to follow
|
||||
# the SDHCI standard, which specifies both those lines as "active
|
||||
# low." Therefore, using the "cd-inverted" property means, that the
|
||||
# CD line is active high, i.e. it is high, when a card is
|
||||
# inserted. Similar logic applies to the "wp-inverted" property.
|
||||
#
|
||||
# CD and WP lines can be implemented on the hardware in one of two
|
||||
# ways: as GPIOs, specified in cd-gpios and wp-gpios properties, or
|
||||
# as dedicated pins. Polarity of dedicated pins can be specified,
|
||||
# using *-inverted properties. GPIO polarity can also be specified
|
||||
# using the GPIO_ACTIVE_LOW flag. This creates an ambiguity in the
|
||||
# latter case. We choose to use the XOR logic for GPIO CD and WP
|
||||
# lines. This means, the two properties are "superimposed," for
|
||||
# example leaving the GPIO_ACTIVE_LOW flag clear and specifying the
|
||||
# respective *-inverted property property results in a
|
||||
# double-inversion and actually means the "normal" line polarity is
|
||||
# in effect.
|
||||
wp-inverted:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
The Write Protect line polarity is inverted.
|
||||
|
||||
cd-inverted:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
The CD line polarity is inverted.
|
||||
|
||||
# Other properties
|
||||
|
||||
bus-width:
|
||||
description:
|
||||
Number of data lines.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [1, 4, 8]
|
||||
default: 1
|
||||
|
||||
max-frequency:
|
||||
description: |
|
||||
Maximum operating frequency of the bus:
|
||||
- for eMMC, the maximum supported frequency is 200MHz,
|
||||
- for SD/SDIO cards the SDR104 mode has a max supported
|
||||
frequency of 208MHz,
|
||||
- some mmc host controllers do support a max frequency upto
|
||||
384MHz.
|
||||
So, lets keep the maximum supported value here.
|
||||
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 400000
|
||||
maximum: 384000000
|
||||
|
||||
disable-wp:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
When set, no physical write-protect line is present. This
|
||||
property should only be specified when the controller has a
|
||||
dedicated write-protect detection logic. If a GPIO is always used
|
||||
for the write-protect detection logic, it is sufficient to not
|
||||
specify the wp-gpios property in the absence of a write-protect
|
||||
line. Not used in combination with eMMC or SDIO.
|
||||
|
||||
wp-gpios:
|
||||
maxItems: 1
|
||||
description:
|
||||
GPIO to use for the write-protect detection.
|
||||
|
||||
cd-debounce-delay-ms:
|
||||
description:
|
||||
Set delay time before detecting card after card insert
|
||||
interrupt.
|
||||
|
||||
no-1-8-v:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
When specified, denotes that 1.8V card voltage is not supported
|
||||
on this system, even if the controller claims it.
|
||||
|
||||
cap-sd-highspeed:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
SD high-speed timing is supported.
|
||||
|
||||
cap-mmc-highspeed:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
MMC high-speed timing is supported.
|
||||
|
||||
sd-uhs-sdr12:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
SD UHS SDR12 speed is supported.
|
||||
|
||||
sd-uhs-sdr25:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
SD UHS SDR25 speed is supported.
|
||||
|
||||
sd-uhs-sdr50:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
SD UHS SDR50 speed is supported.
|
||||
|
||||
sd-uhs-sdr104:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
SD UHS SDR104 speed is supported.
|
||||
|
||||
sd-uhs-ddr50:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
SD UHS DDR50 speed is supported.
|
||||
|
||||
cap-power-off-card:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
Powering off the card is safe.
|
||||
|
||||
cap-mmc-hw-reset:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
eMMC hardware reset is supported
|
||||
|
||||
cap-sdio-irq:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
enable SDIO IRQ signalling on this interface
|
||||
|
||||
full-pwr-cycle:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
Full power cycle of the card is supported.
|
||||
|
||||
full-pwr-cycle-in-suspend:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
Full power cycle of the card in suspend is supported.
|
||||
|
||||
mmc-ddr-1_2v:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
eMMC high-speed DDR mode (1.2V I/O) is supported.
|
||||
|
||||
mmc-ddr-1_8v:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
eMMC high-speed DDR mode (1.8V I/O) is supported.
|
||||
|
||||
mmc-ddr-3_3v:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
eMMC high-speed DDR mode (3.3V I/O) is supported.
|
||||
|
||||
mmc-hs200-1_2v:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
eMMC HS200 mode (1.2V I/O) is supported.
|
||||
|
||||
mmc-hs200-1_8v:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
eMMC HS200 mode (1.8V I/O) is supported.
|
||||
|
||||
mmc-hs400-1_2v:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
eMMC HS400 mode (1.2V I/O) is supported.
|
||||
|
||||
mmc-hs400-1_8v:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
eMMC HS400 mode (1.8V I/O) is supported.
|
||||
|
||||
mmc-hs400-enhanced-strobe:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
eMMC HS400 enhanced strobe mode is supported
|
||||
|
||||
no-mmc-hs400:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
All eMMC HS400 modes are not supported.
|
||||
|
||||
dsr:
|
||||
description:
|
||||
Value the card Driver Stage Register (DSR) should be programmed
|
||||
with.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 0xffff
|
||||
|
||||
no-sdio:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
Controller is limited to send SDIO commands during
|
||||
initialization.
|
||||
|
||||
no-sd:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
Controller is limited to send SD commands during initialization.
|
||||
|
||||
no-mmc:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
Controller is limited to send MMC commands during
|
||||
initialization.
|
||||
|
||||
fixed-emmc-driver-type:
|
||||
description:
|
||||
For non-removable eMMC, enforce this driver type. The value is
|
||||
the driver type as specified in the eMMC specification (table
|
||||
206 in spec version 5.1)
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 4
|
||||
|
||||
post-power-on-delay-ms:
|
||||
description:
|
||||
It was invented for MMC pwrseq-simple which could be referred to
|
||||
mmc-pwrseq-simple.yaml. But now it\'s reused as a tunable delay
|
||||
waiting for I/O signalling and card power supply to be stable,
|
||||
regardless of whether pwrseq-simple is used. Default to 10ms if
|
||||
no available.
|
||||
default: 10
|
||||
|
||||
supports-cqe:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
The presence of this property indicates that the corresponding
|
||||
MMC host controller supports HW command queue feature.
|
||||
|
||||
disable-cqe-dcmd:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
The presence of this property indicates that the MMC
|
||||
controller\'s command queue engine (CQE) does not support direct
|
||||
commands (DCMDs).
|
||||
|
||||
keep-power-in-suspend:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
SDIO only. Preserves card power during a suspend/resume cycle.
|
||||
|
||||
wakeup-source:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
SDIO only. Enables wake up of host system on SDIO IRQ assertion.
|
||||
|
||||
vmmc-supply:
|
||||
description:
|
||||
Supply for the card power
|
||||
|
||||
vqmmc-supply:
|
||||
description:
|
||||
Supply for the bus IO line power, such as a level shifter.
|
||||
If the level shifter is controlled by a GPIO line, this shall
|
||||
be modeled as a "regulator-fixed" with a GPIO line for
|
||||
switching the level shifter on/off.
|
||||
|
||||
mmc-pwrseq:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
System-on-Chip designs may specify a specific MMC power
|
||||
sequence. To successfully detect an (e)MMC/SD/SDIO card, that
|
||||
power sequence must be maintained while initializing the card.
|
||||
|
||||
patternProperties:
|
||||
"^.*@[0-9]+$":
|
||||
type: object
|
||||
description: |
|
||||
On embedded systems the cards connected to a host may need
|
||||
additional properties. These can be specified in subnodes to the
|
||||
host controller node. The subnodes are identified by the
|
||||
standard \'reg\' property. Which information exactly can be
|
||||
specified depends on the bindings for the SDIO function driver
|
||||
for the subnode, as specified by the compatible string.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
description:
|
||||
Name of SDIO function following generic names recommended
|
||||
practice
|
||||
|
||||
reg:
|
||||
items:
|
||||
- minimum: 0
|
||||
maximum: 7
|
||||
description:
|
||||
Must contain the SDIO function number of the function this
|
||||
subnode describes. A value of 0 denotes the memory SD
|
||||
function, values from 1 to 7 denote the SDIO functions.
|
||||
|
||||
required:
|
||||
- reg
|
||||
|
||||
"^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$":
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
items:
|
||||
minimum: 0
|
||||
maximum: 359
|
||||
description:
|
||||
Set the clock (phase) delays which are to be configured in the
|
||||
controller while switching to particular speed mode. These values
|
||||
are in pair of degrees.
|
||||
|
||||
dependencies:
|
||||
cd-debounce-delay-ms: [ cd-gpios ]
|
||||
fixed-emmc-driver-type: [ non-removable ]
|
||||
|
||||
additionalProperties: true
|
||||
@ -9,7 +9,7 @@ title: MMC Controller Common Properties
|
||||
maintainers:
|
||||
- Ulf Hansson <ulf.hansson@linaro.org>
|
||||
|
||||
description: |
|
||||
description:
|
||||
These properties are common to multiple MMC host controllers. Any host
|
||||
that requires the respective functionality should implement them using
|
||||
these definitions.
|
||||
@ -18,351 +18,13 @@ description: |
|
||||
(and the corresponding mmcblkN devices) by defining an alias in the
|
||||
/aliases device tree node.
|
||||
|
||||
$ref: mmc-controller-common.yaml#
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^mmc(@.*)?$"
|
||||
|
||||
"#address-cells":
|
||||
const: 1
|
||||
description: |
|
||||
The cell is the slot ID if a function subnode is used.
|
||||
|
||||
"#size-cells":
|
||||
const: 0
|
||||
|
||||
# Card Detection.
|
||||
# If none of these properties are supplied, the host native card
|
||||
# detect will be used. Only one of them should be provided.
|
||||
|
||||
broken-cd:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
There is no card detection available; polling must be used.
|
||||
|
||||
cd-gpios:
|
||||
maxItems: 1
|
||||
description:
|
||||
The card detection will be done using the GPIO provided.
|
||||
|
||||
non-removable:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
Non-removable slot (like eMMC); assume always present.
|
||||
|
||||
# *NOTE* on CD and WP polarity. To use common for all SD/MMC host
|
||||
# controllers line polarity properties, we have to fix the meaning
|
||||
# of the "normal" and "inverted" line levels. We choose to follow
|
||||
# the SDHCI standard, which specifies both those lines as "active
|
||||
# low." Therefore, using the "cd-inverted" property means, that the
|
||||
# CD line is active high, i.e. it is high, when a card is
|
||||
# inserted. Similar logic applies to the "wp-inverted" property.
|
||||
#
|
||||
# CD and WP lines can be implemented on the hardware in one of two
|
||||
# ways: as GPIOs, specified in cd-gpios and wp-gpios properties, or
|
||||
# as dedicated pins. Polarity of dedicated pins can be specified,
|
||||
# using *-inverted properties. GPIO polarity can also be specified
|
||||
# using the GPIO_ACTIVE_LOW flag. This creates an ambiguity in the
|
||||
# latter case. We choose to use the XOR logic for GPIO CD and WP
|
||||
# lines. This means, the two properties are "superimposed," for
|
||||
# example leaving the GPIO_ACTIVE_LOW flag clear and specifying the
|
||||
# respective *-inverted property property results in a
|
||||
# double-inversion and actually means the "normal" line polarity is
|
||||
# in effect.
|
||||
wp-inverted:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
The Write Protect line polarity is inverted.
|
||||
|
||||
cd-inverted:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
The CD line polarity is inverted.
|
||||
|
||||
# Other properties
|
||||
|
||||
bus-width:
|
||||
description:
|
||||
Number of data lines.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [1, 4, 8]
|
||||
default: 1
|
||||
|
||||
max-frequency:
|
||||
description: |
|
||||
Maximum operating frequency of the bus:
|
||||
- for eMMC, the maximum supported frequency is 200MHz,
|
||||
- for SD/SDIO cards the SDR104 mode has a max supported
|
||||
frequency of 208MHz,
|
||||
- some mmc host controllers do support a max frequency upto
|
||||
384MHz.
|
||||
So, lets keep the maximum supported value here.
|
||||
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 400000
|
||||
maximum: 384000000
|
||||
|
||||
disable-wp:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
When set, no physical write-protect line is present. This
|
||||
property should only be specified when the controller has a
|
||||
dedicated write-protect detection logic. If a GPIO is always used
|
||||
for the write-protect detection logic, it is sufficient to not
|
||||
specify the wp-gpios property in the absence of a write-protect
|
||||
line. Not used in combination with eMMC or SDIO.
|
||||
|
||||
wp-gpios:
|
||||
maxItems: 1
|
||||
description:
|
||||
GPIO to use for the write-protect detection.
|
||||
|
||||
cd-debounce-delay-ms:
|
||||
description:
|
||||
Set delay time before detecting card after card insert
|
||||
interrupt.
|
||||
|
||||
no-1-8-v:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
When specified, denotes that 1.8V card voltage is not supported
|
||||
on this system, even if the controller claims it.
|
||||
|
||||
cap-sd-highspeed:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
SD high-speed timing is supported.
|
||||
|
||||
cap-mmc-highspeed:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
MMC high-speed timing is supported.
|
||||
|
||||
sd-uhs-sdr12:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
SD UHS SDR12 speed is supported.
|
||||
|
||||
sd-uhs-sdr25:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
SD UHS SDR25 speed is supported.
|
||||
|
||||
sd-uhs-sdr50:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
SD UHS SDR50 speed is supported.
|
||||
|
||||
sd-uhs-sdr104:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
SD UHS SDR104 speed is supported.
|
||||
|
||||
sd-uhs-ddr50:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
SD UHS DDR50 speed is supported.
|
||||
|
||||
cap-power-off-card:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
Powering off the card is safe.
|
||||
|
||||
cap-mmc-hw-reset:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
eMMC hardware reset is supported
|
||||
|
||||
cap-sdio-irq:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
enable SDIO IRQ signalling on this interface
|
||||
|
||||
full-pwr-cycle:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
Full power cycle of the card is supported.
|
||||
|
||||
full-pwr-cycle-in-suspend:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
Full power cycle of the card in suspend is supported.
|
||||
|
||||
mmc-ddr-1_2v:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
eMMC high-speed DDR mode (1.2V I/O) is supported.
|
||||
|
||||
mmc-ddr-1_8v:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
eMMC high-speed DDR mode (1.8V I/O) is supported.
|
||||
|
||||
mmc-ddr-3_3v:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
eMMC high-speed DDR mode (3.3V I/O) is supported.
|
||||
|
||||
mmc-hs200-1_2v:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
eMMC HS200 mode (1.2V I/O) is supported.
|
||||
|
||||
mmc-hs200-1_8v:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
eMMC HS200 mode (1.8V I/O) is supported.
|
||||
|
||||
mmc-hs400-1_2v:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
eMMC HS400 mode (1.2V I/O) is supported.
|
||||
|
||||
mmc-hs400-1_8v:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
eMMC HS400 mode (1.8V I/O) is supported.
|
||||
|
||||
mmc-hs400-enhanced-strobe:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
eMMC HS400 enhanced strobe mode is supported
|
||||
|
||||
no-mmc-hs400:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
All eMMC HS400 modes are not supported.
|
||||
|
||||
dsr:
|
||||
description:
|
||||
Value the card Driver Stage Register (DSR) should be programmed
|
||||
with.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 0xffff
|
||||
|
||||
no-sdio:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
Controller is limited to send SDIO commands during
|
||||
initialization.
|
||||
|
||||
no-sd:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
Controller is limited to send SD commands during initialization.
|
||||
|
||||
no-mmc:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
Controller is limited to send MMC commands during
|
||||
initialization.
|
||||
|
||||
fixed-emmc-driver-type:
|
||||
description:
|
||||
For non-removable eMMC, enforce this driver type. The value is
|
||||
the driver type as specified in the eMMC specification (table
|
||||
206 in spec version 5.1)
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 4
|
||||
|
||||
post-power-on-delay-ms:
|
||||
description:
|
||||
It was invented for MMC pwrseq-simple which could be referred to
|
||||
mmc-pwrseq-simple.yaml. But now it\'s reused as a tunable delay
|
||||
waiting for I/O signalling and card power supply to be stable,
|
||||
regardless of whether pwrseq-simple is used. Default to 10ms if
|
||||
no available.
|
||||
default: 10
|
||||
|
||||
supports-cqe:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
The presence of this property indicates that the corresponding
|
||||
MMC host controller supports HW command queue feature.
|
||||
|
||||
disable-cqe-dcmd:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
The presence of this property indicates that the MMC
|
||||
controller\'s command queue engine (CQE) does not support direct
|
||||
commands (DCMDs).
|
||||
|
||||
keep-power-in-suspend:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
SDIO only. Preserves card power during a suspend/resume cycle.
|
||||
|
||||
wakeup-source:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
SDIO only. Enables wake up of host system on SDIO IRQ assertion.
|
||||
|
||||
vmmc-supply:
|
||||
description:
|
||||
Supply for the card power
|
||||
|
||||
vqmmc-supply:
|
||||
description:
|
||||
Supply for the bus IO line power, such as a level shifter.
|
||||
If the level shifter is controlled by a GPIO line, this shall
|
||||
be modeled as a "regulator-fixed" with a GPIO line for
|
||||
switching the level shifter on/off.
|
||||
|
||||
mmc-pwrseq:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
System-on-Chip designs may specify a specific MMC power
|
||||
sequence. To successfully detect an (e)MMC/SD/SDIO card, that
|
||||
power sequence must be maintained while initializing the card.
|
||||
|
||||
patternProperties:
|
||||
"^.*@[0-9]+$":
|
||||
type: object
|
||||
description: |
|
||||
On embedded systems the cards connected to a host may need
|
||||
additional properties. These can be specified in subnodes to the
|
||||
host controller node. The subnodes are identified by the
|
||||
standard \'reg\' property. Which information exactly can be
|
||||
specified depends on the bindings for the SDIO function driver
|
||||
for the subnode, as specified by the compatible string.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
description: |
|
||||
Name of SDIO function following generic names recommended
|
||||
practice
|
||||
|
||||
reg:
|
||||
items:
|
||||
- minimum: 0
|
||||
maximum: 7
|
||||
description:
|
||||
Must contain the SDIO function number of the function this
|
||||
subnode describes. A value of 0 denotes the memory SD
|
||||
function, values from 1 to 7 denote the SDIO functions.
|
||||
|
||||
required:
|
||||
- reg
|
||||
|
||||
"^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$":
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
items:
|
||||
minimum: 0
|
||||
maximum: 359
|
||||
description:
|
||||
Set the clock (phase) delays which are to be configured in the
|
||||
controller while switching to particular speed mode. These values
|
||||
are in pair of degrees.
|
||||
|
||||
dependencies:
|
||||
cd-debounce-delay-ms: [ cd-gpios ]
|
||||
fixed-emmc-driver-type: [ non-removable ]
|
||||
|
||||
additionalProperties: true
|
||||
unevaluatedProperties: true
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
49
Documentation/devicetree/bindings/mmc/mmc-slot.yaml
Normal file
49
Documentation/devicetree/bindings/mmc/mmc-slot.yaml
Normal file
@ -0,0 +1,49 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mmc/mmc-slot.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MMC slot properties
|
||||
|
||||
maintainers:
|
||||
- Ulf Hansson <ulf.hansson@linaro.org>
|
||||
|
||||
description:
|
||||
These properties defines slot properties for MMC controlers that
|
||||
have multiple slots or ports provided by the same controller and
|
||||
sharing the same resources.
|
||||
|
||||
$ref: mmc-controller-common.yaml#
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^slot(@.*)?$"
|
||||
|
||||
compatible:
|
||||
const: mmc-slot
|
||||
|
||||
reg:
|
||||
description:
|
||||
the slot (or "port") ID
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
mmc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
slot@0 {
|
||||
compatible = "mmc-slot";
|
||||
reg = <0>;
|
||||
bus-width = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@ -235,11 +235,19 @@ allOf:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: mediatek,mt8183-mmc
|
||||
enum:
|
||||
- mediatek,mt7986-mmc
|
||||
- mediatek,mt7988-mmc
|
||||
- mediatek,mt8183-mmc
|
||||
- mediatek,mt8196-mmc
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 2
|
||||
else:
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
- if:
|
||||
properties:
|
||||
|
||||
@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Qualcomm SDHCI controller (sdhci-msm)
|
||||
|
||||
maintainers:
|
||||
- Bhupesh Sharma <bhupesh.sharma@linaro.org>
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Konrad Dybcio <konradybcio@kernel.org>
|
||||
|
||||
description:
|
||||
Secure Digital Host Controller Interface (SDHCI) present on
|
||||
|
||||
@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Qualcomm Ethernet ETHQOS device
|
||||
|
||||
maintainers:
|
||||
- Bhupesh Sharma <bhupesh.sharma@linaro.org>
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Konrad Dybcio <konradybcio@kernel.org>
|
||||
|
||||
description:
|
||||
dwmmac based Qualcomm ethernet devices which support Gigabit
|
||||
|
||||
@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Qualcomm SM6115 Peripheral Authentication Service
|
||||
|
||||
maintainers:
|
||||
- Bhupesh Sharma <bhupesh.sharma@linaro.org>
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Konrad Dybcio <konradybcio@kernel.org>
|
||||
|
||||
description:
|
||||
Qualcomm SM6115 SoC Peripheral Authentication Service loads and boots
|
||||
|
||||
@ -19,7 +19,6 @@
|
||||
#include <linux/scatterlist.h>
|
||||
#include <linux/log2.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/pm_wakeup.h>
|
||||
#include <linux/suspend.h>
|
||||
#include <linux/fault-inject.h>
|
||||
#include <linux/random.h>
|
||||
@ -557,8 +556,7 @@ int mmc_cqe_recovery(struct mmc_host *host)
|
||||
|
||||
memset(&cmd, 0, sizeof(cmd));
|
||||
cmd.opcode = MMC_STOP_TRANSMISSION;
|
||||
cmd.flags = MMC_RSP_R1B | MMC_CMD_AC;
|
||||
cmd.flags &= ~MMC_RSP_CRC; /* Ignore CRC */
|
||||
cmd.flags = MMC_RSP_R1B_NO_CRC | MMC_CMD_AC; /* Ignore CRC */
|
||||
cmd.busy_timeout = MMC_CQE_RECOVERY_TIMEOUT;
|
||||
mmc_wait_for_cmd(host, &cmd, MMC_CMD_RETRIES);
|
||||
|
||||
@ -567,8 +565,7 @@ int mmc_cqe_recovery(struct mmc_host *host)
|
||||
memset(&cmd, 0, sizeof(cmd));
|
||||
cmd.opcode = MMC_CMDQ_TASK_MGMT;
|
||||
cmd.arg = 1; /* Discard entire queue */
|
||||
cmd.flags = MMC_RSP_R1B | MMC_CMD_AC;
|
||||
cmd.flags &= ~MMC_RSP_CRC; /* Ignore CRC */
|
||||
cmd.flags = MMC_RSP_R1B_NO_CRC | MMC_CMD_AC; /* Ignore CRC */
|
||||
cmd.busy_timeout = MMC_CQE_RECOVERY_TIMEOUT;
|
||||
err = mmc_wait_for_cmd(host, &cmd, MMC_CMD_RETRIES);
|
||||
|
||||
|
||||
@ -14,7 +14,6 @@
|
||||
#include <linux/idr.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/pagemap.h>
|
||||
#include <linux/pm_wakeup.h>
|
||||
#include <linux/export.h>
|
||||
#include <linux/leds.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
@ -458,6 +458,8 @@ static unsigned mmc_sdio_get_max_clock(struct mmc_card *card)
|
||||
if (mmc_card_sd_combo(card))
|
||||
max_dtr = min(max_dtr, mmc_sd_get_max_clock(card));
|
||||
|
||||
max_dtr = min_not_zero(max_dtr, card->quirk_max_rate);
|
||||
|
||||
return max_dtr;
|
||||
}
|
||||
|
||||
|
||||
@ -1343,6 +1343,25 @@ static int bcm2835_add_host(struct bcm2835_host *host)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bcm2835_suspend(struct device *dev)
|
||||
{
|
||||
struct bcm2835_host *host = dev_get_drvdata(dev);
|
||||
|
||||
clk_disable_unprepare(host->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bcm2835_resume(struct device *dev)
|
||||
{
|
||||
struct bcm2835_host *host = dev_get_drvdata(dev);
|
||||
|
||||
return clk_prepare_enable(host->clk);
|
||||
}
|
||||
|
||||
static DEFINE_SIMPLE_DEV_PM_OPS(bcm2835_pm_ops, bcm2835_suspend,
|
||||
bcm2835_resume);
|
||||
|
||||
static int bcm2835_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
@ -1471,6 +1490,7 @@ static struct platform_driver bcm2835_driver = {
|
||||
.name = "sdhost-bcm2835",
|
||||
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
|
||||
.of_match_table = bcm2835_match,
|
||||
.pm = pm_ptr(&bcm2835_pm_ops),
|
||||
},
|
||||
};
|
||||
module_platform_driver(bcm2835_driver);
|
||||
|
||||
@ -25,22 +25,16 @@ static const struct cqhci_crypto_alg_entry {
|
||||
static inline struct cqhci_host *
|
||||
cqhci_host_from_crypto_profile(struct blk_crypto_profile *profile)
|
||||
{
|
||||
struct mmc_host *mmc =
|
||||
container_of(profile, struct mmc_host, crypto_profile);
|
||||
|
||||
return mmc->cqe_private;
|
||||
return mmc_from_crypto_profile(profile)->cqe_private;
|
||||
}
|
||||
|
||||
static int cqhci_crypto_program_key(struct cqhci_host *cq_host,
|
||||
const union cqhci_crypto_cfg_entry *cfg,
|
||||
int slot)
|
||||
static void cqhci_crypto_program_key(struct cqhci_host *cq_host,
|
||||
const union cqhci_crypto_cfg_entry *cfg,
|
||||
int slot)
|
||||
{
|
||||
u32 slot_offset = cq_host->crypto_cfg_register + slot * sizeof(*cfg);
|
||||
int i;
|
||||
|
||||
if (cq_host->ops->program_key)
|
||||
return cq_host->ops->program_key(cq_host, cfg, slot);
|
||||
|
||||
/* Clear CFGE */
|
||||
cqhci_writel(cq_host, 0, slot_offset + 16 * sizeof(cfg->reg_val[0]));
|
||||
|
||||
@ -55,7 +49,6 @@ static int cqhci_crypto_program_key(struct cqhci_host *cq_host,
|
||||
/* Write dword 16, which includes the new value of CFGE */
|
||||
cqhci_writel(cq_host, le32_to_cpu(cfg->reg_val[16]),
|
||||
slot_offset + 16 * sizeof(cfg->reg_val[0]));
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cqhci_crypto_keyslot_program(struct blk_crypto_profile *profile,
|
||||
@ -72,7 +65,6 @@ static int cqhci_crypto_keyslot_program(struct blk_crypto_profile *profile,
|
||||
int i;
|
||||
int cap_idx = -1;
|
||||
union cqhci_crypto_cfg_entry cfg = {};
|
||||
int err;
|
||||
|
||||
BUILD_BUG_ON(CQHCI_CRYPTO_KEY_SIZE_INVALID != 0);
|
||||
for (i = 0; i < cq_host->crypto_capabilities.num_crypto_cap; i++) {
|
||||
@ -99,10 +91,10 @@ static int cqhci_crypto_keyslot_program(struct blk_crypto_profile *profile,
|
||||
memcpy(cfg.crypto_key, key->raw, key->size);
|
||||
}
|
||||
|
||||
err = cqhci_crypto_program_key(cq_host, &cfg, slot);
|
||||
cqhci_crypto_program_key(cq_host, &cfg, slot);
|
||||
|
||||
memzero_explicit(&cfg, sizeof(cfg));
|
||||
return err;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cqhci_crypto_clear_keyslot(struct cqhci_host *cq_host, int slot)
|
||||
@ -113,7 +105,8 @@ static int cqhci_crypto_clear_keyslot(struct cqhci_host *cq_host, int slot)
|
||||
*/
|
||||
union cqhci_crypto_cfg_entry cfg = {};
|
||||
|
||||
return cqhci_crypto_program_key(cq_host, &cfg, slot);
|
||||
cqhci_crypto_program_key(cq_host, &cfg, slot);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cqhci_crypto_keyslot_evict(struct blk_crypto_profile *profile,
|
||||
@ -170,7 +163,6 @@ int cqhci_crypto_init(struct cqhci_host *cq_host)
|
||||
struct mmc_host *mmc = cq_host->mmc;
|
||||
struct device *dev = mmc_dev(mmc);
|
||||
struct blk_crypto_profile *profile = &mmc->crypto_profile;
|
||||
unsigned int num_keyslots;
|
||||
unsigned int cap_idx;
|
||||
enum blk_crypto_mode_num blk_mode_num;
|
||||
unsigned int slot;
|
||||
@ -180,6 +172,9 @@ int cqhci_crypto_init(struct cqhci_host *cq_host)
|
||||
!(cqhci_readl(cq_host, CQHCI_CAP) & CQHCI_CAP_CS))
|
||||
goto out;
|
||||
|
||||
if (cq_host->ops->uses_custom_crypto_profile)
|
||||
goto profile_initialized;
|
||||
|
||||
cq_host->crypto_capabilities.reg_val =
|
||||
cpu_to_le32(cqhci_readl(cq_host, CQHCI_CCAP));
|
||||
|
||||
@ -198,9 +193,8 @@ int cqhci_crypto_init(struct cqhci_host *cq_host)
|
||||
* CCAP.CFGC is off by one, so the actual number of crypto
|
||||
* configurations (a.k.a. keyslots) is CCAP.CFGC + 1.
|
||||
*/
|
||||
num_keyslots = cq_host->crypto_capabilities.config_count + 1;
|
||||
|
||||
err = devm_blk_crypto_profile_init(dev, profile, num_keyslots);
|
||||
err = devm_blk_crypto_profile_init(
|
||||
dev, profile, cq_host->crypto_capabilities.config_count + 1);
|
||||
if (err)
|
||||
goto out;
|
||||
|
||||
@ -228,9 +222,11 @@ int cqhci_crypto_init(struct cqhci_host *cq_host)
|
||||
cq_host->crypto_cap_array[cap_idx].sdus_mask * 512;
|
||||
}
|
||||
|
||||
profile_initialized:
|
||||
|
||||
/* Clear all the keyslots so that we start in a known state. */
|
||||
for (slot = 0; slot < num_keyslots; slot++)
|
||||
cqhci_crypto_clear_keyslot(cq_host, slot);
|
||||
for (slot = 0; slot < profile->num_slots; slot++)
|
||||
profile->ll_ops.keyslot_evict(profile, NULL, slot);
|
||||
|
||||
/* CQHCI crypto requires the use of 128-bit task descriptors. */
|
||||
cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
|
||||
|
||||
@ -289,13 +289,11 @@ struct cqhci_host_ops {
|
||||
u64 *data);
|
||||
void (*pre_enable)(struct mmc_host *mmc);
|
||||
void (*post_disable)(struct mmc_host *mmc);
|
||||
#ifdef CONFIG_MMC_CRYPTO
|
||||
int (*program_key)(struct cqhci_host *cq_host,
|
||||
const union cqhci_crypto_cfg_entry *cfg, int slot);
|
||||
#endif
|
||||
void (*set_tran_desc)(struct cqhci_host *cq_host, u8 **desc,
|
||||
dma_addr_t addr, int len, bool end, bool dma64);
|
||||
|
||||
#ifdef CONFIG_MMC_CRYPTO
|
||||
bool uses_custom_crypto_profile;
|
||||
#endif
|
||||
};
|
||||
|
||||
static inline void cqhci_writel(struct cqhci_host *host, u32 val, int reg)
|
||||
|
||||
@ -414,6 +414,7 @@ struct mtk_mmc_compatible {
|
||||
u8 clk_div_bits;
|
||||
bool recheck_sdio_irq;
|
||||
bool hs400_tune; /* only used for MT8173 */
|
||||
bool needs_top_base;
|
||||
u32 pad_tune_reg;
|
||||
bool async_fifo;
|
||||
bool data_tune;
|
||||
@ -587,6 +588,7 @@ static const struct mtk_mmc_compatible mt7986_compat = {
|
||||
.clk_div_bits = 12,
|
||||
.recheck_sdio_irq = true,
|
||||
.hs400_tune = false,
|
||||
.needs_top_base = true,
|
||||
.pad_tune_reg = MSDC_PAD_TUNE0,
|
||||
.async_fifo = true,
|
||||
.data_tune = true,
|
||||
@ -627,6 +629,7 @@ static const struct mtk_mmc_compatible mt8183_compat = {
|
||||
.clk_div_bits = 12,
|
||||
.recheck_sdio_irq = false,
|
||||
.hs400_tune = false,
|
||||
.needs_top_base = true,
|
||||
.pad_tune_reg = MSDC_PAD_TUNE0,
|
||||
.async_fifo = true,
|
||||
.data_tune = true,
|
||||
@ -653,6 +656,7 @@ static const struct mtk_mmc_compatible mt8196_compat = {
|
||||
.clk_div_bits = 12,
|
||||
.recheck_sdio_irq = false,
|
||||
.hs400_tune = false,
|
||||
.needs_top_base = true,
|
||||
.pad_tune_reg = MSDC_PAD_TUNE0,
|
||||
.async_fifo = true,
|
||||
.data_tune = true,
|
||||
@ -1097,11 +1101,12 @@ static inline u32 msdc_cmd_find_resp(struct msdc_host *host,
|
||||
u32 resp;
|
||||
|
||||
switch (mmc_resp_type(cmd)) {
|
||||
/* Actually, R1, R5, R6, R7 are the same */
|
||||
/* Actually, R1, R5, R6, R7 are the same */
|
||||
case MMC_RSP_R1:
|
||||
resp = 0x1;
|
||||
break;
|
||||
case MMC_RSP_R1B:
|
||||
case MMC_RSP_R1B_NO_CRC:
|
||||
resp = 0x7;
|
||||
break;
|
||||
case MMC_RSP_R2:
|
||||
@ -1351,7 +1356,8 @@ static bool msdc_cmd_done(struct msdc_host *host, int events,
|
||||
* CRC error.
|
||||
*/
|
||||
msdc_reset_hw(host);
|
||||
if (events & MSDC_INT_RSPCRCERR) {
|
||||
if (events & MSDC_INT_RSPCRCERR &&
|
||||
mmc_resp_type(cmd) != MMC_RSP_R1B_NO_CRC) {
|
||||
cmd->error = -EILSEQ;
|
||||
host->error |= REQ_CMD_EIO;
|
||||
} else if (events & MSDC_INT_CMDTMO) {
|
||||
@ -2885,9 +2891,13 @@ static int msdc_drv_probe(struct platform_device *pdev)
|
||||
if (IS_ERR(host->base))
|
||||
return PTR_ERR(host->base);
|
||||
|
||||
host->top_base = devm_platform_ioremap_resource(pdev, 1);
|
||||
if (IS_ERR(host->top_base))
|
||||
host->top_base = NULL;
|
||||
host->dev_comp = of_device_get_match_data(&pdev->dev);
|
||||
|
||||
if (host->dev_comp->needs_top_base) {
|
||||
host->top_base = devm_platform_ioremap_resource(pdev, 1);
|
||||
if (IS_ERR(host->top_base))
|
||||
return PTR_ERR(host->top_base);
|
||||
}
|
||||
|
||||
ret = mmc_regulator_get_supply(mmc);
|
||||
if (ret)
|
||||
@ -2949,7 +2959,6 @@ static int msdc_drv_probe(struct platform_device *pdev)
|
||||
msdc_of_property_parse(pdev, host);
|
||||
|
||||
host->dev = &pdev->dev;
|
||||
host->dev_comp = of_device_get_match_data(&pdev->dev);
|
||||
host->src_clk_freq = clk_get_rate(host->src_clk);
|
||||
/* Set host parameters to mmc */
|
||||
mmc->ops = &mt_msdc_ops;
|
||||
|
||||
@ -115,8 +115,6 @@ static int sd_response_type(struct mmc_command *cmd)
|
||||
return SD_RSP_TYPE_R0;
|
||||
case MMC_RSP_R1:
|
||||
return SD_RSP_TYPE_R1;
|
||||
case MMC_RSP_R1_NO_CRC:
|
||||
return SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7;
|
||||
case MMC_RSP_R1B:
|
||||
return SD_RSP_TYPE_R1b;
|
||||
case MMC_RSP_R2:
|
||||
|
||||
@ -313,9 +313,6 @@ static void sd_send_cmd_get_rsp(struct rtsx_usb_sdmmc *host,
|
||||
case MMC_RSP_R1:
|
||||
rsp_type = SD_RSP_TYPE_R1;
|
||||
break;
|
||||
case MMC_RSP_R1_NO_CRC:
|
||||
rsp_type = SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7;
|
||||
break;
|
||||
case MMC_RSP_R1B:
|
||||
rsp_type = SD_RSP_TYPE_R1b;
|
||||
break;
|
||||
|
||||
@ -822,8 +822,6 @@ static int sdhci_acpi_probe(struct platform_device *pdev)
|
||||
struct acpi_device *device;
|
||||
struct sdhci_acpi_host *c;
|
||||
struct sdhci_host *host;
|
||||
struct resource *iomem;
|
||||
resource_size_t len;
|
||||
size_t priv_size;
|
||||
int quirks = 0;
|
||||
int err;
|
||||
@ -844,17 +842,6 @@ static int sdhci_acpi_probe(struct platform_device *pdev)
|
||||
if (sdhci_acpi_byt_defer(dev))
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!iomem)
|
||||
return -ENOMEM;
|
||||
|
||||
len = resource_size(iomem);
|
||||
if (len < 0x100)
|
||||
dev_err(dev, "Invalid iomem size!\n");
|
||||
|
||||
if (!devm_request_mem_region(dev, iomem->start, len, dev_name(dev)))
|
||||
return -ENOMEM;
|
||||
|
||||
priv_size = slot ? slot->priv_size : 0;
|
||||
host = sdhci_alloc_host(dev, sizeof(struct sdhci_acpi_host) + priv_size);
|
||||
if (IS_ERR(host))
|
||||
@ -876,10 +863,9 @@ static int sdhci_acpi_probe(struct platform_device *pdev)
|
||||
goto err_free;
|
||||
}
|
||||
|
||||
host->ioaddr = devm_ioremap(dev, iomem->start,
|
||||
resource_size(iomem));
|
||||
if (host->ioaddr == NULL) {
|
||||
err = -ENOMEM;
|
||||
host->ioaddr = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(host->ioaddr)) {
|
||||
err = PTR_ERR(host->ioaddr);
|
||||
goto err_free;
|
||||
}
|
||||
|
||||
|
||||
@ -304,6 +304,7 @@ static struct esdhc_soc_data usdhc_s32g2_data = {
|
||||
| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
|
||||
| ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
|
||||
| ESDHC_FLAG_SKIP_ERR004536 | ESDHC_FLAG_SKIP_CD_WAKE,
|
||||
.quirks = SDHCI_QUIRK_NO_LED,
|
||||
};
|
||||
|
||||
static struct esdhc_soc_data usdhc_imx7ulp_data = {
|
||||
|
||||
@ -1807,12 +1807,19 @@ out:
|
||||
|
||||
#ifdef CONFIG_MMC_CRYPTO
|
||||
|
||||
static const struct blk_crypto_ll_ops sdhci_msm_crypto_ops; /* forward decl */
|
||||
|
||||
static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host,
|
||||
struct cqhci_host *cq_host)
|
||||
{
|
||||
struct mmc_host *mmc = msm_host->mmc;
|
||||
struct blk_crypto_profile *profile = &mmc->crypto_profile;
|
||||
struct device *dev = mmc_dev(mmc);
|
||||
struct qcom_ice *ice;
|
||||
union cqhci_crypto_capabilities caps;
|
||||
union cqhci_crypto_cap_entry cap;
|
||||
int err;
|
||||
int i;
|
||||
|
||||
if (!(cqhci_readl(cq_host, CQHCI_CAP) & CQHCI_CAP_CS))
|
||||
return 0;
|
||||
@ -1827,8 +1834,37 @@ static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host,
|
||||
return PTR_ERR_OR_ZERO(ice);
|
||||
|
||||
msm_host->ice = ice;
|
||||
mmc->caps2 |= MMC_CAP2_CRYPTO;
|
||||
|
||||
/* Initialize the blk_crypto_profile */
|
||||
|
||||
caps.reg_val = cpu_to_le32(cqhci_readl(cq_host, CQHCI_CCAP));
|
||||
|
||||
/* The number of keyslots supported is (CFGC+1) */
|
||||
err = devm_blk_crypto_profile_init(dev, profile, caps.config_count + 1);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
profile->ll_ops = sdhci_msm_crypto_ops;
|
||||
profile->max_dun_bytes_supported = 4;
|
||||
profile->dev = dev;
|
||||
|
||||
/*
|
||||
* Currently this driver only supports AES-256-XTS. All known versions
|
||||
* of ICE support it, but to be safe make sure it is really declared in
|
||||
* the crypto capability registers. The crypto capability registers
|
||||
* also give the supported data unit size(s).
|
||||
*/
|
||||
for (i = 0; i < caps.num_crypto_cap; i++) {
|
||||
cap.reg_val = cpu_to_le32(cqhci_readl(cq_host,
|
||||
CQHCI_CRYPTOCAP +
|
||||
i * sizeof(__le32)));
|
||||
if (cap.algorithm_id == CQHCI_CRYPTO_ALG_AES_XTS &&
|
||||
cap.key_size == CQHCI_CRYPTO_KEY_SIZE_256)
|
||||
profile->modes_supported[BLK_ENCRYPTION_MODE_AES_256_XTS] |=
|
||||
cap.sdus_mask * 512;
|
||||
}
|
||||
|
||||
mmc->caps2 |= MMC_CAP2_CRYPTO;
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -1854,35 +1890,55 @@ static __maybe_unused int sdhci_msm_ice_suspend(struct sdhci_msm_host *msm_host)
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Program a key into a QC ICE keyslot, or evict a keyslot. QC ICE requires
|
||||
* vendor-specific SCM calls for this; it doesn't support the standard way.
|
||||
*/
|
||||
static int sdhci_msm_program_key(struct cqhci_host *cq_host,
|
||||
const union cqhci_crypto_cfg_entry *cfg,
|
||||
int slot)
|
||||
static inline struct sdhci_msm_host *
|
||||
sdhci_msm_host_from_crypto_profile(struct blk_crypto_profile *profile)
|
||||
{
|
||||
struct sdhci_host *host = mmc_priv(cq_host->mmc);
|
||||
struct mmc_host *mmc = mmc_from_crypto_profile(profile);
|
||||
struct sdhci_host *host = mmc_priv(mmc);
|
||||
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
|
||||
struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
|
||||
union cqhci_crypto_cap_entry cap;
|
||||
|
||||
if (!(cfg->config_enable & CQHCI_CRYPTO_CONFIGURATION_ENABLE))
|
||||
return qcom_ice_evict_key(msm_host->ice, slot);
|
||||
return msm_host;
|
||||
}
|
||||
|
||||
/*
|
||||
* Program a key into a QC ICE keyslot. QC ICE requires a QC-specific SCM call
|
||||
* for this; it doesn't support the standard way.
|
||||
*/
|
||||
static int sdhci_msm_ice_keyslot_program(struct blk_crypto_profile *profile,
|
||||
const struct blk_crypto_key *key,
|
||||
unsigned int slot)
|
||||
{
|
||||
struct sdhci_msm_host *msm_host =
|
||||
sdhci_msm_host_from_crypto_profile(profile);
|
||||
|
||||
/* Only AES-256-XTS has been tested so far. */
|
||||
cap = cq_host->crypto_cap_array[cfg->crypto_cap_idx];
|
||||
if (cap.algorithm_id != CQHCI_CRYPTO_ALG_AES_XTS ||
|
||||
cap.key_size != CQHCI_CRYPTO_KEY_SIZE_256)
|
||||
return -EINVAL;
|
||||
if (key->crypto_cfg.crypto_mode != BLK_ENCRYPTION_MODE_AES_256_XTS)
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
return qcom_ice_program_key(msm_host->ice,
|
||||
QCOM_ICE_CRYPTO_ALG_AES_XTS,
|
||||
QCOM_ICE_CRYPTO_KEY_SIZE_256,
|
||||
cfg->crypto_key,
|
||||
cfg->data_unit_size, slot);
|
||||
key->raw,
|
||||
key->crypto_cfg.data_unit_size / 512,
|
||||
slot);
|
||||
}
|
||||
|
||||
static int sdhci_msm_ice_keyslot_evict(struct blk_crypto_profile *profile,
|
||||
const struct blk_crypto_key *key,
|
||||
unsigned int slot)
|
||||
{
|
||||
struct sdhci_msm_host *msm_host =
|
||||
sdhci_msm_host_from_crypto_profile(profile);
|
||||
|
||||
return qcom_ice_evict_key(msm_host->ice, slot);
|
||||
}
|
||||
|
||||
static const struct blk_crypto_ll_ops sdhci_msm_crypto_ops = {
|
||||
.keyslot_program = sdhci_msm_ice_keyslot_program,
|
||||
.keyslot_evict = sdhci_msm_ice_keyslot_evict,
|
||||
};
|
||||
|
||||
#else /* CONFIG_MMC_CRYPTO */
|
||||
|
||||
static inline int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host,
|
||||
@ -1988,7 +2044,7 @@ static const struct cqhci_host_ops sdhci_msm_cqhci_ops = {
|
||||
.enable = sdhci_msm_cqe_enable,
|
||||
.disable = sdhci_msm_cqe_disable,
|
||||
#ifdef CONFIG_MMC_CRYPTO
|
||||
.program_key = sdhci_msm_program_key,
|
||||
.uses_custom_crypto_profile = true,
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
@ -297,7 +297,6 @@ static int tmio_mmc_start_command(struct tmio_mmc_host *host,
|
||||
switch (mmc_resp_type(cmd)) {
|
||||
case MMC_RSP_NONE: c |= RESP_NONE; break;
|
||||
case MMC_RSP_R1:
|
||||
case MMC_RSP_R1_NO_CRC:
|
||||
c |= RESP_R1; break;
|
||||
case MMC_RSP_R1B: c |= RESP_R1B; break;
|
||||
case MMC_RSP_R2: c |= RESP_R2; break;
|
||||
|
||||
@ -57,6 +57,7 @@ struct mmc_command {
|
||||
#define MMC_RSP_NONE (0)
|
||||
#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
|
||||
#define MMC_RSP_R1B (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE|MMC_RSP_BUSY)
|
||||
#define MMC_RSP_R1B_NO_CRC (MMC_RSP_PRESENT|MMC_RSP_OPCODE|MMC_RSP_BUSY)
|
||||
#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
|
||||
#define MMC_RSP_R3 (MMC_RSP_PRESENT)
|
||||
#define MMC_RSP_R4 (MMC_RSP_PRESENT)
|
||||
@ -64,9 +65,6 @@ struct mmc_command {
|
||||
#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
|
||||
#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
|
||||
|
||||
/* Can be used by core to poll after switch to MMC HS mode */
|
||||
#define MMC_RSP_R1_NO_CRC (MMC_RSP_PRESENT|MMC_RSP_OPCODE)
|
||||
|
||||
#define mmc_resp_type(cmd) ((cmd)->flags & (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC|MMC_RSP_BUSY|MMC_RSP_OPCODE))
|
||||
|
||||
/*
|
||||
|
||||
@ -590,6 +590,14 @@ static inline struct mmc_host *mmc_from_priv(void *priv)
|
||||
return container_of(priv, struct mmc_host, private);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MMC_CRYPTO
|
||||
static inline struct mmc_host *
|
||||
mmc_from_crypto_profile(struct blk_crypto_profile *profile)
|
||||
{
|
||||
return container_of(profile, struct mmc_host, crypto_profile);
|
||||
}
|
||||
#endif
|
||||
|
||||
#define mmc_host_is_spi(host) ((host)->caps & MMC_CAP_SPI)
|
||||
|
||||
#define mmc_dev(x) ((x)->parent)
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user