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net: pse-pd: pd692x0: Enhance with new current limit and voltage read callbacks
This patch expands PSE callbacks with newly introduced pi_get/set_current_limit() and pi_get_voltage() callback. It also add the power limit ranges description in the status returned. The only way to set ps692x0 port power limit is by configure the power class plus a small power supplement which maximum depends on each class. Acked-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Kory Maincent <kory.maincent@bootlin.com> Link: https://patch.msgid.link/20240704-feature_poe_power_cap-v6-7-320003204264@bootlin.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Kory Maincent (Dent Project)
Jakub Kicinski
parent
dac3de1930
commit
a87e699c9d
@ -74,6 +74,8 @@ enum {
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PD692X0_MSG_GET_PORT_STATUS,
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PD692X0_MSG_DOWNLOAD_CMD,
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PD692X0_MSG_GET_PORT_CLASS,
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PD692X0_MSG_GET_PORT_MEAS,
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PD692X0_MSG_GET_PORT_PARAM,
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/* add new message above here */
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PD692X0_MSG_CNT
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@ -135,7 +137,7 @@ static const struct pd692x0_msg pd692x0_msg_template_list[PD692X0_MSG_CNT] = {
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[PD692X0_MSG_SET_PORT_PARAM] = {
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.key = PD692X0_KEY_CMD,
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.sub = {0x05, 0xc0},
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.data = { 0, 0xff, 0xff, 0xff,
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.data = { 0xf, 0xff, 0xff, 0xff,
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0x4e, 0x4e, 0x4e, 0x4e},
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},
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[PD692X0_MSG_GET_PORT_STATUS] = {
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@ -156,6 +158,18 @@ static const struct pd692x0_msg pd692x0_msg_template_list[PD692X0_MSG_CNT] = {
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.data = {0x4e, 0x4e, 0x4e, 0x4e,
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0x4e, 0x4e, 0x4e, 0x4e},
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},
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[PD692X0_MSG_GET_PORT_MEAS] = {
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.key = PD692X0_KEY_REQ,
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.sub = {0x05, 0xc5},
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.data = {0x4e, 0x4e, 0x4e, 0x4e,
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0x4e, 0x4e, 0x4e, 0x4e},
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},
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[PD692X0_MSG_GET_PORT_PARAM] = {
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.key = PD692X0_KEY_REQ,
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.sub = {0x05, 0xc0},
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.data = {0x4e, 0x4e, 0x4e, 0x4e,
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0x4e, 0x4e, 0x4e, 0x4e},
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},
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};
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static u8 pd692x0_build_msg(struct pd692x0_msg *msg, u8 echo)
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@ -520,6 +534,106 @@ pd692x0_get_ext_state(struct ethtool_c33_pse_ext_state_info *c33_ext_state_info,
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}
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}
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struct pd692x0_class_pw {
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int class;
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int class_cfg_value;
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int class_pw;
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int max_added_class_pw;
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};
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#define PD692X0_CLASS_PW_TABLE_SIZE 4
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/* 4/2 pairs class configuration power table in compliance mode.
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* Need to be arranged in ascending order of power support.
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*/
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static const struct pd692x0_class_pw
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pd692x0_class_pw_table[PD692X0_CLASS_PW_TABLE_SIZE] = {
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{.class = 3, .class_cfg_value = 0x3, .class_pw = 15000, .max_added_class_pw = 3100},
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{.class = 4, .class_cfg_value = 0x2, .class_pw = 30000, .max_added_class_pw = 8000},
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{.class = 6, .class_cfg_value = 0x1, .class_pw = 60000, .max_added_class_pw = 5000},
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{.class = 8, .class_cfg_value = 0x0, .class_pw = 90000, .max_added_class_pw = 7500},
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};
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static int pd692x0_pi_get_pw_from_table(int op_mode, int added_pw)
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{
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const struct pd692x0_class_pw *pw_table;
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int i;
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pw_table = pd692x0_class_pw_table;
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for (i = 0; i < PD692X0_CLASS_PW_TABLE_SIZE; i++, pw_table++) {
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if (pw_table->class_cfg_value == op_mode)
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return pw_table->class_pw + added_pw * 100;
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}
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return -ERANGE;
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}
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static int pd692x0_pi_set_pw_from_table(struct device *dev,
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struct pd692x0_msg *msg, int pw)
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{
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const struct pd692x0_class_pw *pw_table;
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int i;
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pw_table = pd692x0_class_pw_table;
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if (pw < pw_table->class_pw) {
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dev_err(dev,
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"Power limit %dmW not supported. Ranges minimal available: [%d-%d]\n",
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pw,
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pw_table->class_pw,
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pw_table->class_pw + pw_table->max_added_class_pw);
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return -ERANGE;
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}
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for (i = 0; i < PD692X0_CLASS_PW_TABLE_SIZE; i++, pw_table++) {
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if (pw > (pw_table->class_pw + pw_table->max_added_class_pw))
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continue;
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if (pw < pw_table->class_pw) {
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dev_err(dev,
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"Power limit %dmW not supported. Ranges availables: [%d-%d] or [%d-%d]\n",
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pw,
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(pw_table - 1)->class_pw,
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(pw_table - 1)->class_pw + (pw_table - 1)->max_added_class_pw,
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pw_table->class_pw,
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pw_table->class_pw + pw_table->max_added_class_pw);
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return -ERANGE;
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}
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msg->data[2] = pw_table->class_cfg_value;
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msg->data[3] = (pw - pw_table->class_pw) / 100;
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return 0;
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}
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pw_table--;
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dev_warn(dev,
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"Power limit %dmW not supported. Set to highest power limit %dmW\n",
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pw, pw_table->class_pw + pw_table->max_added_class_pw);
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msg->data[2] = pw_table->class_cfg_value;
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msg->data[3] = pw_table->max_added_class_pw / 100;
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return 0;
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}
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static int
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pd692x0_pi_get_pw_ranges(struct pse_control_status *st)
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{
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const struct pd692x0_class_pw *pw_table;
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int i;
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pw_table = pd692x0_class_pw_table;
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st->c33_pw_limit_ranges = kcalloc(PD692X0_CLASS_PW_TABLE_SIZE,
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sizeof(struct ethtool_c33_pse_pw_limit_range),
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GFP_KERNEL);
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if (!st->c33_pw_limit_ranges)
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return -ENOMEM;
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for (i = 0; i < PD692X0_CLASS_PW_TABLE_SIZE; i++, pw_table++) {
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st->c33_pw_limit_ranges[i].min = pw_table->class_pw;
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st->c33_pw_limit_ranges[i].max = pw_table->class_pw + pw_table->max_added_class_pw;
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}
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st->c33_pw_limit_nb_ranges = i;
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return 0;
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}
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static int pd692x0_ethtool_get_status(struct pse_controller_dev *pcdev,
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unsigned long id,
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struct netlink_ext_ack *extack,
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@ -558,9 +672,20 @@ static int pd692x0_ethtool_get_status(struct pse_controller_dev *pcdev,
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priv->admin_state[id] = status->c33_admin_state;
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pd692x0_get_ext_state(&status->c33_ext_state_info, buf.sub[0]);
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status->c33_actual_pw = (buf.data[0] << 4 | buf.data[1]) * 100;
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msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_PARAM];
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msg.sub[2] = id;
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memset(&buf, 0, sizeof(buf));
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ret = pd692x0_sendrecv_msg(priv, &msg, &buf);
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if (ret < 0)
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return ret;
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ret = pd692x0_pi_get_pw_from_table(buf.data[0], buf.data[1]);
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if (ret < 0)
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return ret;
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status->c33_avail_pw_limit = ret;
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memset(&buf, 0, sizeof(buf));
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msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_CLASS];
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msg.sub[2] = id;
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@ -572,6 +697,10 @@ static int pd692x0_ethtool_get_status(struct pse_controller_dev *pcdev,
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if (class <= 8)
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status->c33_pw_class = class;
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ret = pd692x0_pi_get_pw_ranges(status);
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if (ret < 0)
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return ret;
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return 0;
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}
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@ -850,12 +979,97 @@ static int pd692x0_setup_pi_matrix(struct pse_controller_dev *pcdev)
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return ret;
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}
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static int pd692x0_pi_get_voltage(struct pse_controller_dev *pcdev, int id)
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{
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struct pd692x0_priv *priv = to_pd692x0_priv(pcdev);
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struct pd692x0_msg msg, buf = {0};
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int ret;
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ret = pd692x0_fw_unavailable(priv);
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if (ret)
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return ret;
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msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_MEAS];
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msg.sub[2] = id;
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ret = pd692x0_sendrecv_msg(priv, &msg, &buf);
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if (ret < 0)
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return ret;
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/* Convert 0.1V unit to uV */
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return (buf.sub[0] << 8 | buf.sub[1]) * 100000;
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}
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static int pd692x0_pi_get_current_limit(struct pse_controller_dev *pcdev,
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int id)
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{
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struct pd692x0_priv *priv = to_pd692x0_priv(pcdev);
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struct pd692x0_msg msg, buf = {0};
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int mW, uV, uA, ret;
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s64 tmp_64;
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msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_PARAM];
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msg.sub[2] = id;
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ret = pd692x0_sendrecv_msg(priv, &msg, &buf);
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if (ret < 0)
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return ret;
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ret = pd692x0_pi_get_pw_from_table(buf.data[2], buf.data[3]);
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if (ret < 0)
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return ret;
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mW = ret;
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ret = pd692x0_pi_get_voltage(pcdev, id);
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if (ret < 0)
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return ret;
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uV = ret;
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tmp_64 = mW;
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tmp_64 *= 1000000000ull;
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/* uA = mW * 1000000000 / uV */
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uA = DIV_ROUND_CLOSEST_ULL(tmp_64, uV);
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return uA;
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}
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static int pd692x0_pi_set_current_limit(struct pse_controller_dev *pcdev,
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int id, int max_uA)
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{
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struct pd692x0_priv *priv = to_pd692x0_priv(pcdev);
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struct device *dev = &priv->client->dev;
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struct pd692x0_msg msg, buf = {0};
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int uV, ret, mW;
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s64 tmp_64;
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ret = pd692x0_fw_unavailable(priv);
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if (ret)
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return ret;
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ret = pd692x0_pi_get_voltage(pcdev, id);
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if (ret < 0)
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return ret;
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uV = ret;
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msg = pd692x0_msg_template_list[PD692X0_MSG_SET_PORT_PARAM];
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msg.sub[2] = id;
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tmp_64 = uV;
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tmp_64 *= max_uA;
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/* mW = uV * uA / 1000000000 */
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mW = DIV_ROUND_CLOSEST_ULL(tmp_64, 1000000000);
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ret = pd692x0_pi_set_pw_from_table(dev, &msg, mW);
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if (ret)
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return ret;
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return pd692x0_sendrecv_msg(priv, &msg, &buf);
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}
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static const struct pse_controller_ops pd692x0_ops = {
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.setup_pi_matrix = pd692x0_setup_pi_matrix,
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.ethtool_get_status = pd692x0_ethtool_get_status,
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.pi_enable = pd692x0_pi_enable,
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.pi_disable = pd692x0_pi_disable,
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.pi_is_enabled = pd692x0_pi_is_enabled,
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.pi_get_voltage = pd692x0_pi_get_voltage,
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.pi_get_current_limit = pd692x0_pi_get_current_limit,
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.pi_set_current_limit = pd692x0_pi_set_current_limit,
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};
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#define PD692X0_FW_LINE_MAX_SZ 0xff
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