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https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
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objtool/LoongArch: Implement instruction decoder
Only copy the minimal definitions of instruction opcodes and formats in inst.h from arch/loongarch to tools/arch/loongarch, and also copy the definition of sign_extend64() to tools/include/linux/bitops.h to decode the following kinds of instructions: (1) stack pointer related instructions addi.d, ld.d, st.d, ldptr.d and stptr.d (2) branch and jump related instructions beq, bne, blt, bge, bltu, bgeu, beqz, bnez, bceqz, bcnez, b, bl and jirl (3) other instructions break, nop and ertn See more info about instructions in LoongArch Reference Manual: https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html Co-developed-by: Jinyang He <hejinyang@loongson.cn> Signed-off-by: Jinyang He <hejinyang@loongson.cn> Co-developed-by: Youling Tang <tangyouling@loongson.cn> Signed-off-by: Youling Tang <tangyouling@loongson.cn> Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
This commit is contained in:
Tiezhu Yang
Huacai Chen
parent
e8aff71ca9
commit
b2d23158e6
161
tools/arch/loongarch/include/asm/inst.h
Normal file
161
tools/arch/loongarch/include/asm/inst.h
Normal file
@ -0,0 +1,161 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#ifndef _ASM_INST_H
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#define _ASM_INST_H
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#include <linux/bitops.h>
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#define LOONGARCH_INSN_NOP 0x03400000
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enum reg0i15_op {
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break_op = 0x54,
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};
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enum reg0i26_op {
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b_op = 0x14,
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bl_op = 0x15,
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};
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enum reg1i21_op {
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beqz_op = 0x10,
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bnez_op = 0x11,
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bceqz_op = 0x12, /* bits[9:8] = 0x00 */
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bcnez_op = 0x12, /* bits[9:8] = 0x01 */
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};
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enum reg2_op {
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ertn_op = 0x1920e,
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};
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enum reg2i12_op {
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addid_op = 0x0b,
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andi_op = 0x0d,
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ldd_op = 0xa3,
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std_op = 0xa7,
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};
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enum reg2i14_op {
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ldptrd_op = 0x26,
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stptrd_op = 0x27,
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};
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enum reg2i16_op {
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jirl_op = 0x13,
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beq_op = 0x16,
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bne_op = 0x17,
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blt_op = 0x18,
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bge_op = 0x19,
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bltu_op = 0x1a,
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bgeu_op = 0x1b,
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};
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struct reg0i15_format {
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unsigned int immediate : 15;
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unsigned int opcode : 17;
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};
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struct reg0i26_format {
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unsigned int immediate_h : 10;
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unsigned int immediate_l : 16;
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unsigned int opcode : 6;
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};
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struct reg1i21_format {
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unsigned int immediate_h : 5;
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unsigned int rj : 5;
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unsigned int immediate_l : 16;
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unsigned int opcode : 6;
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};
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struct reg2_format {
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unsigned int rd : 5;
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unsigned int rj : 5;
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unsigned int opcode : 22;
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};
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struct reg2i12_format {
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unsigned int rd : 5;
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unsigned int rj : 5;
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unsigned int immediate : 12;
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unsigned int opcode : 10;
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};
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struct reg2i14_format {
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unsigned int rd : 5;
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unsigned int rj : 5;
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unsigned int immediate : 14;
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unsigned int opcode : 8;
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};
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struct reg2i16_format {
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unsigned int rd : 5;
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unsigned int rj : 5;
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unsigned int immediate : 16;
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unsigned int opcode : 6;
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};
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union loongarch_instruction {
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unsigned int word;
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struct reg0i15_format reg0i15_format;
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struct reg0i26_format reg0i26_format;
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struct reg1i21_format reg1i21_format;
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struct reg2_format reg2_format;
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struct reg2i12_format reg2i12_format;
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struct reg2i14_format reg2i14_format;
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struct reg2i16_format reg2i16_format;
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};
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#define LOONGARCH_INSN_SIZE sizeof(union loongarch_instruction)
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enum loongarch_gpr {
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LOONGARCH_GPR_ZERO = 0,
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LOONGARCH_GPR_RA = 1,
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LOONGARCH_GPR_TP = 2,
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LOONGARCH_GPR_SP = 3,
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LOONGARCH_GPR_A0 = 4, /* Reused as V0 for return value */
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LOONGARCH_GPR_A1, /* Reused as V1 for return value */
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LOONGARCH_GPR_A2,
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LOONGARCH_GPR_A3,
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LOONGARCH_GPR_A4,
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LOONGARCH_GPR_A5,
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LOONGARCH_GPR_A6,
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LOONGARCH_GPR_A7,
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LOONGARCH_GPR_T0 = 12,
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LOONGARCH_GPR_T1,
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LOONGARCH_GPR_T2,
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LOONGARCH_GPR_T3,
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LOONGARCH_GPR_T4,
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LOONGARCH_GPR_T5,
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LOONGARCH_GPR_T6,
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LOONGARCH_GPR_T7,
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LOONGARCH_GPR_T8,
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LOONGARCH_GPR_FP = 22,
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LOONGARCH_GPR_S0 = 23,
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LOONGARCH_GPR_S1,
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LOONGARCH_GPR_S2,
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LOONGARCH_GPR_S3,
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LOONGARCH_GPR_S4,
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LOONGARCH_GPR_S5,
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LOONGARCH_GPR_S6,
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LOONGARCH_GPR_S7,
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LOONGARCH_GPR_S8,
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LOONGARCH_GPR_MAX
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};
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#define DEF_EMIT_REG2I16_FORMAT(NAME, OP) \
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static inline void emit_##NAME(union loongarch_instruction *insn, \
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enum loongarch_gpr rj, \
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enum loongarch_gpr rd, \
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int offset) \
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{ \
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insn->reg2i16_format.opcode = OP; \
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insn->reg2i16_format.immediate = offset; \
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insn->reg2i16_format.rj = rj; \
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insn->reg2i16_format.rd = rd; \
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}
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DEF_EMIT_REG2I16_FORMAT(jirl, jirl_op)
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#endif /* _ASM_INST_H */
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@ -87,4 +87,15 @@ static inline __u32 rol32(__u32 word, unsigned int shift)
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return (word << shift) | (word >> ((-shift) & 31));
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}
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/**
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* sign_extend64 - sign extend a 64-bit value using specified bit as sign-bit
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* @value: value to sign extend
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* @index: 0 based bit index (0<=index<64) to sign bit
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*/
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static __always_inline __s64 sign_extend64(__u64 value, int index)
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{
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__u8 shift = 63 - index;
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return (__s64)(value << shift) >> shift;
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}
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#endif
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@ -1,6 +1,12 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include <string.h>
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#include <objtool/check.h>
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#include <objtool/warn.h>
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#include <asm/inst.h>
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#ifndef EM_LOONGARCH
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#define EM_LOONGARCH 258
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#endif
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int arch_ftrace_match(char *name)
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{
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@ -39,21 +45,284 @@ int arch_decode_hint_reg(u8 sp_reg, int *base)
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return 0;
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}
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static bool is_loongarch(const struct elf *elf)
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{
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if (elf->ehdr.e_machine == EM_LOONGARCH)
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return true;
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WARN("unexpected ELF machine type %d", elf->ehdr.e_machine);
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return false;
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}
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#define ADD_OP(op) \
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if (!(op = calloc(1, sizeof(*op)))) \
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return -1; \
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else for (*ops_list = op, ops_list = &op->next; op; op = NULL)
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static bool decode_insn_reg0i26_fomat(union loongarch_instruction inst,
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struct instruction *insn)
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{
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switch (inst.reg0i26_format.opcode) {
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case b_op:
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insn->type = INSN_JUMP_UNCONDITIONAL;
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insn->immediate = sign_extend64(inst.reg0i26_format.immediate_h << 16 |
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inst.reg0i26_format.immediate_l, 25);
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break;
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case bl_op:
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insn->type = INSN_CALL;
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insn->immediate = sign_extend64(inst.reg0i26_format.immediate_h << 16 |
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inst.reg0i26_format.immediate_l, 25);
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break;
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default:
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return false;
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}
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return true;
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}
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static bool decode_insn_reg1i21_fomat(union loongarch_instruction inst,
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struct instruction *insn)
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{
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switch (inst.reg1i21_format.opcode) {
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case beqz_op:
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case bnez_op:
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case bceqz_op:
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insn->type = INSN_JUMP_CONDITIONAL;
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insn->immediate = sign_extend64(inst.reg1i21_format.immediate_h << 16 |
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inst.reg1i21_format.immediate_l, 20);
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break;
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default:
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return false;
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}
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return true;
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}
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static bool decode_insn_reg2i12_fomat(union loongarch_instruction inst,
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struct instruction *insn,
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struct stack_op **ops_list,
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struct stack_op *op)
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{
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switch (inst.reg2i12_format.opcode) {
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case addid_op:
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if ((inst.reg2i12_format.rd == CFI_SP) || (inst.reg2i12_format.rj == CFI_SP)) {
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/* addi.d sp,sp,si12 or addi.d fp,sp,si12 */
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insn->immediate = sign_extend64(inst.reg2i12_format.immediate, 11);
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ADD_OP(op) {
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op->src.type = OP_SRC_ADD;
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op->src.reg = inst.reg2i12_format.rj;
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op->src.offset = insn->immediate;
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op->dest.type = OP_DEST_REG;
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op->dest.reg = inst.reg2i12_format.rd;
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}
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}
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break;
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case ldd_op:
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if (inst.reg2i12_format.rj == CFI_SP) {
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/* ld.d rd,sp,si12 */
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insn->immediate = sign_extend64(inst.reg2i12_format.immediate, 11);
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ADD_OP(op) {
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op->src.type = OP_SRC_REG_INDIRECT;
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op->src.reg = CFI_SP;
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op->src.offset = insn->immediate;
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op->dest.type = OP_DEST_REG;
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op->dest.reg = inst.reg2i12_format.rd;
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}
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}
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break;
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case std_op:
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if (inst.reg2i12_format.rj == CFI_SP) {
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/* st.d rd,sp,si12 */
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insn->immediate = sign_extend64(inst.reg2i12_format.immediate, 11);
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ADD_OP(op) {
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op->src.type = OP_SRC_REG;
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op->src.reg = inst.reg2i12_format.rd;
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op->dest.type = OP_DEST_REG_INDIRECT;
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op->dest.reg = CFI_SP;
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op->dest.offset = insn->immediate;
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}
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}
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break;
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case andi_op:
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if (inst.reg2i12_format.rd == 0 &&
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inst.reg2i12_format.rj == 0 &&
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inst.reg2i12_format.immediate == 0)
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/* andi r0,r0,0 */
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insn->type = INSN_NOP;
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break;
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default:
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return false;
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}
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return true;
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}
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static bool decode_insn_reg2i14_fomat(union loongarch_instruction inst,
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struct instruction *insn,
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struct stack_op **ops_list,
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struct stack_op *op)
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{
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switch (inst.reg2i14_format.opcode) {
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case ldptrd_op:
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if (inst.reg2i14_format.rj == CFI_SP) {
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/* ldptr.d rd,sp,si14 */
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insn->immediate = sign_extend64(inst.reg2i14_format.immediate, 13);
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ADD_OP(op) {
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op->src.type = OP_SRC_REG_INDIRECT;
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op->src.reg = CFI_SP;
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op->src.offset = insn->immediate;
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op->dest.type = OP_DEST_REG;
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op->dest.reg = inst.reg2i14_format.rd;
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}
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}
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break;
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case stptrd_op:
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if (inst.reg2i14_format.rj == CFI_SP) {
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/* stptr.d ra,sp,0 */
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if (inst.reg2i14_format.rd == LOONGARCH_GPR_RA &&
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inst.reg2i14_format.immediate == 0)
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break;
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/* stptr.d rd,sp,si14 */
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insn->immediate = sign_extend64(inst.reg2i14_format.immediate, 13);
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ADD_OP(op) {
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op->src.type = OP_SRC_REG;
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op->src.reg = inst.reg2i14_format.rd;
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op->dest.type = OP_DEST_REG_INDIRECT;
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op->dest.reg = CFI_SP;
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op->dest.offset = insn->immediate;
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}
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}
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break;
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default:
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return false;
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}
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return true;
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}
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static bool decode_insn_reg2i16_fomat(union loongarch_instruction inst,
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struct instruction *insn)
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{
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switch (inst.reg2i16_format.opcode) {
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case jirl_op:
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if (inst.reg2i16_format.rd == 0 &&
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inst.reg2i16_format.rj == CFI_RA &&
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inst.reg2i16_format.immediate == 0) {
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/* jirl r0,ra,0 */
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insn->type = INSN_RETURN;
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} else if (inst.reg2i16_format.rd == CFI_RA) {
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/* jirl ra,rj,offs16 */
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insn->type = INSN_CALL_DYNAMIC;
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} else if (inst.reg2i16_format.rd == CFI_A0 &&
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inst.reg2i16_format.immediate == 0) {
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/*
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* jirl a0,t0,0
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* this is a special case in loongarch_suspend_enter,
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* just treat it as a call instruction.
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*/
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insn->type = INSN_CALL_DYNAMIC;
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} else if (inst.reg2i16_format.rd == 0 &&
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inst.reg2i16_format.immediate == 0) {
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/* jirl r0,rj,0 */
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insn->type = INSN_JUMP_DYNAMIC;
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} else if (inst.reg2i16_format.rd == 0 &&
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inst.reg2i16_format.immediate != 0) {
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/*
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* jirl r0,t0,12
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* this is a rare case in JUMP_VIRT_ADDR,
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* just ignore it due to it is harmless for tracing.
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*/
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break;
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} else {
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/* jirl rd,rj,offs16 */
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insn->type = INSN_JUMP_UNCONDITIONAL;
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insn->immediate = sign_extend64(inst.reg2i16_format.immediate, 15);
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}
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break;
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case beq_op:
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case bne_op:
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case blt_op:
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case bge_op:
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case bltu_op:
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case bgeu_op:
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insn->type = INSN_JUMP_CONDITIONAL;
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insn->immediate = sign_extend64(inst.reg2i16_format.immediate, 15);
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break;
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default:
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return false;
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}
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return true;
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}
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int arch_decode_instruction(struct objtool_file *file, const struct section *sec,
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unsigned long offset, unsigned int maxlen,
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struct instruction *insn)
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{
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struct stack_op **ops_list = &insn->stack_ops;
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const struct elf *elf = file->elf;
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struct stack_op *op = NULL;
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union loongarch_instruction inst;
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if (!is_loongarch(elf))
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return -1;
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if (maxlen < LOONGARCH_INSN_SIZE)
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return 0;
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insn->len = LOONGARCH_INSN_SIZE;
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insn->type = INSN_OTHER;
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insn->immediate = 0;
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inst = *(union loongarch_instruction *)(sec->data->d_buf + offset);
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if (decode_insn_reg0i26_fomat(inst, insn))
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return 0;
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if (decode_insn_reg1i21_fomat(inst, insn))
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return 0;
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if (decode_insn_reg2i12_fomat(inst, insn, ops_list, op))
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return 0;
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if (decode_insn_reg2i14_fomat(inst, insn, ops_list, op))
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return 0;
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if (decode_insn_reg2i16_fomat(inst, insn))
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return 0;
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if (inst.word == 0)
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insn->type = INSN_NOP;
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else if (inst.reg0i15_format.opcode == break_op) {
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/* break */
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insn->type = INSN_BUG;
|
||||
} else if (inst.reg2_format.opcode == ertn_op) {
|
||||
/* ertn */
|
||||
insn->type = INSN_RETURN;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
const char *arch_nop_insn(int len)
|
||||
{
|
||||
return NULL;
|
||||
static u32 nop;
|
||||
|
||||
if (len != LOONGARCH_INSN_SIZE)
|
||||
WARN("invalid NOP size: %d\n", len);
|
||||
|
||||
nop = LOONGARCH_INSN_NOP;
|
||||
|
||||
return (const char *)&nop;
|
||||
}
|
||||
|
||||
const char *arch_ret_insn(int len)
|
||||
{
|
||||
return NULL;
|
||||
static u32 ret;
|
||||
|
||||
if (len != LOONGARCH_INSN_SIZE)
|
||||
WARN("invalid RET size: %d\n", len);
|
||||
|
||||
emit_jirl((union loongarch_instruction *)&ret, LOONGARCH_GPR_RA, LOONGARCH_GPR_ZERO, 0);
|
||||
|
||||
return (const char *)&ret;
|
||||
}
|
||||
|
||||
void arch_initial_func_cfi_state(struct cfi_init_state *state)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user