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pinctrl: rockchip: rename RK1108 to RV1108
Rockchip finally named the SOC as RV1108, so change it. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> [adapted rk1108 dtsi to keep bisectability] Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Andy Yan
Linus Walleij
parent
ab714cfb4e
commit
b9c6dcab26
@ -222,7 +222,7 @@
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};
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pinctrl: pinctrl {
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compatible = "rockchip,rk1108-pinctrl";
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compatible = "rockchip,rv1108-pinctrl";
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rockchip,grf = <&grf>;
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rockchip,pmu = <&pmugrf>;
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#address-cells = <1>;
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@ -59,7 +59,7 @@
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#define GPIO_LS_SYNC 0x60
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enum rockchip_pinctrl_type {
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RK1108,
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RV1108,
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RK2928,
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RK3066B,
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RK3188,
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@ -713,13 +713,13 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
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return ret;
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}
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#define RK1108_PULL_PMU_OFFSET 0x10
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#define RK1108_PULL_OFFSET 0x110
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#define RK1108_PULL_PINS_PER_REG 8
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#define RK1108_PULL_BITS_PER_PIN 2
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#define RK1108_PULL_BANK_STRIDE 16
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#define RV1108_PULL_PMU_OFFSET 0x10
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#define RV1108_PULL_OFFSET 0x110
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#define RV1108_PULL_PINS_PER_REG 8
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#define RV1108_PULL_BITS_PER_PIN 2
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#define RV1108_PULL_BANK_STRIDE 16
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static void rk1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
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static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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@ -728,27 +728,27 @@ static void rk1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
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/* The first 24 pins of the first bank are located in PMU */
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if (bank->bank_num == 0) {
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*regmap = info->regmap_pmu;
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*reg = RK1108_PULL_PMU_OFFSET;
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*reg = RV1108_PULL_PMU_OFFSET;
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} else {
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*reg = RK1108_PULL_OFFSET;
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*reg = RV1108_PULL_OFFSET;
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*regmap = info->regmap_base;
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/* correct the offset, as we're starting with the 2nd bank */
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*reg -= 0x10;
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*reg += bank->bank_num * RK1108_PULL_BANK_STRIDE;
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*reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
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}
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*reg += ((pin_num / RK1108_PULL_PINS_PER_REG) * 4);
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*bit = (pin_num % RK1108_PULL_PINS_PER_REG);
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*bit *= RK1108_PULL_BITS_PER_PIN;
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*reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
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*bit = (pin_num % RV1108_PULL_PINS_PER_REG);
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*bit *= RV1108_PULL_BITS_PER_PIN;
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}
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#define RK1108_DRV_PMU_OFFSET 0x20
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#define RK1108_DRV_GRF_OFFSET 0x210
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#define RK1108_DRV_BITS_PER_PIN 2
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#define RK1108_DRV_PINS_PER_REG 8
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#define RK1108_DRV_BANK_STRIDE 16
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#define RV1108_DRV_PMU_OFFSET 0x20
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#define RV1108_DRV_GRF_OFFSET 0x210
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#define RV1108_DRV_BITS_PER_PIN 2
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#define RV1108_DRV_PINS_PER_REG 8
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#define RV1108_DRV_BANK_STRIDE 16
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static void rk1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
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static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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@ -757,19 +757,19 @@ static void rk1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
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/* The first 24 pins of the first bank are located in PMU */
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if (bank->bank_num == 0) {
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*regmap = info->regmap_pmu;
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*reg = RK1108_DRV_PMU_OFFSET;
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*reg = RV1108_DRV_PMU_OFFSET;
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} else {
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*regmap = info->regmap_base;
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*reg = RK1108_DRV_GRF_OFFSET;
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*reg = RV1108_DRV_GRF_OFFSET;
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/* correct the offset, as we're starting with the 2nd bank */
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*reg -= 0x10;
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*reg += bank->bank_num * RK1108_DRV_BANK_STRIDE;
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*reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
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}
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*reg += ((pin_num / RK1108_DRV_PINS_PER_REG) * 4);
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*bit = pin_num % RK1108_DRV_PINS_PER_REG;
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*bit *= RK1108_DRV_BITS_PER_PIN;
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*reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
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*bit = pin_num % RV1108_DRV_PINS_PER_REG;
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*bit *= RV1108_DRV_BITS_PER_PIN;
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}
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#define RK2928_PULL_OFFSET 0x118
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@ -1271,7 +1271,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
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return !(data & BIT(bit))
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? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
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: PIN_CONFIG_BIAS_DISABLE;
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case RK1108:
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case RV1108:
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case RK3188:
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case RK3288:
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case RK3368:
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@ -1318,7 +1318,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
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spin_unlock_irqrestore(&bank->slock, flags);
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break;
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case RK1108:
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case RV1108:
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case RK3188:
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case RK3288:
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case RK3368:
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@ -1581,7 +1581,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
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pull == PIN_CONFIG_BIAS_DISABLE);
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case RK3066B:
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return pull ? false : true;
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case RK1108:
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case RV1108:
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case RK3188:
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case RK3288:
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case RK3368:
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@ -2700,7 +2700,7 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev)
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return 0;
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}
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static struct rockchip_pin_bank rk1108_pin_banks[] = {
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static struct rockchip_pin_bank rv1108_pin_banks[] = {
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PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU,
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@ -2710,15 +2710,15 @@ static struct rockchip_pin_bank rk1108_pin_banks[] = {
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PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
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};
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static struct rockchip_pin_ctrl rk1108_pin_ctrl = {
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.pin_banks = rk1108_pin_banks,
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.nr_banks = ARRAY_SIZE(rk1108_pin_banks),
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.label = "RK1108-GPIO",
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.type = RK1108,
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static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
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.pin_banks = rv1108_pin_banks,
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.nr_banks = ARRAY_SIZE(rv1108_pin_banks),
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.label = "RV1108-GPIO",
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.type = RV1108,
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.grf_mux_offset = 0x10,
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.pmu_mux_offset = 0x0,
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.pull_calc_reg = rk1108_calc_pull_reg_and_bit,
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.drv_calc_reg = rk1108_calc_drv_reg_and_bit,
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.pull_calc_reg = rv1108_calc_pull_reg_and_bit,
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.drv_calc_reg = rv1108_calc_drv_reg_and_bit,
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};
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static struct rockchip_pin_bank rk2928_pin_banks[] = {
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@ -2976,8 +2976,8 @@ static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
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};
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static const struct of_device_id rockchip_pinctrl_dt_match[] = {
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{ .compatible = "rockchip,rk1108-pinctrl",
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.data = (void *)&rk1108_pin_ctrl },
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{ .compatible = "rockchip,rv1108-pinctrl",
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.data = (void *)&rv1108_pin_ctrl },
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{ .compatible = "rockchip,rk2928-pinctrl",
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.data = (void *)&rk2928_pin_ctrl },
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{ .compatible = "rockchip,rk3036-pinctrl",
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