mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
synced 2025-01-15 02:05:33 +00:00
Merge branch 'edac-for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras.git
# Conflicts: # drivers/edac/i10nm_base.c
This commit is contained in:
commit
ba9abdf065
@ -13612,6 +13612,12 @@ S: Maintained
|
||||
F: Documentation/devicetree/bindings/thermal/loongson,ls2k-thermal.yaml
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F: drivers/thermal/loongson2_thermal.c
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LOONGSON EDAC DRIVER
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M: Zhao Qunqin <zhaoqunqin@loongson.cn>
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L: linux-edac@vger.kernel.org
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S: Maintained
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F: drivers/edac/loongson_edac.c
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LSILOGIC MPT FUSION DRIVERS (FC/SAS/SPI)
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M: Sathya Prakash <sathya.prakash@broadcom.com>
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M: Sreekanth Reddy <sreekanth.reddy@broadcom.com>
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|
@ -81,6 +81,7 @@ config LOONGARCH
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select BUILDTIME_TABLE_SORT
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select COMMON_CLK
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select CPU_PM
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select EDAC_SUPPORT
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select EFI
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select GENERIC_CLOCKEVENTS
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select GENERIC_CMOS_UPDATE
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|
@ -547,5 +547,13 @@ config EDAC_VERSAL
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Support injecting both correctable and uncorrectable errors
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for debugging purposes.
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config EDAC_LOONGSON
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tristate "Loongson Memory Controller"
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depends on LOONGARCH && ACPI
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help
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Support for error detection and correction on the Loongson
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family memory controller. This driver reports single bit
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errors (CE) only. Loongson-3A5000/3C5000/3D5000/3A6000/3C6000
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are compatible.
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endif # EDAC
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|
@ -86,3 +86,4 @@ obj-$(CONFIG_EDAC_DMC520) += dmc520_edac.o
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obj-$(CONFIG_EDAC_NPCM) += npcm_edac.o
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obj-$(CONFIG_EDAC_ZYNQMP) += zynqmp_edac.o
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obj-$(CONFIG_EDAC_VERSAL) += versal_edac.o
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obj-$(CONFIG_EDAC_LOONGSON) += loongson_edac.o
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|
@ -214,7 +214,7 @@ static int edac_mc_alloc_csrows(struct mem_ctl_info *mci)
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unsigned int row, chn;
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/*
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* Alocate and fill the csrow/channels structs
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* Allocate and fill the csrow/channels structs
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*/
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mci->csrows = kcalloc(tot_csrows, sizeof(*mci->csrows), GFP_KERNEL);
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if (!mci->csrows)
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|
@ -422,7 +422,7 @@ static inline int nr_pages_per_csrow(struct csrow_info *csrow)
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return nr_pages;
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}
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/* Create a CSROW object under specifed edac_mc_device */
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/* Create a CSROW object under specified edac_mc_device */
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static int edac_create_csrow_object(struct mem_ctl_info *mci,
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struct csrow_info *csrow, int index)
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{
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@ -449,7 +449,7 @@ static int edac_create_csrow_object(struct mem_ctl_info *mci,
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return 0;
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}
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|
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/* Create a CSROW object under specifed edac_mc_device */
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/* Create a CSROW object under specified edac_mc_device */
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static int edac_create_csrow_objects(struct mem_ctl_info *mci)
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{
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int err, i;
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@ -636,7 +636,7 @@ static void dimm_release(struct device *dev)
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*/
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}
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/* Create a DIMM object under specifed memory controller device */
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/* Create a DIMM object under specified memory controller device */
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static int edac_create_dimm_object(struct mem_ctl_info *mci,
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struct dimm_info *dimm)
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{
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|
@ -949,6 +949,7 @@ static const struct x86_cpu_id i10nm_cpuids[] = {
|
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X86_MATCH_VFM(INTEL_GRANITERAPIDS_X, &gnr_cfg),
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X86_MATCH_VFM(INTEL_ATOM_CRESTMONT_X, &gnr_cfg),
|
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X86_MATCH_VFM(INTEL_ATOM_CRESTMONT, &gnr_cfg),
|
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X86_MATCH_VFM(INTEL_ATOM_DARKMONT_X, &gnr_cfg),
|
||||
{}
|
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};
|
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MODULE_DEVICE_TABLE(x86cpu, i10nm_cpuids);
|
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@ -1011,7 +1012,7 @@ static struct notifier_block i10nm_mce_dec = {
|
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|
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static int __init i10nm_init(void)
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{
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u8 mc = 0, src_id = 0, node_id = 0;
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u8 mc = 0, src_id = 0;
|
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const struct x86_cpu_id *id;
|
||||
struct res_config *cfg;
|
||||
const char *owner;
|
||||
@ -1071,11 +1072,7 @@ static int __init i10nm_init(void)
|
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if (rc < 0)
|
||||
goto fail;
|
||||
|
||||
rc = skx_get_node_id(d, &node_id);
|
||||
if (rc < 0)
|
||||
goto fail;
|
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|
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edac_dbg(2, "src_id = %d node_id = %d\n", src_id, node_id);
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edac_dbg(2, "src_id = %d\n", src_id);
|
||||
for (i = 0; i < imc_num; i++) {
|
||||
if (!d->imc[i].mdev)
|
||||
continue;
|
||||
@ -1083,7 +1080,6 @@ static int __init i10nm_init(void)
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||||
d->imc[i].mc = mc++;
|
||||
d->imc[i].lmc = i;
|
||||
d->imc[i].src_id = src_id;
|
||||
d->imc[i].node_id = node_id;
|
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if (d->imc[i].hbm_mc) {
|
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d->imc[i].chan_mmio_sz = cfg->hbm_chan_mmio_sz;
|
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d->imc[i].num_channels = cfg->hbm_chan_num;
|
||||
|
@ -338,11 +338,11 @@ struct i5000_pvt {
|
||||
|
||||
u16 mir0, mir1, mir2;
|
||||
|
||||
u16 b0_mtr[NUM_MTRS]; /* Memory Technlogy Reg */
|
||||
u16 b0_mtr[NUM_MTRS]; /* Memory Technology Reg */
|
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u16 b0_ambpresent0; /* Branch 0, Channel 0 */
|
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u16 b0_ambpresent1; /* Brnach 0, Channel 1 */
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||||
u16 b0_ambpresent1; /* Branch 0, Channel 1 */
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u16 b1_mtr[NUM_MTRS]; /* Memory Technlogy Reg */
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u16 b1_mtr[NUM_MTRS]; /* Memory Technology Reg */
|
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u16 b1_ambpresent0; /* Branch 1, Channel 8 */
|
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u16 b1_ambpresent1; /* Branch 1, Channel 1 */
|
||||
|
||||
@ -1210,7 +1210,7 @@ static void i5000_get_mc_regs(struct mem_ctl_info *mci)
|
||||
&pvt->b0_ambpresent1);
|
||||
edac_dbg(2, "\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1);
|
||||
|
||||
/* Only if we have 2 branchs (4 channels) */
|
||||
/* Only if we have 2 branches (4 channels) */
|
||||
if (pvt->maxch < CHANNELS_PER_BRANCH) {
|
||||
pvt->b1_ambpresent0 = 0;
|
||||
pvt->b1_ambpresent1 = 0;
|
||||
|
157
drivers/edac/loongson_edac.c
Normal file
157
drivers/edac/loongson_edac.c
Normal file
@ -0,0 +1,157 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2024 Loongson Technology Corporation Limited.
|
||||
*/
|
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|
||||
#include <linux/acpi.h>
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#include <linux/edac.h>
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#include <linux/init.h>
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||||
#include <linux/io-64-nonatomic-lo-hi.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include "edac_module.h"
|
||||
|
||||
#define ECC_CS_COUNT_REG 0x18
|
||||
|
||||
struct loongson_edac_pvt {
|
||||
void __iomem *ecc_base;
|
||||
|
||||
/*
|
||||
* The ECC register in this controller records the number of errors
|
||||
* encountered since reset and cannot be zeroed so in order to be able
|
||||
* to report the error count at each check, this records the previous
|
||||
* register state.
|
||||
*/
|
||||
int last_ce_count;
|
||||
};
|
||||
|
||||
static int read_ecc(struct mem_ctl_info *mci)
|
||||
{
|
||||
struct loongson_edac_pvt *pvt = mci->pvt_info;
|
||||
u64 ecc;
|
||||
int cs;
|
||||
|
||||
ecc = readq(pvt->ecc_base + ECC_CS_COUNT_REG);
|
||||
/* cs0 -- cs3 */
|
||||
cs = ecc & 0xff;
|
||||
cs += (ecc >> 8) & 0xff;
|
||||
cs += (ecc >> 16) & 0xff;
|
||||
cs += (ecc >> 24) & 0xff;
|
||||
|
||||
return cs;
|
||||
}
|
||||
|
||||
static void edac_check(struct mem_ctl_info *mci)
|
||||
{
|
||||
struct loongson_edac_pvt *pvt = mci->pvt_info;
|
||||
int new, add;
|
||||
|
||||
new = read_ecc(mci);
|
||||
add = new - pvt->last_ce_count;
|
||||
pvt->last_ce_count = new;
|
||||
if (add <= 0)
|
||||
return;
|
||||
|
||||
edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, add,
|
||||
0, 0, 0, 0, 0, -1, "error", "");
|
||||
}
|
||||
|
||||
static void dimm_config_init(struct mem_ctl_info *mci)
|
||||
{
|
||||
struct dimm_info *dimm;
|
||||
u32 size, npages;
|
||||
|
||||
/* size not used */
|
||||
size = -1;
|
||||
npages = MiB_TO_PAGES(size);
|
||||
|
||||
dimm = edac_get_dimm(mci, 0, 0, 0);
|
||||
dimm->nr_pages = npages;
|
||||
snprintf(dimm->label, sizeof(dimm->label),
|
||||
"MC#%uChannel#%u_DIMM#%u", mci->mc_idx, 0, 0);
|
||||
dimm->grain = 8;
|
||||
}
|
||||
|
||||
static void pvt_init(struct mem_ctl_info *mci, void __iomem *vbase)
|
||||
{
|
||||
struct loongson_edac_pvt *pvt = mci->pvt_info;
|
||||
|
||||
pvt->ecc_base = vbase;
|
||||
pvt->last_ce_count = read_ecc(mci);
|
||||
}
|
||||
|
||||
static int edac_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct edac_mc_layer layers[2];
|
||||
struct mem_ctl_info *mci;
|
||||
void __iomem *vbase;
|
||||
int ret;
|
||||
|
||||
vbase = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(vbase))
|
||||
return PTR_ERR(vbase);
|
||||
|
||||
layers[0].type = EDAC_MC_LAYER_CHANNEL;
|
||||
layers[0].size = 1;
|
||||
layers[0].is_virt_csrow = false;
|
||||
layers[1].type = EDAC_MC_LAYER_SLOT;
|
||||
layers[1].size = 1;
|
||||
layers[1].is_virt_csrow = true;
|
||||
mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
|
||||
sizeof(struct loongson_edac_pvt));
|
||||
if (mci == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
mci->mc_idx = edac_device_alloc_index();
|
||||
mci->mtype_cap = MEM_FLAG_RDDR4;
|
||||
mci->edac_ctl_cap = EDAC_FLAG_NONE;
|
||||
mci->edac_cap = EDAC_FLAG_NONE;
|
||||
mci->mod_name = "loongson_edac.c";
|
||||
mci->ctl_name = "loongson_edac_ctl";
|
||||
mci->dev_name = "loongson_edac_dev";
|
||||
mci->ctl_page_to_phys = NULL;
|
||||
mci->pdev = &pdev->dev;
|
||||
mci->error_desc.grain = 8;
|
||||
mci->edac_check = edac_check;
|
||||
|
||||
pvt_init(mci, vbase);
|
||||
dimm_config_init(mci);
|
||||
|
||||
ret = edac_mc_add_mc(mci);
|
||||
if (ret) {
|
||||
edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
|
||||
edac_mc_free(mci);
|
||||
return ret;
|
||||
}
|
||||
edac_op_state = EDAC_OPSTATE_POLL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void edac_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct mem_ctl_info *mci = edac_mc_del_mc(&pdev->dev);
|
||||
|
||||
if (mci)
|
||||
edac_mc_free(mci);
|
||||
}
|
||||
|
||||
static const struct acpi_device_id loongson_edac_acpi_match[] = {
|
||||
{"LOON0010", 0},
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(acpi, loongson_edac_acpi_match);
|
||||
|
||||
static struct platform_driver loongson_edac_driver = {
|
||||
.probe = edac_probe,
|
||||
.remove = edac_remove,
|
||||
.driver = {
|
||||
.name = "loongson-mc-edac",
|
||||
.acpi_match_table = loongson_edac_acpi_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(loongson_edac_driver);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("Zhao Qunqin <zhaoqunqin@loongson.cn>");
|
||||
MODULE_DESCRIPTION("EDAC driver for loongson memory controller");
|
@ -600,7 +600,7 @@ static int __init skx_init(void)
|
||||
const struct munit *m;
|
||||
const char *owner;
|
||||
int rc = 0, i, off[3] = {0xd0, 0xd4, 0xd8};
|
||||
u8 mc = 0, src_id, node_id;
|
||||
u8 mc = 0, src_id;
|
||||
struct skx_dev *d;
|
||||
|
||||
edac_dbg(2, "\n");
|
||||
@ -650,15 +650,12 @@ static int __init skx_init(void)
|
||||
rc = skx_get_src_id(d, 0xf0, &src_id);
|
||||
if (rc < 0)
|
||||
goto fail;
|
||||
rc = skx_get_node_id(d, &node_id);
|
||||
if (rc < 0)
|
||||
goto fail;
|
||||
edac_dbg(2, "src_id=%d node_id=%d\n", src_id, node_id);
|
||||
|
||||
edac_dbg(2, "src_id = %d\n", src_id);
|
||||
for (i = 0; i < SKX_NUM_IMC; i++) {
|
||||
d->imc[i].mc = mc++;
|
||||
d->imc[i].lmc = i;
|
||||
d->imc[i].src_id = src_id;
|
||||
d->imc[i].node_id = node_id;
|
||||
rc = skx_register_mci(&d->imc[i], d->imc[i].chan[0].cdev,
|
||||
"Skylake Socket", EDAC_MOD_STR,
|
||||
skx_get_dimm_config, cfg);
|
||||
|
@ -19,6 +19,7 @@
|
||||
#include <linux/adxl.h>
|
||||
#include <acpi/nfit.h>
|
||||
#include <asm/mce.h>
|
||||
#include <asm/uv/uv.h>
|
||||
#include "edac_module.h"
|
||||
#include "skx_common.h"
|
||||
|
||||
@ -221,10 +222,42 @@ void skx_set_decode(skx_decode_f decode, skx_show_retry_log_f show_retry_log)
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(skx_set_decode);
|
||||
|
||||
static int skx_get_pkg_id(struct skx_dev *d, u8 *id)
|
||||
{
|
||||
int node;
|
||||
int cpu;
|
||||
|
||||
node = pcibus_to_node(d->util_all->bus);
|
||||
if (numa_valid_node(node)) {
|
||||
for_each_cpu(cpu, cpumask_of_pcibus(d->util_all->bus)) {
|
||||
struct cpuinfo_x86 *c = &cpu_data(cpu);
|
||||
|
||||
if (c->initialized && cpu_to_node(cpu) == node) {
|
||||
*id = c->topo.pkg_id;
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
skx_printk(KERN_ERR, "Failed to get package ID from NUMA information\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
int skx_get_src_id(struct skx_dev *d, int off, u8 *id)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
/*
|
||||
* The 3-bit source IDs in PCI configuration space registers are limited
|
||||
* to 8 unique IDs, and each ID is local to a UPI/QPI domain.
|
||||
*
|
||||
* Source IDs cannot be used to map devices to sockets on UV systems
|
||||
* because they can exceed 8 sockets and have multiple UPI/QPI domains
|
||||
* with identical, repeating source IDs.
|
||||
*/
|
||||
if (is_uv_system())
|
||||
return skx_get_pkg_id(d, id);
|
||||
|
||||
if (pci_read_config_dword(d->util_all, off, ®)) {
|
||||
skx_printk(KERN_ERR, "Failed to read src id\n");
|
||||
return -ENODEV;
|
||||
@ -235,20 +268,6 @@ int skx_get_src_id(struct skx_dev *d, int off, u8 *id)
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(skx_get_src_id);
|
||||
|
||||
int skx_get_node_id(struct skx_dev *d, u8 *id)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
if (pci_read_config_dword(d->util_all, 0xf4, ®)) {
|
||||
skx_printk(KERN_ERR, "Failed to read node id\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
*id = GET_BITFIELD(reg, 0, 2);
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(skx_get_node_id);
|
||||
|
||||
static int get_width(u32 mtr)
|
||||
{
|
||||
switch (GET_BITFIELD(mtr, 8, 9)) {
|
||||
@ -507,7 +526,7 @@ int skx_register_mci(struct skx_imc *imc, struct pci_dev *pdev,
|
||||
pvt->imc = imc;
|
||||
|
||||
mci->ctl_name = kasprintf(GFP_KERNEL, "%s#%d IMC#%d", ctl_name,
|
||||
imc->node_id, imc->lmc);
|
||||
imc->src_id, imc->lmc);
|
||||
if (!mci->ctl_name) {
|
||||
rc = -ENOMEM;
|
||||
goto fail0;
|
||||
|
@ -103,7 +103,7 @@ struct skx_dev {
|
||||
bool hbm_mc;
|
||||
u8 mc; /* system wide mc# */
|
||||
u8 lmc; /* socket relative mc# */
|
||||
u8 src_id, node_id;
|
||||
u8 src_id;
|
||||
struct skx_channel {
|
||||
struct pci_dev *cdev;
|
||||
struct pci_dev *edev;
|
||||
@ -244,7 +244,6 @@ void skx_set_mem_cfg(bool mem_cfg_2lm);
|
||||
void skx_set_res_cfg(struct res_config *cfg);
|
||||
|
||||
int skx_get_src_id(struct skx_dev *d, int off, u8 *id);
|
||||
int skx_get_node_id(struct skx_dev *d, u8 *id);
|
||||
|
||||
int skx_get_all_bus_mappings(struct res_config *cfg, struct list_head **list);
|
||||
|
||||
|
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Reference in New Issue
Block a user